JPH07121990A - Signal reproducing method and signal reproducer - Google Patents

Abstract

PURPOSE:To obtain a data reproducer adapted for a digital VTR. CONSTITUTION:A partial response equalization detection (PR (1, 0, -1)) signal is output through switching circuits 204, 220 in a normal reproducing mode of a digital VTR. This is because the PR (1, 0, -1) signal is stable and highly accurate in the normal reproducing mode. In a variable speed reproducing mode, an integration detection signal is selected by the circuit 204, and output from the circuit 220 through a demodulator 210 of interleave NRZI modulation having D-FFs 212, 214 and an exclusive OR circuit 216. This is because the integration detection mode is more stable in the variable speed reproducing mode. A clock reproducer 206 reproduces a clock based on a PLL system from the integration detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing method and a signal reproducing circuit, and more particularly to signal reproducing in a magnetic recording / reproducing apparatus such as a video signal recording / reproducing apparatus (VTR). INDUSTRIAL APPLICABILITY The present invention can be suitably used especially for a digital video reproducing apparatus using both a highly accurate and stable partial response equalization detection method in normal reproduction and a stable integral detection method in variable speed reproduction (picture search).

The magnetic recording / reproducing apparatus includes, for example, an analog system for recording and reproducing a video signal in an analog manner and a digital system for recording and reproducing a video signal in a digital manner. It is used for consumer use, and the digital method is used exclusively for business purposes that require high accuracy. Integral detection, peak detection, and partial response detection are known as detection methods for the digital VTR. These will be described in detail later.

This digital VTR is equipped with a rotary head for performing a helical scan, and a digital recording signal, for example, a digital video signal is converted into a pulse signal and then provided on the rotary head via a rotary transformer. It is applied to the head and recorded on the magnetic tape. Up to now, since the DC component of the video signal is cut off by the rotary transformer, in the case of the pulse code including the DC component, the current level provided in the rotary head fluctuates depending on the arrangement state of this code, and the digital magnetic recording / reproducing apparatus. It was difficult to identify the code in the decoding circuit in. Therefore, as a recent trend, the partial response class 4 used in communication, that is, (1,
It has been proposed to detect a code by using a partial response method of 0, -1) type.

This permanent response (1,0,-
1) method (hereinafter, referred to as PR (1, 0, -1) method) will be described with reference to the waveform diagrams of FIGS. 4 and 5A to 5D. FIG. 4 is a configuration diagram of a PR (1, 0, -1) system circuit (PR signal processing circuit). The digital signal “1011010010 ...” Shown in FIG. 5A is converted into an NRZ code and applied to the digital signal input terminal of the PR signal processing circuit shown in FIG. The pulse signal waveform converted into the NRZ code is shown in FIG. This NRZ code has a pulse waveform of "+1" level when the digital signal is "1",
When the digital signal is "0", it is a waveform code represented as a "0" level pulse waveform. This NRZ code is PR
It is input to the precoder 52 of the signal processing circuit and precoded. The precoder 52 is a modulo 2 (mod
2) It is composed of an adder 53 and a delay circuit 54 that delays by 2 time slots (2T).
The NRZ code is precoded by the precoder output from the delay circuit 54 delayed by 2T and addition based on mod 2 by the adder 53. The waveform of the precoded pulse signal is shown in FIG. Precoder 5
In the case of the transmission line 55 and the digital VTR, the pulse signal output of 2 is transmitted through the magnetic tape. While passing through the transmission path 55, deterioration of the pulse signal occurs particularly in a high frequency band. This signal deterioration becomes more noticeable as the data transmission rate increases, and interference between the codes increases, which causes a code identification error on the decoding side. Therefore, a pre-equalizer 56 is provided at the receiving end to compensate the phase and frequency characteristics of the pulse signal so that the frequency characteristics of the pulse signal transmitted through the transmission path 55 satisfy the Nyquist frequency condition. The pulse signal pre-equalized by the pre-equalizer 56 is decoded by the decoder 57. Decoder 57
Is a delay circuit 5 that delays the output from the pre-equalizer 56 by 2T.
9 and a subtracter 58 for subtracting the output signal delayed by the delay circuit 59 from the output signal of the pre-equalizer 56. The output of the decoder 57 which is the output of the subtractor 58 is "+1", "0" and "-" as shown in FIG.
The pulse waveform has three values of "1". The pulse waveform of "+1" and the pulse waveform of "-1" correspond to the pulse of "+1" of the pulse waveform of the NRZ code.
When the code identifying circuit 60 identifies the pulse waveforms of "1" and "-1" as "1", the original digital signal can be decoded.

It should be noted that the decoder 57 is set to PR as described above.
With the configuration using the (1, 0, -1) system, the noise increased by the pre-equalizer 56, and when the transmission line 55 is a magnetic recording medium such as a magnetic tape, the output from the transmission line 55 is Since the differential waveform is obtained and the DC component is cut off, it is possible to reduce code identification errors caused by noise in the low frequency region increased by the pre-equalization circuit 56 compensating for this. Because of this advantage, in particular PR (1,
Applying the 0, -1) method to a digital VTR is being promoted.

The above is the basic circuit of the partial response equalization detection circuit, but various improvement measures have been taken.
Some of them are described below. In the PR (1, 0, -1) method, since a ternary pulse signal is handled, its eye pattern becomes complicated as shown in FIG. In other words, when the pulse signal changes from "+1" level to "0" level, 1
When making a step transition and when changing from "+1" level to "-
The width of the identification window, which is the lateral opening of the eye pattern, is different from the case where the transition is made in two steps when changing to the "1" level. This means that the data obtained by slicing the central portion of the eye pattern at the slice level indicated by the broken line contains jitter. Therefore, when the sliced data waveform is used as data for clock extraction, it becomes a clock pulse including jitter.

In order to solve this problem, as shown in FIG. 7, separate equalization circuits are used for a clock extraction circuit system and a digital signal reproduction system. FIG. 7 is a circuit diagram of the PR signal processing circuit 100B. A pulse signal reproduced by a reproducing head 100 from a magnetic tape (not shown) in a differential waveform is amplified by a reproducing amplifier 101 and then input to a pre-equalization circuit 103 via a rotary transformer 102. The pre-equalization circuit 103 is the pre-equalization circuit 5 shown in FIG.
6 performs the same function as 6 and compensates the phase and frequency characteristics of the pulse signal and also compensates for the interruption of the DC component. The pre-equalized pulse signal is sliced by the identification circuit 105 via the integral equalization circuit 104 to extract a clock. The pre-equalized pulse signal is equalized by the equalizing circuit 106 of the PR (1, 0, -1) system, and then the delay circuit 10 for timing adjustment is used.
The signal is sliced by the code identification circuit 108 via 7 and decoded into a digital signal.

The integral equalization circuit 104 includes a reproducing head 100.
Since the signal reproduced from has a differential characteristic, it is inversely corrected by the integrating circuit and restored to the same data as the signal recorded on the magnetic tape. Since the integration equalization circuit 104 is an equalization system that has less jitter depending on the code pattern, the clock extracted from the data equalized by the integration equalization circuit 104 has less jitter. The integral equalization circuit 104 directly associates “1” with “1” and “0” with “0”, but in this case, in order to prevent interference (intersymbol interference) in discrimination of other codes, , Are equalized so that the amplitude at the time of identifying other codes becomes zero. Therefore, the equalization circuit 104 performs equalization (hereinafter referred to as Nyquist equalization) for obtaining a response waveform that satisfies the Nyquist theorem.

When decoding a digital signal, in order to reduce code errors due to noise that increases in the pre-equalization circuit 103, the equalization circuit 106 of the PR (1,0, -1) system is used.
Is used. The PR (1,0, -1) method is shown in FIG.
As shown in (B), for the recording code of "1", "1,"
0, -1 "and 3 bits are made to respond. Let r (t) be the response waveform that satisfies the Nyquist theorem,
The response waveform pr (t) of the PR (1,0, −1) method can be expressed by the following equation 1.

[0010]

[Equation 1]

Fourier transform of equation 1 yields equation 2 below, and further transformation yields equation 3 below.

[0012]

[Equation 2]

[0013]

[Equation 3]

Referring to Equation 3, by multiplying R (ω), which is a characteristic satisfying the Nyquist theorem, by a transfer function of jsin (ωT), a response of PR (1,0, -1) is obtained. I understand. However, as shown in FIG. 7, when equalization is performed by two separate equalization circuits, although clock jitter is reduced, two equalization circuits having different configurations are required, and each equalization circuit is different. Since the propagation delay time due to is different, the timing adjustment delay circuit 107 for matching the time of the clock and the digital signal
Is required. The timing adjusting delay circuit 107 must be adjusted so that the clock and the digital signal are matched in time. If two equalizer circuits are provided independently and a circuit that adjusts the propagation delay time difference between them is provided, the circuit scale, cost, and power consumption increase, and it is necessary to adjust the adjustment of the delay time for each circuit. . Further, the deviation of the adjustment adjustment value due to the temperature fluctuation and the temporal change becomes a problem, and the performance deterioration of the digital magnetic recording / reproducing apparatus in the market is expected. Therefore, the applicant of the present invention further improved this. The circuit configuration is shown in FIG.

PR signal processing circuit 100C shown in FIG.
Devises an equalizer circuit so that one equalizer circuit 110 can perform integral equalization and PR (1,0, -1) equalization. That is, the pre-equalization circuit 1 that performs Nyquist equalization
03 is provided in the preceding stage, the delay circuit is driven by a signal source having the characteristic impedance of the delay circuit in which the output terminal having a predetermined delay time is short-circuited, and the output current is taken out from the short-circuited output terminal of the delay circuit to perform integration, etc. The converted data is extracted and PR is performed from the voltage signal at the input terminal of the delay circuit.
The data that has been equalized by the (1, 0, -1) method is extracted. In this way, common equalization circuits are used for integral equalization and PR.
Equalization by the (1,0, -1) method is performed. This allows
It is not necessary to provide the timing adjustment circuit for the propagation delay time difference described above. Further, since the phase difference does not occur in principle, it is possible to eliminate the need to consider factors such as variations, temperature characteristics, changes over time, and adjustment errors. Further, it is possible to reduce the manufacturing cost without requiring a complicated adjustment for adjusting the phase difference.

More specifically, the pre-equalization circuit 10 will be described.
3 performs equalization to obtain a response waveform that satisfies the Nyquist theorem. The output equalized by the pre-equalization circuit 103 is applied to the common equalization circuit 110, the integrated and equalized pulse signal is output to the identification circuit 105, and a clock is extracted by being sliced and extracted. The recovered clock is output from the output terminal a. The output equalized by the PR (1,0, -1) method in the common equalization circuit 110 is applied to the code identification circuit 108, sliced therein to be decoded into the original digital signal, and output from the output terminal b. Is output. Then, using the reproduced clock output from the output terminal a, signal processing such as sampling the digital signal output from the output terminal b is performed in a subsequent circuit (not shown).

[0017]

The partial response equalization detection method is essentially a method suitable for a digital VTR, and as described above, various improvement measures have been taken to improve it. There is a problem of lack of stability with respect to the speed data rate. Specifically, when performing variable speed reproduction (picture search) in a digital VTR, there is a problem that the partial response equalization detection method cannot perform sufficiently accurate decoding. That is, as shown in the graph of the reproduction RF signal in FIG. 9, since the reproduction head obliquely crosses the reverse azimuth track and the guard band, the reproduction RF signal becomes discontinuous and its envelope has a triangular (abacus ball) waveform. become. As can be seen from FIG. 9, in such a state, the amplitude of the reproduction RF signal is accompanied by an extremely large amplitude variation from the state of almost no signal to the maximum value (vertex of the triangle). Assuming that a partial response equalization detection method that is stable even with such data rate fluctuations is configured, it is expected that the circuit configuration will be extremely complicated. That is, in the case where the reproduction bit rate changes according to the tape speed, such as the variable speed reproduction of the digital VTR, the null in the Nyquist characteristic is used.
Point must be changed according to tape speed. Usually, this Null Point is composed of a combination of a delay line and an adder, and the frequency of the Null Point is determined by the delay amount of the delay line. Therefore, in order to control this, the delay amount of the delay line is controlled, which is extremely difficult to realize.

On the other hand, the reproduced signal is A / D converted as it is,
There is a method of performing PR detection in the digital domain. (For example, digital β cam.) In this case, since the 2T delay required for PR equalization can be realized by the delay circuit including the shift register, the delay amount always follows the reproduced clock frequency, and the above problem does not occur. . The eye pattern characteristics are shown in FIG. However, for this,
A high-speed A / D converter and digital arithmetic circuit are required,
In particular, a high-definition digital VTR, which requires recording / reproduction at a high recording rate, requires an ultra-high-speed digital processing circuit, which has been a major obstacle in terms of power consumption, cost, and circuit scale.

Therefore, the present invention has a relatively simple circuit configuration and utilizes the characteristics of the partial response equalization detection method in the steady operation state, while also making it possible to perform stable decoding even at a variable data rate. An object is to provide a recording / reproducing device.

[0020]

According to the present invention, a partial response (PR) equalization detection method and an integral detection method are used separately. That is, in the present invention, (1) the PR equalization detection method that is excellent in S / N and crosstalk characteristics is used during normal reproduction, and (2) the integral detection method that is resistant to fluctuations in the data rate is used during variable speed reproduction. . As a result, it is not necessary for the PR equalization detection method, which is sensitive to fluctuations in the data rate, to follow the reproduction rate that changes according to the magnetic tape speed, and the integral detection method is configured with extremely high accuracy for normal reproduction. There is no need to do it. As a result, the best reproduction state can always be ensured with a simple circuit configuration. More preferably, in addition to switching by the reproduction mode (normal / shuttle), the reproduction error rate is also referred to, and the optimum detection method of either PR equalization detection method or integral detection is selected to perform equalization reproduction. To do.

Therefore, according to the present invention, the transmission data rate of the received signal is monitored, the partial response detection signal is selected when the data transmission rate is substantially constant, and the partial response detection signal is selected when the data transmission rate changes. There is provided a signal reproduction method for selecting an integral detection signal, extracting a clock signal using these selected signals, and reproducing received transmission data using the extracted clock signal. Preferably, the reproduction error rate of the transmission data is monitored, and the partial response detection signal or the integral detection signal is selected by also referring to the error rate. More preferably, EE
When the signal is selected, the output with the partial response characteristic compensated is output. Specifically, the transmission data is a signal read from a magnetic tape in a digital magnetic recording / reproducing apparatus. Preferably, the partial response is a PR (1,0, -1) system.

Further, according to the present invention, the first switching means for selectively outputting the partial response signal and the integral detection signal, the clock regenerating means for regenerating a clock from the integral detection signal, and the partial response equalizing means. A second switching means for selectively outputting an output signal of the partial response equalization means and a signal before the partial response equalization means, and energizing the first and second switching means. Switching control means, the switching control means, in the first operation mode, the partial response signal is output from the second switching means at a timing according to the recovered clock from the clock recovery means, In the second operation mode, based on the recovered clock from the clock recovery means, There signal reproducing circuit for outputting an output from said second switching means to apply the integration detection signal to the partial response equalization means is provided.

Preferably, the apparatus further comprises means for monitoring the data output from the reproduction clock and the second switching means, and the monitoring means, when the error rate of the monitored data falls below a predetermined level. , Operating the switching control means to reverse the biasing positions of the first and second switching means.

Specifically, the signal reproducing circuit is used as a decoding circuit of a digital magnetic recording / reproducing apparatus, and the first operation mode is a normal reproduction mode and the second operation mode is a variable speed reproduction mode. is there. Also preferably, E
A third switching means for selectively outputting the -E signal and the integral detection signal, wherein the switching control means, in the EE mode, the EE signal is transmitted through the partial response equalization means. The first to third switching means are energized to be output.

Further, preferably, the partial response signal is a PR (1, 0, -1) signal, and the partial response equalizing means is an equalizer corresponding to the PR (1, 0, -1) system. It has a circuit.

[0026]

When the data rate of the received signal is constant, the partial response equalization detection signal is used for reproduction, and when the data rate changes, the integral detection signal is used for reproduction. Further, the error rate of the reproduced data is monitored, and even if the data rate is fixed, the method using the integral detection signal is switched.

[0027]

1 is a circuit configuration diagram of a signal reproducing circuit 200 applied to a digital magnetic recording / reproducing apparatus (VTR) as a first embodiment of a signal reproducing circuit of the present invention. Before describing the details of the signal reproducing circuit 200, the features of the digital VTR will be described. In the digital VTR, DT (Dyna
Mic Tracking) Noiseless slow playback is possible without using a head. In the case of such slow reproduction, the reproduction head diagonally crosses the reverse azimuth track and the guard band, and the reproduction RF signal is as shown in FIG.
As illustrated in, it becomes choppy. By collecting intermittent reproduction data and restoring the original correct data by signal processing, noiseless slow reproduction is possible without the DT head. The envelope of the choppy playback PR signal is a triangular waveform,
The amplitude greatly changes depending on the positional relationship between the reproducing head and the recording track. On the other hand, in the PR (1, 0, -1) system, the equalized waveform is a ternary signal, so as illustrated in FIG.
The detection level requires two threshold values of "+" and "-". It is necessary to set the two threshold values between the plus / minus peak values and the zero level, and it is required to accurately follow the envelope of the reproduced PR signal.

On the other hand, the equalized waveform of the integral detection method is a binary signal as shown in FIG. 10, and the detection level is only at one point of the zero cross at the center. Therefore, a large reproduction P
It is not necessary to make the detection level follow the fluctuation of the R signal amplitude at all, and extremely strong detection of the amplitude fluctuation is possible. Therefore, in the case of the detection in which the reproduction RF signal amplitude fluctuates significantly, it is possible to perform detection with less errors by switching to integral detection that is more resistant to amplitude fluctuation than detection by the PR method. When fast-forwarding and rewinding in the variable speed playback mode, the tape speed changes significantly compared to standard playback. For this reason, the data rate of the reproduced digital signal greatly changes in accordance with the tape speed unless measures such as controlling the reverse correction based on the rotational speed of the magnetic head drum are taken. If the data rate changes, the equalization characteristic (transmission characteristic of the equalization circuit) required accordingly also changes. As mentioned above, PR
In the (1,0, -1) system, for the signal of "1",
This is a method of detecting "1, 0, -1" by responding over 3 bits. As a way to achieve this, in general,
A method of inverting and adding a signal obtained by delaying the response of "1" by 2T (T is the time of one time slot) is adopted.
Therefore, the equalization characteristic required for the PR (1,0, -1) system is closely related to the time slot depending on the data rate, and it becomes difficult for a fixed circuit to cope with a large change in the reproduction data rate. . Furthermore, in the PR (1, 0, -1) system, the detection signal has three values, and +1 to -1 (or -1
Since there is a direct code transition from +1 to +1), the detection window width becomes narrower than in integral detection. As a result, the timing margin decreases, the data rate increases due to fast-forwarding and rewinding, and the detection window width decreases, which is a great disadvantage. Therefore, when data detection is required during fast-forwarding and rewinding such as in the picture search, the detection is switched to integral detection that has a wider detection window width and is more resistant to frequency fluctuation than detection by the PR method, which has a relatively narrow detection window width. It is possible to detect with less error. As described above, PR (1,
The 0, -1) system has various characteristics such as strong low-frequency cutoff, excellent crosstalk characteristics, and good S / N ratio. Therefore, in the normal reproduction mode, by selecting the PR (1, 0, -1) system, it is possible to perform reproduction detection with higher reliability and realize higher density recording and reproduction.

However, various state changes are expected even in the normal reproduction mode. For example, increase in dropout due to damage or deterioration of the recording tape, increase in spacing loss and track deviation due to aging of the head and tape running system, amplitude fluctuation (contact fluctuation) of the reproduction RF signal caused by decoding thereof, etc. Is. If such a symptom becomes conspicuous, it may not be possible to fully utilize the advantages of the PR (1,0, -1) method. In some cases, integral detection results in fewer errors. There is also the possibility of becoming a system. Therefore, it is possible to always maintain the optimum reproduction state by selecting the detection method according to the situation of the head trace at the time of recording rape or reproduction, and the situation of the error rate obtained by each detection method. .

The present invention is based on the background and technical idea described above, and a signal reproducing circuit applied to a digital VTR will be specifically described below with reference to FIGS. 1 and 2. The signal reproduction circuit 200 includes a first switching circuit 202, a second switching circuit 204, a clock reproduction circuit 206, a latch circuit 208, a precoding circuit (or a demodulation circuit for interleaved NRZI modulation).
210, a third switching circuit 220, and a switching control circuit 230. The latch circuit 208 is specifically a delay flip-flop (D-FF). The precoding circuit 210 is composed of two D-FFs 212 and 214 connected in series and an exclusive OR circuit 216. D-FF21
2 and the D-FF 214 delays 2T corresponding to PR (1,0, -1). The switching control circuit 230 energizes the first switching circuit 202, the second switching circuit 204, and the third switching circuit 220 according to the operation mode of the digital VTR. In this example, the second switching circuit 204 and the third switching circuit 220 are interlocking switching circuits and operate in the same manner.

FIG. 2 is a circuit diagram of the clock recovery circuit 206. The clock reproduction circuit 206 includes a precoding circuit 300 including a delay circuit 302 and an exclusive OR circuit 304, a phase difference detection circuit 310, a loop filter circuit 312, and a variable control type oscillation circuit (VCO) 314.
In the figure, a closed loop is constructed. Delay circuit 30
2 is the D-FF 212 and the D-FF 21 shown in FIG.
Substantially the same delay as 4. Therefore, the precoding circuit 300 operates in the same manner as the precoding circuit 210 shown in FIG. Clock recovery circuit 206
The phase difference detection circuit 310 calculates the phase difference between the signal obtained by precoding the signal selected from the first switching circuit 202 by the precoding circuit 300 and the output signal of the VCO 314, and filters it by the loop filter circuit 312. Note that the phase-locked loop circuit (PLL circuit) is configured so that the VCO 314 outputs a signal having an oscillation frequency corresponding to the result (voltage). That is, the precoding circuit 300 detects the information of the data change point of the input signal, the phase difference detection circuit 310 compares the detected signal with the clock signal from the VCO 314 to calculate the phase difference, and the obtained error is obtained. The voltage is transmitted to the VCO 314 via the loop filter circuit 312.
The clock regenerating circuit 206 outputs a clock signal that is fed back to the pre-encoding circuit 300 so that there is no phase difference.

The operation of the circuit illustrated in FIGS. 1 and 2 will be described below. In the PR (1, 0, -1) system, the data before recording is pre-modulated by the interleaved NRZI system. This modulation before recording is called precoding in the PR system, and by doing this, error propagation after detection is prevented and +1 and -1 of the ternary signal are set to 1
By associating 0 with 0, the original data recorded on the magnetic tape can be restored. Signal reproduction circuit 200
To the first input terminal a of the output signal of the partial response equalization detection circuit of any one of FIG. 4, FIG. 5 and FIG. 6 described above, PR (1, 0, −1) signal, that is, PR
The ternary signal detected by the (1, 0, -1) method is +1 and-.
P of binary data obtained by corresponding 1 to 1 and 0 to 0
The R (1,0, -1) signal is input. Data that has been integrated and detected for clock extraction is input to the second input terminal b, and is applied to the clock recovery circuit 206 via the first switching circuit 202. These first and second
The signal applied to the input terminals a and b of is the output signal of any one of FIG. 4, FIG. 7, and FIG. The third input terminal c is
"E-" for directly returning data without passing through an electromagnetic conversion system of a magnetic head / magnetic tape and a reproduction equalization circuit (not shown)
This is a terminal for inputting an “E signal”, and is applied to the clock recovery circuit 206 via the first switching circuit 202.

The normal playback mode of the digital VTR will be described. In the normal reproduction mode, the switching control circuit 230 energizes the first switching circuit 202 to the state shown by the solid line in the figure, energizes the second switching circuit 204 as shown in the figure, and the third switching circuit 220 in the figure. Energize As a result, in the normal reproduction mode, the integral detection signal applied to the second input terminal b is reproduced by the clock reproduction circuit 206 and applied as the reproduction clock CK to the latch circuit 208. Further, the PR (1,0, -1) signal applied to the first input terminal a is
Is applied to the latch circuit 208 via the switching circuit 204, and the output signal latched by the recovered clock from the clock recovery circuit 206 is applied to the first input terminal 1 of the third switching circuit 220 to be selectively output. And output as a data output from the output terminal d. That is,
In the normal reproduction mode, a reproduction clock is generated from the integral detection signal and output from the output terminal e, and PR (1, 0,
-1) Output a signal from the output terminal d.

Next, the EE mode of the digital VTR will be described. In the EE mode, the switching control circuit 230 selectively outputs the signal applied to the input terminal 2 of the first switching circuit 202, the second switching circuit 204, and the third switching circuit 220. That is, the state is biased to the state opposite to the state shown by the solid line. When data is returned directly after passing through an electromagnetic conversion system such as a magnetic head or magnetic tape, it is originally EE
The signal is output as it is from the output terminal d.
However, the EE signal is precoded by delaying it by 2T and inverting and adding it to the original signal, that is,
Since the PR (1,0, -1) equalization is not performed, the code form of the output terminal d needs to be the same as the PR (1,0, -1) equalization. For this purpose, the same processing as PR equalization is necessary for the EE signal. In other words, it is necessary to perform demodulation (decoding) of interleaved NRZI modulation performed as precoding for PR (1,0, -1) equalization on the EE signal. The precoding circuit 210 performs this precoding, that is, demodulation (decoding) of interleaved NRZI modulation. The precoding circuit (demodulation circuit) 210 is used when outputting the EE signal and the integral detection signal applied to the second input terminal b.

The variable speed reproduction mode of the digital VTR will be described. As illustrated in FIG. 9, in the case of slow playback or shuttle playback (picture search) in which the envelope of the playback RF signal becomes a triangular waveform and the amplitude changes significantly, or the playback data rate changes, PR
In the case of fast forward or rewind that further narrows the detection window width of the method, the amplitude fluctuation of the reproduced RF signal is large due to dropout or fluctuation of contact even during the normal reproduction, and the advantage of the PR method In such cases, as shown in the characteristic diagram of FIG. 10, there is a possibility that integral detection can perform detection with relatively few errors. As the main line data output from d, the integral detection signal applied to the input terminal b is directly selected and output. In this case, the switching control circuit 230 uses the first switching circuit 2
02 is energized so as to select the integral detection signal applied to the first input terminal 1 as shown, and the second switching circuit 204 is selected to be the integral detection signal output from the first switching circuit 202. Input terminal 2 to output
To activate the third switching circuit 220 so that the input terminal 2 is selected so that the output of the precoding circuit 210 is selectively output.

In the digital VTR having the signal reproducing circuit of the present invention, by performing the above-mentioned control operation, the PR (1,0, -1) signal is used in the normal reproducing mode and also in the variable speed reproducing mode. Using the integral detection signal, using the EE signal in the EE mode,
It is possible to always maintain the best reproduction detection state.

The precoding circuit 210, that is, the demodulation circuit 210 for interleaved NRZI modulation is
Originally, it is a circuit required in the EE mode, and it is not necessary to newly add it to configure the signal reproducing circuit of the present invention, and the digital VTR of the present invention can be realized with almost the same circuit scale as the conventional one. There is an advantage to say.

FIG. 3 is a circuit diagram of a signal reproducing circuit applied to a digital VTR as a second embodiment of the signal reproducing circuit of the present invention shown in FIG. The signal reproducing circuit shown in FIG. 3 has a circuit configuration similar to that of the signal reproducing circuit illustrated in FIG. 1, but the signal reproducing circuit of FIG. 3 has a switching control circuit 232 equivalent to the switching control circuit 230. A state monitoring circuit 234 is provided. The state monitoring circuit 234 monitors the data output from the output terminal d and monitors its error. When the error exceeds a predetermined level, for example, the normal control mode of the digital magnetic recording / reproducing apparatus is set and the switching control circuit 23 is set.
2 forcibly energizes the first switching circuit 202, the second switching circuit 204, and the third switching circuit 220 to the switching position in the variable speed reproduction mode even when energized to the state indicated by the solid line in the figure. Thus, the switching control circuit 232 is instructed. As a result, even if the digital VTR is set to the normal reproduction mode and is operating, in actuality, in the case where the data rate of the read data from the magnetic tape is changed due to some factor described above, the details will be given. According to the state, reproduction is performed using a more stable integral detection signal.

As the partial response equalization detection method of the present invention, PR (1, 0,
Although the -1) signal has been described as an example, other partial response signals such as PR (1, -1) and its equalization detection method can be used as the partial response signal and its detection method. Further, the above-mentioned signal reproducing circuit of the present invention uses a digital VTR as a preferred embodiment,
Although the case of applying to a digital VTR has been described, the present invention is not limited to the digital VTR, and other systems that receive and reproduce (decode) data whose data rate changes while receiving and reproducing data at a fixed data rate, For example, it goes without saying that the invention can be applied to a variable speed data communication system as well as the digital VTR. That is, the signal reproducing circuit and the signal reproducing method of the present invention are not limited to the digital VTR, and are applied to various other systems that perform the above-described data reproducing process.

[0040]

According to the present invention, the received data can be reproduced very stably and accurately with a simple circuit configuration when the data rate is fixed, and the received data can be stably reproduced when the data rate changes. A signal reproduction circuit can be provided. When this signal reproducing circuit is applied to, for example, a digital recording / reproducing apparatus, particularly a digital reproducing apparatus, it is possible to always obtain stable and accurate reproduced data. Further, according to the present invention, the following effects are exhibited. (1) It is not necessary to control the delay amount of a complicated delay circuit according to the speed of a data transmission system such as a magnetic tape, and the circuit can be simplified. (2) A high-speed A / D converter in the integral equalization system and a digital arithmetic circuit for PR detection in the digital domain are not required, and power consumption and cost can be significantly reduced. (3) Furthermore, the error rate is applied to appropriately select a signal to be used for reproduction, and it is possible to always maintain an optimum reproduction state, and it is possible to improve reliability.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a signal reproducing circuit applied to a digital magnetic recording / reproducing apparatus as a first embodiment of a signal reproducing circuit of the present invention.

FIG. 2 is a circuit configuration diagram of the clock recovery circuit shown in FIG.

FIG. 3 is a circuit configuration diagram of a signal reproducing circuit applied to a digital magnetic recording / reproducing apparatus as a second embodiment of the signal reproducing circuit of the present invention.

FIG. 4 is a configuration diagram of a PR (1,0, −1) type PR equalization detection circuit applied to the digital magnetic recording / reproducing apparatus of the present invention.

5 (A) to (D) are graphs showing the waveforms in FIG.

6 is a graph showing an eye pattern of the PR equalization detection circuit shown in FIG.

FIG. 7 is a second configuration diagram of a PR equalization detection circuit applied to the digital magnetic recording / reproducing apparatus of the present invention.

FIG. 8 is a third configuration diagram of a PR equalization detection circuit applied to the digital magnetic recording / reproducing apparatus of the present invention.

FIG. 9 is a graph showing the characteristics when the data rate changes when the partial response equalization detection method is applied.

FIG. 10 is a graph showing an eye pattern for integral equalization detection.

[Explanation of symbols]

 200, 200A .. Signal reproduction circuit 202 .. First switching circuit 204 .. Second switching circuit 206 .. Clock reproduction circuit 208 .. Latch circuit 210 .. Precoding circuit Interleaved NRZI modulation demodulation circuit 220 .. Third switching circuit 230, 232 .. Switching control circuit 234 .. State monitoring circuit

Claims (10)

[Claims] 1. A transmission data rate of a received signal is monitored, a partial response detection signal is selected when the data transmission rate is substantially constant, and an integral detection signal is selected when the data transmission rate changes. , A signal reproducing method for reproducing received transmission data by using these selected signals. 2. The signal reproducing method according to claim 1, wherein the reproduction error rate of the transmission data is monitored, and the partial response detection signal or the integral detection signal is selected by also referring to the error rate. 3. The signal reproducing method according to claim 1 or 2, wherein when the E-E signal is selected, the partial response characteristic is compensated for output. 4. The signal reproducing method according to claim 1, wherein the transmission data is a signal read from a magnetic tape in a digital magnetic reproducing device. 5. The partial response is PR (1,
The signal reproducing method according to claim 4, which is a 0, -1) system. 6. A first switching means for selectively outputting a partial response equalization detection signal and an integral detection signal, a clock regeneration means for regenerating a clock from the integral detection signal, and a partial response equalization means. Second switching means for selectively outputting an output signal of the partial response equalization means and a signal before the partial response equalization means, and switching control for energizing the first and second switching means In the first operation mode, the switching control means outputs the partial response equalization detection signal from the second switching means at a timing according to a reproduction clock from the clock reproduction means. In the second operation mode, based on the recovered clock from the clock recovery means, A signal reproduction circuit for applying the integral detection signal to the partial response equalization means and outputting the output from the second switching means. 7. The apparatus further comprises means for monitoring the data output from the reproduction clock and the second switching means, and the monitoring means, when the error rate of the monitored data drops below a predetermined level. 7. The signal reproducing circuit according to claim 6, wherein the switching control means is operated to reverse the energizing positions of the first and second switching means. 8. The signal reproducing circuit is used as a decoding circuit of a digital magnetic recording / reproducing apparatus, the first operation mode is a normal reproduction mode, and the second operation mode is a variable speed reproduction mode. The signal reproduction circuit according to 6 or 7. 9. The apparatus further comprises third switching means for selectively outputting the EE signal and the integral detection signal, wherein the switching control means in the EE mode:
9. The signal reproduction circuit according to claim 8, wherein the first to third switching means are energized so that the EE signal is output via the partial response equalization means. 10. The partial response signal is PR
(1, 0, -1) signal, and the partial response equalization unit is PR (1, 0, -1)
10. An equalization circuit corresponding to the -1) method is provided.
Any one of the signal reproduction circuits described above.