JPH07121687A - Processor for image codec and access pattern conversion method - Google Patents

Abstract

PURPOSE:To provide a processor for image codec capable of reducing the capacity of data address storage memory. CONSTITUTION:Data address sequence (pattern expressing access sequence to data memory 72, 74 by an arithmetic circuit 6 by using a data address) assuming frame DCT is stored in the data address storage memory 2, and when the frame DCT is executed, the data address sequence is used as it is, and when field DCT is executed, the data address sequence is converted at a data address conversion circuit 4, and access to the data memory 72, 74 in which data transfer for field DCT is completed are performed by using converted data address sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image codec processor used, for example, in numerical calculation, image processing, graphics processing and the like.

[0002]

2. Description of the Related Art First, the concept of image macroblocks and blocks in image codec processing is described in CCIR.
A 4: 2: 2 signal based on the 601 format will be described as an example. Image codec processing is CCITT
H. H.261, MPEG, and other image compression encoding / decompression decoding standards, and image encoding and decoding processing using a macroblock based on motion compensation + discrete cosine transform (DCT) as a processing unit. Is.

As shown in FIG. 7, one image frame has 7
It is composed of a luminance component (Y component) having a size of 20 × 480 pixels and two color difference components (Cr component and Cb component) having a size of 360 × 480 pixels sub-sampled in the horizontal direction. This image frame is 16x1 for the luminance component.
It is divided into a rectangular area of 6 pixels, and two color difference components are divided into a rectangular area of 8 × 16 pixels. A 16 × 16 pixel rectangular area in the luminance component and an 8 × 16 pixel rectangular area in the two color difference components positionally corresponding to the rectangular area are collectively called a macroblock.

Further, regardless of the luminance component and the color difference component,
A rectangular area of 8 × 8 pixels is called a block. Therefore,
As shown in FIG. 4, one macroblock includes four luminance component blocks and four chrominance component blocks (two Cr component blocks and two C components).
It consists of a total of 8 blocks (2 blocks of b component).

By the way, in image codec processing such as MPEG2, there is element processing called field / frame adaptive processing. This is a process of adaptively switching, for each macroblock, whether to perform discrete cosine transform (DCT) in units of fields or in units of frames, depending on the intensity of movement of the image to be compressed. IDCT at the time of decoding when the field DCT is selected at the time of encoding
Is also done in field units. In addition, the frame D
When CT is selected, IDCT at the time of decoding is also performed in frame units. When DCT / IDCT is performed in field units in this way, it is called field processing, and when it is performed in frame units, it is called frame processing.

Hereinafter, the field / frame adaptive DCT will be described with reference to the drawings. FIG. 8 is a diagram for explaining the structure of the frame. One frame consists of two fields, an A field and a B field, as shown in FIG. FIG. 9 is a diagram for explaining pixels forming two vertically adjacent blocks (8 × 16 pixels) in a macroblock. Aij (i = 0 to 0 in FIG. 9
7, j = 0 to 7) are pixels in the A field shown in FIG. 8, and Bij (i = 0 to 7, j = 0 to 7) are pixels in the B field.

In the frame DCT, as shown in FIG. 10, two vertically adjacent blocks (8 × 8) shown in FIG. 9 are used.
The pixel value of 16 pixels) is divided into two blocks (frame 0 and frame 1) consisting of 8x8 pixels, frame 0 is stored in the data memory A in the element processor A, and frame 1 is the data in the element processor B. Store in memory B. Then, the processor elements A and B perform the two-dimensional 8x8 DCT in units of frames on the blocks of 8x8 pixels stored in the data memories A and B, respectively.

On the other hand, in the field DCT, as shown in FIG.
As shown in FIG. 1, the pixel values of two vertically adjacent blocks (8 × 16 pixels) shown in FIG. 9 are alternately extracted in the vertical direction and divided into two blocks (field 0 and field 1) of 8 × 8 pixels. Then, the field 0 is stored in the data memory A in the element processor A, and the field 1 is stored in the data memory in the element processor B. Then, the element processors A and B perform the two-dimensional 8 × 8 DCT in units of fields on the blocks of 8 × 8 pixels stored in the data memories A and B, respectively.

Here, the 6-digit binary number beside the image data matrix shown in FIGS. 10 and 11 means the address of the first image data in each row. This address is an address in the data memory (64 words) in the element processor. For example, in FIG. 10, frame 0
The address of A00 is "000000", and the address of B15 of frame 1 is "011001".
Also, for example, in FIG. 11, A00 of field 0
Address is "000000" and field 1
The address of B15 is “011001”.

The element processors A and B are data memories A and
The address pattern for accessing B is the same in both frame DCT and field DCT.

The problem here is that since the data arrangement of the image data in the data memory differs between the field DCT and the frame DCT, the distribution of the image data and the control of other element processing (motion compensation etc.) are performed. This requires two systems, which is complicated.

In order to solve such a problem, Japanese Patent Application No. 5-074764 filed by the present applicant assumes either a frame DCT or a field DCT at the time of distributing image data to each element processor. Disclosed is an image codec processor that distributes data and transfers data between adjacent element processors when the assumption is not met. According to this image codec processor, control of distribution of image data and control of other element processing (motion compensation, etc.) need only one system. Hereinafter, Japanese Patent Application No. 5-07476 by the applicant
The image codec processor disclosed in No. 4 will be described. This image codec processor has a number of element processors corresponding to each block forming the macro block, and performs image codec processing for each block by SIMD (Single Instruction stream Mult).
iple Data stream: Single instruction stream / multiple data stream) Control is performed in parallel.

FIG. 1 is a block diagram of an image codec processor. The image codec processor is shown in FIG.
8 element processors PE0 (11) corresponding to each of the 8 element blocks forming the macroblock shown in FIG.
It has PE7 (18). In this image codec processor, the eight blocks forming the macroblock are the element processors PE0 (11) to PE7 (1).
8). For example, the block 0 is assigned to the element processor PE0 (11), the block 1 is assigned to the element processor PE1 (12), ..., And the block 7 is assigned to the element processor PE7 (18). Element processor P
E0 (11) and PE1 (12), PE2 (13) and PE
3 (14), PE4 (15) and PE5 (16), and PE6 (17) and PE7 (18) are connected via data transfer paths 42, 43, 44 and 45, respectively, which will be described later. As described above, during the field DCT / IDC processing, data exchange is performed between the data memories in the mutual element processors.

For example, assuming that the image data is stored in the data memory of each element processor assuming the frame DCT, the data memory A in the element processor PE0 (11) shown in FIG. 1, for example, is stored in the data memory A as shown in FIG. Stores the frame 0, and the data memory B in the element processor PE1 (12) stores the frame 1. Then, when the field DCT is selected, data transfer between the data memory A in the element processor PE0 (11) and the data memory B in the element processor PE1 (12) via the inter-element processor data transfer path 42 ( Exchange) is performed. At this time, the image data in the portion surrounded by the bold line in FIG. 12 is transferred and exchanged between the data memory A and the data memory B. 13A and 13B show the arrangement of image data in the data memories A and B after the data transfer at the field DCT is completed.

[0015]

However, as shown in FIG.
As shown in (A) and (B), the arrangement of the image data after the data transfer is different from the arrangement shown in FIG. 11. For example, at the address "001000" of the data memory A, A04 should be stored although A01 should be stored originally.

Therefore, in the conventional image codec processor, from the element processors A and B to the data memory A,
A data address for storing a data address sequence in which the element processors A and B use the data address to indicate the pattern for accessing the image data so that the access patterns for the image data stored in B are the same. Storage memory for field DCT and frame D
Two are prepared independently for CT. That is, FIG.
A data address storage memory for storing a data address sequence for a frame DCT as shown in FIG. 14A and a data address storage memory for storing a data address sequence for a field DCT as shown in FIG. 14B are independently provided. I have it.

Although the DCT has been described above, the conventional image codec processor also has two independent data address storage memories for the frame IDCT and the field IDCT.

As a result, the above-mentioned conventional image codec processor has a problem that the capacity of the data address storage memory becomes large.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide an image codec processor capable of reducing the capacity of a data address storage memory.

[0020]

In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, the image codec processor of the present invention comprises a plurality of blocks each of which is composed of mxn image data. With a macroblock consisting of 1 as a processing unit, the first signal processing over the image data of a plurality of blocks and the second signal processing for the image data in one block are adaptively performed by a single instruction stream. Multiple data stream control processing "Single instruction stream / multiple data stream: SIMD"
In the control type image codec processor, a plurality of pairs of element processors, which are connected by a data transfer path between the element processors and are provided corresponding to the blocks, and one of the first signal processing and the second signal processing. Image data suitable for one of the processes is stored as initial data, and a first storage unit is provided corresponding to each of the plurality of element processors, and the first processor in which the element processor corresponds to the initial data. Second storage means for storing an access pattern indicating an access pattern indicating the pattern for accessing the image data when performing either one of the signal processing and the second processing; and the first signal processing. When performing the other processing of the second signal processing, the image data suitable for the other processing is stored in the first storage means. As a control means for the exchange of data via the inter-processor data transfer path, said first
Access pattern conversion means for converting the access pattern stored in the second storage means so as to match the other processing when performing the other processing of the second signal processing and the other signal processing. Have.

Further, in the access pattern conversion method of the present invention, a macro block composed of a plurality of blocks each of which is composed of mxn image data is used as one processing unit.
The first signal processing for the image data of a plurality of blocks and the second signal processing for the image data in one block are adaptively provided corresponding to the blocks using a single instruction stream. In a processor for a "single instruction stream / multiple data stream: SIMD" control type image codec for performing multiple data stream control processing by a plurality of paired element processors, one of the first signal processing and the second signal processing Image data is stored as initial data in a memory layout suitable for one process,
The element processor stores an access pattern indicating a pattern for accessing the image data by using an address when performing one of the first signal processing and the second processing corresponding to the initial data. Then
When performing the other processing of the first signal processing and the second signal processing, image data is stored between the plurality of pairs of processors so that image data is stored in a storage arrangement suitable for the other processing. When the exchange is performed and the other processing of the first signal processing and the second signal processing is performed, the stored access pattern is converted to be compatible with the other processing, and the exchange is performed. The other process is performed based on the converted access pattern using image data.

[0022]

In the image codec processor and the access pattern conversion method of the present invention, for example, initial data suitable for the first signal processing is stored in the first storage means, and the first signal processing is performed. In this case, the access pattern stored in the second storage means is used as it is, and the first storage means is accessed according to the access pattern to perform the first signal processing.

Next, in the image codec processor and the access pattern conversion method of the present invention, for example, the first
Initial data adapted to the signal processing of No. 1 is stored in the first storage means, and when performing the second signal processing, it is adapted to the second signal processing based on the control signal from the control means. Data exchange is performed between the paired element processors so that the image data is stored in the first storage means. Further, the access pattern stored in the second storage unit is converted so as to be suitable for the second signal processing. Then, using the converted access pattern,
According to the access pattern, the first storage unit with which the image data is exchanged is accessed to perform the second processing.

[0024]

Embodiments of the image codec processor of the present invention will now be described in detail with reference to the drawings. The image codec processor according to the embodiment of the present invention has a plurality of arithmetic circuits each including an arithmetic logic operation unit (ALU), a multiplier, an accumulator, etc., and these arithmetic circuits have a single instruction stream. "Single instruction stream / multiple data stream:
SIMD (Single Instructionstream Multiple Data s)
tream) based processor. Regarding the “single instruction stream / multiple data stream: SIMD” control, see Yamauchi, et al, “Arc”.
hitecture and Implemententati
on of a Highly Parallel Si
single: Chip Video DSP ", IEEE
TRANSACTIONS AND SYSTEMS
FOR VIDEO TECHNOLOGY, VO
L. 2, JUNE 1992, pp. See 207-220. Furthermore, the arithmetic circuit of this processor is
It is possible to connect arithmetic units in a pipeline, and also perform pipeline arithmetic processing.

The overall configuration of the image codec processor of the present invention will be described below. FIG. 1 is an overall configuration diagram of an image codec processor as one embodiment of the present invention. The image codec processor of this embodiment includes
Eight element processors 11 to 18 are provided for each block of the macro block shown in FIG. Further, as shown in FIG. 1, the image codec processor of the present embodiment has a macroblock input terminal 21, a macroblock output terminal 22, a macroblock input / output terminal 23 of a frame memory, and a macroblock input terminal 2 of a frame memory.
4 and further has an input data bus 31, an output data bus 32, and data buses 33 and 34 connected to these terminals. Further, a plurality of image codec processors are connected to each other via these buses 31 to 34, in this example, eight element processors (PE) 11 to 18 and four element processors 11 to 1
1 is applied to the adder circuit 41 for adding the results of 4 and the arithmetic circuit 6 (FIGS. 2 and 3) of each element processor 1
And one coefficient memory 51. The element processor 1
1 to 18 are connected to each other by the buses 31 to 34, and are adjacent element processors, that is, PE0 and PE.
1, PE2 and PE3, PE4 and PE5, PE6 and PE7
And are connected to each other.

The operation of the image codec processor of the present invention will be described below. First, image data is input one by one from the macroblock terminal 21 shown in FIG. 1 to the macroblock to be processed by the image codec.
At this time, each block of the macro block is divided into two vertically adjacent blocks 0 and 1 shown in FIG. 7 in a data storage arrangement assuming a frame DCT as shown in FIG. ), PE1 (12) are stored in the data memories 72 and 74 as the first storage means. Similarly, two vertically adjacent blocks 2 and 3 shown in FIG. 7, blocks 4, 5 and blocks 6 and 7 are the element processors PE2 (13) and PE3 (1 shown in FIG.
4) and the element processors PE4 (15) and PE5 (1
6) and the element processors PE6 (17) and PE7 (1
8) and are stored separately.

In parallel with these input operations, the arithmetic circuit 6 of each element processor PE shown in FIG. 2 controls the "single instruction stream / multiple data stream: SIMD" control in discrete cosine transform (DCT) at the time of encoding. Image codec element processing such as quantization and quantization is executed in parallel. In addition, as described in the above-mentioned literature,
"Single instruction stream / multiple data streams: SIM
"D" control is a method of controlling multiple (multiple) data flows with a single instruction. Further, since the element processing of all image codecs is performed by the "single instruction stream / multiple data stream: SIMD" control, the coefficient memory 51 shown in FIG. 1 is shared by all the element processors 11 to 18. The memory 51 is replaced by each of the element processors 11-1
You don't have to have it in 8. Further, in parallel with these input operation and calculation operation, the macro block after the image codec processing is output from the macro block output terminal 22 one data at a time.

A more detailed description of the overall configuration of the image codec processor of this embodiment will be given below.
Please refer to Japanese Patent Application No. 5-074764 cited in the section "Prior Art".

Hereinafter, the adder circuit 41 and the data transfer paths 42 to
45 and field / frame selection circuit 7 shown in FIG.
0 will be described. Inter-block data dependency such as image data motion vector detection and mode determination processing can be solved if all the calculation results obtained for each block can be added. For example, considering the image data motion vector detection, the sum of absolute differences is obtained for each block of the luminance component (4 blocks) of the macroblock, and finally the 4
It suffices to add the sums of the absolute differences. For this purpose, the adder circuit 41 is provided at the outputs of the four element processors 11 to 14 which store the luminance components of the macroblocks. The adder circuit 41 may have any configuration as long as all four calculation results can be added.

The data transfer paths 42 to 45 are arranged adjacent to each other so that the data corresponding to the field DCT is stored in the data memory of the element processor PE when the field DCT is selected in the processing in the element processor PE. Data transfer (exchange) between PEs
Used to do.

The field / frame selection circuit 70 uses the D
A determination is made as to whether CT is performed in field units or in frame units, and the result of the determination is shown to indicate the field / frame selection signal S70 to the data address storage memory 2 and a control circuit (not shown) as control means. ) Is output.

The element processor will be described in detail below. FIG. 2 shows element processors PE0 (11) and PE1.
It is a schematic block diagram of (12). As shown in FIG. 2, the element processors PE0 and PE1 mainly include the data memories 72 and 74 as the first storage means, the data address storage memory 2 as the second storage means, and the access pattern conversion means. Of the data address conversion circuit 4 and the arithmetic circuit 6. As shown in FIG. 2, in the data memories 72 and 74, the frame DCT is assumed as in the conventional image codec processor, and the image data is stored as initial data in the same data arrangement as in FIG.
The 6-digit binary number next to the matrix of image data shown in the data memories 72 and 74 in FIG. 2 indicates the address of the first image data in each row. For example, A00 of the data memory A
The address of B10 is "000000", and the address of B10 is "001001".

In the image codec processor of this embodiment, when the field DCT is selected in the field / frame selection circuit 70, the thick line shown in FIG. 2 is generated based on the instruction signal from the control circuit (not shown). The image data located in the row surrounded by is transferred (exchanged) between the data memory 72 and the data memory 74 via the data transfer path 42, and the image data is transferred in the data storage arrangement as shown in FIG. It is stored in the memories 72 and 74.

In the data address storage memory 2, a pattern (address order) in which the element processors A and B access image data is shown by using a data address indicating an address of each storage position in the data memories 72 and 74. A data address sequence as an access pattern is stored. For example, as shown in FIG.
A data address sequence 82 assuming the same frame DCT as the frame data address sequence shown in (A) is stored. The data address sequence 82 shown in FIG. 4 includes the data memories 72 and 74 shown in FIG.
The address of the image data located at the beginning of each row of the matrix of image data in is shown.

As described above, in the image codec processor of the embodiment, only the data address sequence 82 assuming the frame DCT is stored in the data address storage memory 2, and the field DCT is stored as in the conventional image codec processor. The assumed data address sequence (FIG. 14 (B)) is not stored, and the capacity of the data address storage memory 2 may be smaller than that of the conventional case.

As shown in FIG. 5, the data address conversion circuit 4 has a rotate circuit 62 and a selector 64, and when the arithmetic circuit 6 reads the data memories 72 and 74, it operates according to the user's operation. DCT / from part 8
The IDCT selection signal S8, the field / frame selection signal S70 from the field / frame selection circuit 70, and the data address sequence 82 from the data address storage memory 2 are input and included in the data address sequence when the field DCT is selected. A predetermined address conversion is performed on the data address to be converted, and the converted data address sequence 86 (FIG. 4A) is output to the arithmetic circuit 6. Further, the data address conversion circuit 4 is
When the frame DCT is selected, the data address sequence 8 stored in the data address storage memory 2
2 is directly output to the arithmetic circuit 6 (FIG. 4 (B)).

The rotate circuit 62 is operated by the D from the operation unit 8.
When the CT / IDCT selection signal S8 and the row address 82a of the upper 3 bits of the data address included in the data address sequence from the data address storage memory 2 are input and the selection signal S8 indicates DCT, As shown in FIG. 4A, the row address 82a is converted so that the access pattern to the image data of the arithmetic circuit 6 becomes a pattern corresponding to the field DCT, and the row address 86a generated by the conversion is generated (see FIG. 4). (A)) is output to the selector 64.

The selector 64 includes the row address 82a from the data address storage memory 2 and the rotate circuit 6.
The converted row address 86a from 2 and the field / frame selection signal S70 from the field / frame selection circuit 70 are input, and when the selection signal S70 indicates a frame (DCT), the row address 82a remains unchanged. When the selection signal S70 indicates the field (DCT), the row address 86a converted in the rotate circuit 62 is output to the arithmetic circuit 6.

The processing in the data address conversion circuit 4 will be described. First, the DCT / IDCT selection signal S8
Indicates DCT and the field / frame selection signal S70 indicates a frame (DCT). In this case, the data memory 72 of PE0 (11) and the data memory 74 of PE1 (12) are
As shown in FIG. 2, image data is stored in a storage arrangement that assumes a frame DCT. Therefore, the arithmetic circuit 6 can use the data address sequence 82 stored in the data address storage memory 2 as it is. Therefore, when the arithmetic circuit 6 reads the image data of the data memories 72 and 74, the data address conversion circuit 4 is used. Selects the row address 82a in the selector 64 and outputs the data address sequence 82 stored in the data address storage memory 2 to the arithmetic circuit 6 as it is.

Next, the DCT / IDCT selection signal S8 is D
CT is shown, and the field / frame selection signal S7
A case where 0 indicates a field (DCT) will be exemplified. At this time, as will be described later, the data memory 7
Of the image data in the matrix format shown in FIG. 2 stored in Nos. 2 and 74, the image data located in the row surrounded by the thick line is transferred between the data memory 72 and the data memory 74 via the data transfer path 42. After the exchange, the image data is stored in the data arrangement as shown in FIG. 3 after the exchange. Therefore, if the data address sequence stored in the data address storage memory 2 is used as it is, the field DCT cannot be properly performed in the arithmetic circuit 6,
When the arithmetic circuit 6 reads the image data in the data memories 72 and 74, the data address conversion circuit 4 performs data address conversion on the data address included in the data address sequence according to the field DCT. At this time, in the data address conversion circuit 42,
The selector 64 selects the converted row address 86a from the rotate circuit 62, and selects the row address 86a shown in FIG.
The data address sequence 86 corresponding to the field DCT as shown in (A) and (B) is output to the arithmetic circuit 6.

According to the data address sequence 86,
As shown in FIGS. 6A and 6B, the storage arrangement of the image data in the data memories 72 and 74 is the same as the storage arrangement shown in FIGS. 13A and 13B in the conventional image codec processor. However, by using the converted data address sequence 86, the arithmetic circuit 6 substantially accesses the image data with the data arrangement shown in FIGS. 6A and 6B, and the arithmetic circuit 6 can properly perform the field DCT.

Next, the operation of the element processor will be described. First, it is shown that the DCT / IDCT selection signal S8 selects the DCT, and the field / frame selection signal S
A case where 70 indicates that a frame (DCT) is selected will be exemplified. Element processor PE0 (11), PE
Image data is stored in the 1 (12) data memories 72 and 74 in a storage arrangement assuming a frame DCT as shown in FIG. 2 as an initial state. When the arithmetic circuit 6 reads the image data in the data memories 72 and 74, the data address storage memory 2 outputs the data address sequence 82 shown in FIG. 4 to the data address conversion circuit 4. In this case, the data address conversion circuit 4 does not perform the data address conversion, and the data address sequence 82 is directly output to the arithmetic circuit 6. Then, in the arithmetic circuit 6, the image data is read from the data memories 72 and 74 based on the data address sequence 82 input from the data address conversion circuit 4, and the frame D is read based on the read image data.
CT is performed. The calculation result of the frame DCT is output to the adder 41, and the output data bus 32,
The data is output to the output terminals 22 and 24 and the input / output terminal 23 via the data buses 33 and 34.

Next, the DCT / IDCT selection signal S8 is D
A case where CT is selected and the field / frame selection signal S70 indicates that the field (DCT) is selected will be exemplified. Element processor PE0 (1
1), in the data memory 72, 74 of PE1 (12),
In the initial state, image data is stored in a storage arrangement that assumes a frame DCT as shown in FIG. Based on the field / frame selection signal S70 from the field / frame selection circuit 70, the control circuit (not shown) causes the data located in the row surrounded by the thick line in FIG. It is transferred (exchanged) between 72 and the data memory 74. After this transfer,
Image data is stored in the data memories 72 and 74 in a storage arrangement as shown in FIG. Further, when the arithmetic circuit 6 reads the image data in the data memories 72 and 74, the data address conversion circuit 4 receives the data address sequence 82 from the data address storage memory 2 and, as shown in FIG. Bit low address 8
2a is a row address 86a according to the field DCT
Is converted into a data address sequence 86 including the row address 86a and the column address 82b of the data address sequence 82, and the data address sequence 86 is output to the arithmetic circuit 6.

Then, the data address sequence 86 input from the data address conversion circuit 4 is input to the arithmetic circuit 6.
The image data in the data memories 72 and 74 is read based on the above, and the field DCT is performed using the read image data. The calculation result of the field DCT is output to the adder 41 and also output terminal 2 via the output data bus 32 and the data buses 33 and 34.
2, 24 and the input / output terminal 23.

Element processors PE2, PE3 and PE4
The same applies to the element processors PE0 and PE1 described above, and PE5 and PE6 and PE7, but the results of the DCT of PE4 and PE5 and PE6 and PE7 are not output to the adder circuit 41.

As described above, according to the image codec processor of the present embodiment, only the data address sequence 82 assuming the frame DCT is stored in the data address storage memory 2, and the field is stored like the conventional image codec processor. Since the data address sequence assuming the DCT (FIG. 14 (B)) is not stored, the capacity of the data address storage memory 2 can be made smaller than in the conventional case. As a result, the image codec processor according to the present exemplary embodiment is responsive to the selection result of the field / frame selection circuit 70 in the field DCT.
Although it is possible to execute both the frame DCT and the frame DCT, the control of the data address using the data address sequence is one system, and the control can be simplified.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, in the above-described embodiment, the frame DCT is stored in the data address storage memory 2.
Although the case of storing the data address sequence assuming the above is illustrated, the data address sequence assuming the field DCT is stored in the data address storage memory 2, and this data address sequence is stored in the data address conversion circuit when performing the frame DCT. In step 4, the data address sequence may be converted according to the frame DCT.

In the above-mentioned embodiment, the DCT is exemplified, but also in the image codec processor to which the field / frame IDCT is applied, when the image data before IDCT is written, like the image codec processor described above. By converting the data address using the data address storage memory 2 shown in FIG. 5, the capacity of the data address storage memory 2 can be reduced and the data address control can be simplified.

[0049]

As described above, according to the image codec processor and the access pattern conversion method of the present invention, the element processor in the second storage means performs either the first signal processing or the second signal processing. When doing one,
An access pattern indicating a pattern for accessing the image data by using an address is stored, and when the element processor performs the other signal processing of the first signal processing and the second signal processing, the second pattern is also stored. Since the access pattern stored in the storage means is converted and used, the access pattern adapted to either the first signal processing or the second signal processing may be stored in the second storage means. As a result, the storage capacity of the second storage means can be reduced. Further, although both the first signal processing and the second signal processing can be executed, the control of the data address using the access pattern can be a simple one system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image codec processor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of PE0 and PE1 shown in FIG. 1, and image data assuming a frame DCT is stored as initial data in a data memory.

FIG. 3 shows PE0 and PE1 when performing field DCT.
FIG. 7 is a diagram for explaining image data stored in a data memory after data transfer between and is completed.

FIG. 4 is a diagram for explaining address conversion of a data address sequence in the data address conversion circuit shown in FIG.

FIG. 5 is a configuration diagram of a data address conversion circuit.

6A is a diagram for explaining a relationship between a data address sequence before and after conversion and a storage arrangement of a data memory A, and FIG. 6B is a data address sequence before and after conversion. FIG. 6 is a diagram for explaining the relationship between the storage arrangement of the data memory B and FIG.

FIG. 7 is a diagram for explaining a macroblock.

FIG. 8 is a diagram for explaining the structure of a frame.

FIG. 9 is a diagram for explaining two vertically adjacent blocks shown in FIG. 8;

FIG. 10 is a diagram for explaining the data arrangement of the data memory at the time of frame DCT.

FIG. 11 is a diagram for explaining the data arrangement of the data memory at the time of field DCT.

FIG. 12 is a diagram for explaining data transfer between data memories during field DCT.

FIG. 13A is a diagram for explaining the data arrangement in the data memory A at the time when the data transfer between the data memories is completed during the field DCT;
(B) is a diagram for explaining the data arrangement in the data memory B at the time when the data transfer between the data memories is completed during the field DCT.

FIG. 14A is a frame DC stored in a data address storage memory of a conventional image codec processor.
It is a figure for demonstrating the data address sequence for T, (B) is the field DCT memorize | stored in the data address storage memory of the processor of the conventional image codec.
FIG. 6 is a diagram for explaining a data address sequence for use in data transmission.

[Explanation of Codes] 2 ... Data Address Storage Memory 4 ... Data Address Conversion Circuit 6 ... Arithmetic Circuit 8 ... Operation Unit 11-19 ... Element Processor 42-45 ... Between Element Processors Data transfer path 41 ... Addition circuit 51 ... Coefficient memory 62 ... Rotation circuit 64 ... Selector 70 ... Field / frame selection circuit 82, 86 ... Data address sequence

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Claims (8)

[Claims] 1. A first signal process that spans image data of a plurality of blocks and image data in one block, with a macro block consisting of a plurality of blocks each composed of mxn image data as one processing unit. In the processor for the "single instruction stream / multiple data stream: SIMD" control type image codec, which adaptively controls the second signal processing of No. 1 to multiple data stream with a single instruction stream, a data transfer path between element processors is provided. And a plurality of pairs of element processors provided corresponding to the blocks, and image data suitable for any one of the first signal processing and the second signal processing are stored as initial data. A first storage unit provided corresponding to each of the plurality of element processors; A storage unit that stores an access pattern that indicates, by using an address, a pattern for accessing the image data when the processor performs one of the first signal processing and the second processing corresponding to the initial data. 2 storage means, and when performing the other processing of the first signal processing and the second signal processing, image data suitable for the other processing is stored in the first storage means. Control means for exchanging data via the inter-processor data transfer path, and stored in the second storage means when performing the other processing of the first signal processing and the second signal processing. An image codec processor having an access pattern conversion means for converting the access pattern so as to match the other processing. 2. The image codec processor according to claim 1, wherein the first signal processing is field image signal processing, and the second signal processing is frame image signal processing. 3. The image codec processor according to claim 2, wherein the field image signal processing and the frame image signal processing are discrete cosine transform processing at the time of encoding. 4. The image codec processor according to claim 2, wherein the field image signal processing and the frame image signal processing are discrete cosine inverse transform processing at the time of encoding. 5. The first signal processing and the image data in one block, which spans the image data of a plurality of blocks, with a macroblock consisting of a plurality of blocks each composed of mxn image data as one processing unit. The second signal processing of (1) is adaptively performed by using a single instruction stream, and multiple data stream control processing is performed by a plurality of pairs of element processors provided corresponding to the block "single instruction stream / multiple data A stream: SIMD ”control type image codec processor, wherein image data is stored as initial data in a storage arrangement suitable for either one of the first signal processing and the second signal processing, and the element processor One of the first signal processing and the second processing corresponding to the initial data is performed. An access pattern, which sometimes indicates a pattern for accessing the image data by using an address, is stored, and when the other processing of the first signal processing and the second signal processing is performed, it is adapted to the other processing. The data is exchanged between the plurality of pairs of processors so that the image data is stored in the stored arrangement, and the storage is performed when the other one of the first signal processing and the second signal processing is performed. An access pattern conversion method for converting the access pattern thus converted so as to be compatible with the other process, and performing the other process based on the converted access pattern using the exchanged image data. 6. The access pattern conversion method according to claim 5, wherein the first signal processing is field image signal processing, and the second signal processing is frame image signal processing. 7. The access pattern conversion method according to claim 6, wherein the field image signal processing and the frame image signal processing are discrete cosine conversion processing at the time of encoding. 8. The access pattern conversion method according to claim 6, wherein the field image signal processing and the frame image signal processing are discrete cosine inverse conversion processing at the time of encoding.