JPH07121102A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten the program execution time by employing genetic algorithm for the scheduling process of a register file and decreasing the frequency of memory access. CONSTITUTION:A gene is constituted of a register file number sequence based upon the replacement order of a register file. A compiler 12 judges whether or not data required for the execution of each instruction read in when a source program is compiled are stored in an internal register 11 at the time of its execution, and accesses an external memory 2 and outputs an object instruction to replace corresponding data to the internal register 11 on the basis of the gene unless the data are stored. The frequencies of access to the external memory 2 are calculated, gene by gene, and adaptability is found on the basis of the frequencies; and respective genes are duplicated according to the adaptability, and the genes after the duplication are crossed. Some of register file numbers of the genes after the crossing are mutated and this series of processes is repeated for specific generations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a compiler that compiles each instruction in a source program and outputs its object instruction, and also outputs an object instruction for replacing data stored in an internal register based on a scheduling procedure. The present invention relates to a programmable controller having.

[0002]

2. Description of the Related Art In a programmable controller (hereinafter, referred to as PLC) using a load / store system CPU, the access instruction execution time to an external memory is usually much longer than the access instruction execution time to an internal register. In the case of a program that accesses the external memory a large number of times, the execution time of this part greatly affects the entire program.

Therefore, in order to shorten the program execution time by reducing the number of accesses to the external memory, the CPU
It is essential to make effective use of the register file of internal registers (hereinafter referred to as registers). Once data has been read into the register file, all subsequent access to that data can be made to the register file. Proposed.

[0004]

However, since the register file is finite and not so large in capacity, it is necessary to schedule the register file according to the user program, that is, to replace the contents of the file. It has not been clarified whether the number of accesses to the external memory can be reduced most by replacing the register file.

Recently, in the field of information processing, a genetic algorithm (GA; Gen) has been used as one of the methods for problem solving.
The introduction of etic Algorithm) has been proposed.

Therefore, the present invention has been made in view of such a problem. By incorporating a genetic algorithm in the scheduling of the register file, the number of accesses to the external memory is reduced and the program execution time is shortened. It is an object of the present invention to provide a programmable PLC.

[0007]

In order to achieve the above object, according to the present invention, each instruction in a source program is compiled and its object instruction is output, and the data stored in an internal register is based on a scheduling procedure. A programmable controller having a compiler for outputting an object instruction to be replaced according to the above, wherein the compiler stores gene pool storage means for storing a plurality of register file number sequences of internal registers indicating a scheduling procedure as genes, and When instructions are sequentially read, the object instruction of the instruction is output, and whether the data required for executing the instruction is stored in the register file of the internal register, and it is not stored Is described in the above gene pool storage means A register file is specified on the basis of each generated gene, and a compiling means for outputting an object instruction to access the external memory so that the data is stored in the register file, and an external memory output from the compiling means are accessed. A fitness calculating means for calculating the number of object instructions for each gene and finding the fitness of each gene based on the number of instructions, and a gene for replicating each gene according to the fitness calculated by the fitness calculating means. The replication means, the gene crossover means for crossing over each gene duplicated by the gene duplication means to create a new gene, and some of the register file numbers constituting the new gene created by the gene crossover means are optional. Gene mutation means for mutating to any register number with the probability of Compile means,
The fitness calculation means, the gene duplication means, the gene crossover means and the gene mutation means are repeatedly executed a predetermined number of times, and a repetition control means for stopping each processing after the predetermined number of times is executed. It is characterized by

[0008]

In the compiler according to the present invention, a plurality of register file number sequences of internal registers indicating the scheduling procedure are stored as genes, each instruction in the source program is sequentially read, and the object instruction of the instruction is output and It is judged whether or not the data required for executing the instruction is stored in the register file of the internal register, and if it is not stored, the register is performed based on each gene stored in the gene pool storage means. A file is specified, and an object instruction for accessing the external memory so that the above data is stored in the register file is output.

Then, the number of object instructions for accessing the external memory is calculated for each gene, the fitness of each gene is obtained based on the number of instructions, and each gene is duplicated according to the fitness. Each duplicated gene is crossed over to create a new gene, and at the same time, some of the register file numbers constituting the new gene are mutated to arbitrary register numbers. Such processing is repeatedly executed a predetermined number of times, and each processing is stopped after the predetermined number of times of execution.

[0010]

Embodiments of the PLC according to the present invention will be described below.

FIG. 1 shows the configuration of an embodiment of a PLC according to the present invention.

This PLC has a CPU 1, an external memory (IOM) 2 for storing input / output data, and a user program program memory 3 for storing a source program created by the user in ladder notation and its object program. .

The CPU 1 compiles an internal register 11, a source program created by a user, outputs the object instruction thereof, and a compiler 12 for scheduling a register file described later by a genetic algorithm (GA), and an object. It has an instruction execution unit 13 that executes an instruction while accessing the external memory 2 or the internal register 11.

The internal register 11 has a plurality of register files which are data storage areas in word units, for example, and is configured to store a part of the data stored in the external memory 2 in the register file. Has been done.

The function of the compiler 12 is shown by blocks, and the compiling unit 21, the gene pool storage unit 22, the fitness calculation unit 23, the gene duplication unit 24,
It comprises a gene crossover section 25, a gene mutation section 26, and a repetitive control section 27.

The compiling unit 21 sequentially reads each instruction in the source program and outputs the object instruction of the instruction, and the data necessary for executing the instruction is an internal register as described later in detail. It is determined whether or not it is stored in the file, and if it is not stored, the register file is specified based on each gene stored in the gene pool storage unit 22 described later, and the above data is stored in the register file. The object instruction for accessing the external memory 2 is output.

Further, the gene pool storage unit 22 stores a plurality of register file number sequences of the internal register 11 indicating the scheduling procedure as genes, and the fitness calculating unit 23 outputs the external memory 2 output from the compiling unit 21. The gene duplication unit 24 calculates the number of object instructions for accessing each gene for each gene and determines the fitness of each gene based on the number of instructions according to the fitness calculated by the fitness calculator 24. It is configured to replicate each gene.

Furthermore, the gene crossover section 25 crosses over each gene duplicated by the gene duplication section 24 to create a new gene, and the gene mutation section 26 is constructed by the new gene crossover section 25. Iterative control unit 2 so as to mutate some of the register file numbers that make up various genes to arbitrary register numbers with arbitrary probability.
The processing unit 7 is configured to cause the processing units 21 to 26 to repeatedly execute each processing a predetermined number of times, and to stop each processing after the predetermined number of times of execution.

In this embodiment, the compiler 12 is provided inside the CPU 1 for the sake of convenience, but in the present invention, C is used.
Tools outside CPU1 rather than inside PU1 (not shown)
Etc. having the function of the compiler 12, the tool compiles the source program created by the user, transfers the object program directly to the user program memory 3, and the user program memory 3 stores only the object program. You can

FIG. 2 shows the structure of genes used in the register file scheduling process by the genetic algorithm executed in this embodiment.

As shown in the figure, the genes are "2, 5,
3, 6, 1, ... "The register file number sequence is arranged based on the order of replacement of the register files indicating the data storage unit of the internal register 11, and in this case, it is" 2 ". Indicates that the number register file is replaced first.

Next, the register file scheduling process by the compiler 12 by the genetic algorithm will be described.

First, the data required for calculating the goodness of fit during the scheduling process will be described.

FIG. 3 shows data required for calculating the goodness of fit.

This data includes control data of a register file stored in the schedule management table T,
There is a total number of memory accesses (MEMACC) indicating the total number of accesses to the external memory 2 during program execution.

The control data of the register file includes three control data corresponding to the register file numbers R0, R1, ... Of each register file which is the storage area of the internal register 11, that is, the data stored in the register file. Channel address (table [] .address) and used / unused flag (table [] .on) indicating whether the register file is used or not use) and a modified flag (table [] .modified) indicating whether or not the contents of the register file are different from the contents of the external memory 2. Note that the usage / non-use flag (table [] .on us
For e), "1" is set when it is used, and "0" is set when it is not used. The modified flag (table [] .modified) is set to "0" if the contents of the register file have not been changed from the contents of the external memory 2, and "0" if the contents of the external memory 2 have been changed. 1 "will be set.

Next, a register file scheduling process using a genetic algorithm will be described.

FIG. 4 shows the entire scheduling process of this register file. In this processing, the order of each register file number that constitutes a gene is indicated by "j", and the gene [j] indicates the j-th register file number. Further, the order of each instruction constituting the ladder source program is indicated by "i", and the instruction [i] indicates the i-th instruction.

First, in the case of calculating the degree of conformity, the initialization processing of the control data in the register file described with reference to FIG. 3 is performed as shown in FIG. 5 described later (step 20).
0), and then set "0" to i indicating the order of the instruction in the ladder source program (step 21).
0), j indicating the rank of the register file number in the gene
Is set to "0" (step 220).

Then, the compiling unit 21 sequentially reads the instructions [i] of the ladder source program from the user program memory 3 (step 230), and at this time, the data exchanging unit 23 exchanges the register file for the instruction [i]. Whether or not it is necessary, that is, whether or not the channel data necessary for executing the instruction [i] is stored in the register file of the internal register 11 is determined as shown in FIG. 6 described later (step 240). .

If it is determined that the register files need to be replaced (step 240 "Yes"),
The register file of the register file number of gene [j] is replaced as the replacement target as shown in FIG. 7 described later (step 250), the value of j is incremented by 1 (step 260), and then the next instruction is issued. The value of i is incremented by 1 to specify (step 27
0). On the other hand, if it is determined that the register file does not need to be replaced (step 240 “No”), the value of i is incremented by 1 without replacing the register file or incrementing the value of j (step 27).
0).

Then, the data stored in the register file is read out to evaluate the instruction, that is, to judge whether the instruction is an OUT instruction or not and to output the object as shown in FIG. 8 (step 28).
0), then it is judged whether or not the instruction has reached the end of the ladder source program (step 290), and if the end of the ladder source program has not been reached (step 290 “No”), the next A new instruction [i] is read (step 230) and the same step 2 as above is performed.
Processes 40 to 290 are performed.

On the other hand, when the end of the ladder source program is reached (step 290 "Yes"), the calculation of the goodness-of-fit showing how superior this gene is to other genes is shown in FIG. 9 described later. Based on the total number of memory accesses (MEMACC) (step 30
0), and then it is determined whether or not the processes of steps 200 to 300 have been performed for all genes (step 310).

If all the genes have not been performed (step 310 "No"), the processes of steps 200 to 300 are repeated for other genes.

On the other hand, when all the genes are processed in steps 200 to 300 (step 310 "Yes"), the gene duplication unit 24 copies each gene to the corresponding gene as shown in FIG. Replication is performed according to the fitness (step 320), and then the gene crossover unit 25 performs crossover between the replicated genes as shown in FIG. 11 described later (step 330), and further as shown in FIG. 12 described later. The gene mutation 26 mutates some of register file numbers constituting a new gene after crossover to arbitrary register numbers with an arbitrary probability (step 340). This completes one generation of the genetic algorithm.

In the case of the genetic algorithm,
Usually, it is necessary to evolve or improve the gene to be the solution by repeating the processes of steps 200 to 340 for a predetermined number of times. Therefore, each time the iterative control unit 28 completes one generation, a predetermined number of generations is repeated. Whether or not it is determined (step 350), and when the predetermined number of generations has not been reached (step 350 “No”), step 200
The process from the fitness calculation to the mutation for each gene up to 340 is repeated, but when it is determined that the predetermined generation has been repeated (step 350 “Ye
s ”), the register file scheduling process ends.

In practice, it is possible to perform the calculation of the goodness of fit and the compilation at the same time.
It may be considered that the compatibility calculation unit 23 is included in 1 and the processes of steps 200 to 310 are performed by the compilation unit 21 and the compatibility calculation unit 23.

FIG. 5 shows in detail the initialization processing of the control data in the register file shown in step 200 of FIG.

In this process, first an initial value "0" is set in k (step 300), and the channel address (tabl
e [k] .address) is initialized (step 310) and then used / not used flag (table [k] .on use) is initialized (step 320), and the changed flag (table
[k] .modified) is initialized (step 330), k
Is incremented by 1 (step 340). And
It is judged whether or not such processing is repeated for the number of register files (step 350), and if it is not repeated for the number of register files (step 350 "N").
o ”), initialization is performed for each control data corresponding to the next k (steps 310 to 330), and when it is repeated for the number of register files (step 350“ Ye
s ”), the initial processing is terminated.

FIG. 6 shows in detail the register file replacement judgment processing shown in step 240 of FIG.

In this processing, first, an initial value "0" is set in k (step 400), and the use / non-use flag (t
able [k] .on It is determined whether the register file number k is used by referring to (use) (step 410), and then the channel address (table [k] .add).
By referring to (ress), it is judged whether or not the address matches the channel address of the data required to execute the instruction [i] read from the ladder source program (step 420).

Then, the register file [k] is used (step 410 "Yes"), and the channel address (table [k] .address) of the register file [k] is the channel address (Address of the data necessary for executing the instruction [i]. If it is determined that the register file does not need to be replaced, "0" is returned.

On the other hand, when the register file [k] is not used (step 410 "No"), and even when the register file [k] is used, the channel address (table [k] .address) is the same. When it is determined that the data does not match the channel address (Address) of the data required to execute the instruction [i] (step 410 “Yes”,
Step 420 "No"), the value of k is incremented by 1 (step 440), and it is determined whether the above processing has been repeated for the number of register files (step 45).
0) If it is not repeated for the number of register files (step 450 “No”), the determination process of steps 410 and 420 is performed with the new k, while
If the value of k is repeated for the number of register files (step 450 “Yes”), it indicates that the data necessary for executing the instruction [i] is not stored in the register file, and therefore the register file is replaced. Returns "1" indicating that it is necessary.

FIG. 7 shows in detail the register file replacement processing shown in step 250 of FIG.

In this process, k is first set to the register file number of gene [j], that is, the jth register file number from the beginning of the gene (step 500), and then that register file number is used. / Non-use flag (table [k] .on (use) is used to determine whether the register file [k] is being used (step 510) and the modified flag (table [k] .modified) is referenced to that register file [k]. It is judged whether or not the contents of the register file of the above are changed from the contents of the external memory 2 (step 52).
0).

If it is determined that the register file [k] is being used (step 510 "Yes") and its contents are changed from the contents of the external memory 2 (step 520 " Yes ”), and if necessary, the contents of the register file [k] are stored in the external memory (IO
M) The store type object instruction to be written to 2 is output (step 530) and the total number of memory accesses (ME
The value of MACC) is incremented by 1 (step 54)
0).

On the other hand, when the register file [k] is not used (step 510 "No"), and the register file [k] is used, the contents are not changed from the contents of the external memory 2. If it is determined that the result is (step 510 “Yes”, step 520 “N”).
o "), the data in the register file is not written to the external memory 2.

Then, in both cases, if necessary, a load-type object instruction for reading the data stored in the external memory (IOM) 2 into the register file [k] is output (step 550), and then the memory is continued. The value of the total access count (MEMACC) is incremented by 1 (step 560), and the register file [k] is used /
Unused flag (table [k] .on The use flag is set to "1" indicating use (step 570), and the changed flag (table [k] .modified) is set to "0" indicating no change from the contents of the external memory 2. (Step 580), the channel address (table
The address (Address) of the instruction is set in [k] .address) (step 590).

FIG. 8 shows the evaluation processing of the instruction shown in step 280 of FIG.

In this processing, the read instruction [i]
Is an OUT type instruction (step 6
00), only for OUT type instructions (step 600
"Yes"), and the modified flag (table [k] .modified) of the register file [k] is set to "1" indicating that the content of the register file has been modified from the content of the external memory 2 (step 610), and then the compiling unit 21 outputs an object according to the instruction (step 620), and this evaluation process ends.

FIG. 9 shows an example of a function used in the fitness calculation processing shown in step 300 of FIG.

The goodness of fit is "fitness = f (MEMACC)", that is, a function f of the total number of memory accesses (MEMACC).
It is calculated by. As the function f, a function that returns a larger value as the total memory access count (MEMACC) becomes smaller, that is, the adaptability increases as the total memory access count (MEMACC) becomes smaller, for example, (a)
Examples thereof include a linear function as shown in and a sigmoid function as shown in (b). FIG. 10 shows step 320 of FIG.
The replication process of the gene shown in is briefly shown. In the duplication process, the genes a and b are created according to the goodness of fit, that is, the larger the goodness of fit is.

FIG. 11 briefly shows the gene crossover processing shown in step 330 of FIG. 2 in crossover processing
Register file number sequence "987654", "123456" that constitutes genes a and b between two genes a and b
At the same position (indicated by "^" in the figure), and replace the first half (or second half) of each
A gene c consisting of a register file number sequence "987456" and a gene d consisting of a register file number sequence "123654" are created.

FIG. 12 briefly shows the gene mutation process shown in step 340 of FIG. In the mutation processing, when the mutation is to be caused to the gene a as described above, the register file number sequence “12” of the gene a is used.
For example, the fourth bit "5" of 3456 "is changed to another arbitrary register file number" 9 ".

As described above in detail, in the present embodiment, the compiler 12 in the CPU 1 has the compiling unit 21.
When the source program is compiled by, the register file is scheduled using a genetic algorithm, the register file is replaced based on each gene that is the scheduling procedure, and the fitness is calculated for each generation. Are evolved by repeating replication, crossover, and mutation for a predetermined generation according to their fitness.

Therefore, as the generations are repeated, genes having a higher degree of conformity, that is, the number of times of accessing the external memory 2 is smaller, remain and the ratio increases, and the scheduling processing of the register file is performed based on the genes. Therefore, when the instruction execution unit 11 executes the compiled object program after repeating the predetermined generation, the number of accesses to the external memory 2 is reduced, and the program execution time can be shortened. .

It should be noted that, when starting from a completely random value as an initial value of a gene, it is possible to obtain an excellent result in some cases as compared with a method in which the value of a gene having a certain degree of goodness is initialized by half of the total number of genes. I understand.
From this, if too many genes are determined as solutions in the initial state, the diversity of genes will be limited from the beginning, and it will be difficult to converge to the optimal solution, that is, it will be difficult to generate better genes. In the calculation of the scheduling procedure of the register file, various genes are required.

[0058]

As described above, according to the present invention, a genetic algorithm is incorporated into the scheduling process of the register file, and the register file number sequence indicating the order of replacement of the register file, which is a scheduling procedure, is used as a gene, and the source program Register files are replaced based on each gene at compile time, the fitness is calculated for each generation, and genes are evolved by repeating the process of duplicating, crossing, and mutating each gene according to the fitness for many generations. Let

For this reason, as the number of generations is repeated, the proportion of genes having a high degree of compatibility, that is, the number of times of accessing the external memory is small, increases, and the scheduling processing of the register file is performed based on the genes. , When the processor executes the object program, the number of accesses to the external memory decreases,
The program execution time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a PLC according to the present invention.

FIG. 2 is an explanatory diagram showing the structure of a gene adopted in the scheduling process of this example.

FIG. 3 is an explanatory diagram showing data required for calculation of fitness.

FIG. 4 is a flowchart showing a scheduling process of a register file.

FIG. 5 is a flowchart showing a control data initialization process.

FIG. 6 is a flowchart showing register file replacement determination processing.

FIG. 7 is a flowchart showing a register file replacement process.

FIG. 8 is a flowchart showing an instruction evaluation process.

FIG. 9 is an explanatory diagram showing an example of a function used in a fitness calculation process.

FIG. 10 is an explanatory diagram showing a gene replication process.

FIG. 11 is an explanatory diagram showing a gene crossover process.

FIG. 12 is an explanatory diagram showing a gene mutation process.

[Explanation of symbols]

 1 CPU (processor) 2 External memory 3 User program memory 11 Internal register 12 Compiler 13 Instruction execution unit 21 Compile unit 22 Gene pool storage unit (Gene pool storage unit) 23 Fitness calculation unit (Fit calculation unit) 24 Gene replication unit (Gene replication unit) 25 Gene crossover unit (Gene crossover unit) 26 Gene mutation unit (Gene mutation unit) 27 Repeat control unit (Repeat control unit)

Claims (1)

[Claims] 1. A programmable controller including a compiler that compiles each instruction in a source program and outputs an object instruction thereof, and outputs an object instruction that replaces data stored in an internal register based on a scheduling procedure. Therefore, the compiler sequentially reads each instruction in the source program and a gene pool storage unit that stores a plurality of register file number sequences of internal registers indicating the scheduling procedure as genes, and outputs the object instruction of the instruction. , Determines whether or not the data required for executing the instruction is stored in the register file of the internal register, and if not stored, based on the genes stored in the gene pool storage means. Register file , A compile means for outputting an object instruction to access an external memory so that the data is stored in the register file, and a number of object instructions for accessing the external memory output from the compile means are calculated for each gene, The fitness calculating means for obtaining the fitness of each gene based on the number of instructions, the gene duplicating means for duplicating each gene according to the fitness determined by the fitness computing means, and the gene duplication means Gene crossover means for crossing over each gene to create a new gene, and a gene for mutating some of register file numbers constituting the new gene created by the above-mentioned gene crossover means to any register number with an arbitrary probability Mutation means, the compiling means, the fitness calculating means, the gene Ltd. unit, a programmable controller, wherein for a predetermined number of times repeatedly executed each processing comprises a repeating control means for stopping each of the process after a predetermined number of executions that the said gene crossover means and the genetic mutation means.