JPH07118732B2 - Digital signal processing system - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to functional programmable pulse code modulation data analyzers and transmitters used in telecommunications equipment.

[0002]

2. Description of the Related Art Generally, pulse code modulation (hereinafter referred to as PC
M) The data analysis device is used in a digital telecommunications system for voltage power, frequency, and DTMF (dual-tone multifruit).
frequency) signal characteristics such as detection and a variety of other information characteristics. These devices are typically externally connected to telecommunications equipment. Such an external device
Analog-to-digital conversion is required, and the circuit elements of such devices, when installed in switches of telecommunications systems, often require programming to perform special functions.

[0003]

The present invention overcomes these deficiencies of the prior art and is integrated into telecommunications equipment, and further, programmable data to address different functions at different times. An analysis device and a transmitter are provided.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal processing system which interfaces with central control means having at least one control port. The present invention includes processing control means having an interface port connected to the control port of the central control means. The processing control means also includes at least a first
Port, a second port, and a third port.
At least a first kernel means, a second kernel means, and a third kernel means for executing a software application task are provided in the first port, the second port, and the third port of the processing control means. ,Each,
It has the 1st port, 2nd port, and 3rd port which are connected, respectively. Each of said kernel means has a plurality of channel ports connected to a bus means having a plurality of channels. The processing control means,
Processing in response to data received from the central control means to establish one of a plurality of software application tasks within each of the kernel means. The bus means has at least the 24 channels, and each of the kernel means communicates with 8 of the 24 channels such that each kernel means receives a different channel than the other kernel means. . The 24 channels are pulse code modulated and 0 to 23
, The first kernel means communicates with channels 0, 1, 6, 7, 12, 13, 18, and 19, and the second kernel means communicates with channels 2, 3, 2.
8, 9, 14, 15, 20, and 21, and the third kernel means are channels 22, 23, 4,
5, 10, 11, 16, and 17. Each of the kernel means has a channel port of each of the kernel means configured by the multiplexing and demultiplexing means so that each kernel means communicates with the channel for each of the kernel means of the 24 channels. Connected to the means.

Each of the kernel means has a processing means, and the software application task has DTMF detection and MF (medium frequency).
y) At least one of detection and metering is included. To each of the kernel means, any one of the application tasks is individually designated by the processing control means.

The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention, together with its numerous other objects and advantages, will be better understood by reference to the following description in connection with the accompanying drawings. Throughout these drawings, the same reference numerals identify the same components.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has general applicability, but is most advantageous for digital signal processing implemented on a digital signal processing (DSP) card, such as that shown in FIG. Used. In the preferred embodiment, D
The SP card 10 performs DTMF and MF detection and other functions. Typical automatic call distribution (autom
atic call distribution: AC
D) Application includes one DSP card with another card as a backup. The DSP backup card can be used as a digital multimeter for system connection to various lines for testing purposes, while the digital audio source backup card can be used for message recording and editing.

For clarity, the network control structure outside of the DSP card 10 is referred to herein as the central controller 20. The controller on the card is a 68000 microprocessor, and the three application microprocessors 14, 16, and 1 on the card are
8 is called a DSP kernel.

Each of the three DSP kernels 14, 16, and 18 on the DSP card can be configured for one of several functions. Three of these functions, MF detection, DTMF detection, and measurement, are included within the preferred embodiment of the present invention and add new functionality to this same hardware by adding subsequent software. You are given a way.

Each DSP card 10 has three cards.
It can support any combination of two software applications. For example, DSP card 1
0 is three applications of DTMF detection, MF
It may be designated by the central controller 20 to be either three applications of detection or a mixture of three different applications. The term application refers to code executing within each DSP kernel 14, 16 or 18. Each application serves more than one channel. Central controller 2
After the 0 downloads software to the DSP kernels 14, 16 and 18, each kernel continuously monitors each piece of hardware assigned to the channel. Upon completion of the application task, the DSP kernel will return the results to the 68000 microprocessor 1.
Report to 2. The 68000 microprocessor 12
It then responds to the central controller 20.

In the ACD environment where only a small number of DTMF detection channels are required, a typical configuration is one DTMF application on a single card, one
One MF application and one meter application. Only one D in the system
There will be one SP card and one backup card.

A tandem switch that requires a very large number of channels for both DTMF and MF.
In a switch environment, each card is
There will be three or so dozens of cards, either DTMF or MF, in the system. Again, one card can be the backup card.

The central controller 20 here refers to any part of the control structure that is present outside the DSP card 10 (see FIG. 1). The card is the central control unit 2
0 shows three sections programmable resources.
Control microprocessor (MC680 on DSP card)
00) 12. The control microprocessor 12 is
Controls the entire card, i.e. central controller 2
0 mail information, access to (unknown) serial control link, 3 DSP kernels 14, 16 and 18
Control and dial pulse information (dial pulses)
e information) collection.

Each DSP kernel includes a microprocessor, memory, an interface to the 68000 microprocessor, and an interface to the PCM highway. One of several applications may be downloaded into each of the three DSP kernels. The three released applications are, for example, a DTMF detection function for 8 channels, an MF detection function for 8 channels, and a digital multimeter function for 8 channels.

As shown schematically in FIG. 2, the card appears to the central controller system as a number of channels equal to the number of downloaded applications. For example, when a DTMF register is required at the level of the central controller, the list of available registers is examined and one of them is specified.
This instruction is received by the 68000 microprocessor 12, which issues the instruction to the appropriate DSP micro on the card.
The DSP micro then designates the detector and upon receipt of a valid digit, the digit code is 6
Return to 8000 microprocessor 12. 6800
The 0 microprocessor 12 has the option of collecting digits before reporting them to the central controller 20. If a valid digit is not received by the DSP Micro after some time, then 68
The 000 microprocessor 12 notifies the central controller 20. The DSP micros designated by the 68000 microprocessor 12 are then dedesignated or the designations are continued.

FIG. 3 illustrates communication with the DSP card 10 through the serial control link and PCM highway 22. 24-channel PCM data as well as control link information passes over the link 26. Custom multiplex and demultiplex integrated circuit (NLI IC) 2
4 performs these operations. 24 channels P
The CM data is then further demultiplexed and connected to the three DSP kernels 14, 16 and 18.

Before entering the functional description, a few terms will be defined. The term firmware applies to program code within the DSP kernels 14, 16 and 18 and program code for the 68000 microprocessor 12 that interfaces with the hardware elements (input / output interface). This code is basic in nature, and all application programs (such as DTMF, MF, etc.) interface with this code as well. Therefore, there are two types of firmware, C25 firmware and 68000 firmware.

On the other hand, the term software means an application program that has no connection with input / output and is independent of the hardware configuration. Therefore, the software is the actual application task performed by the microprocessor on the DSP card.

The software residing on the DSP card for the 68000 microprocessor is
Responsible for some control matters. 6800
The 0 microprocessor must handle communication with the central controller 20 through the receive and transmit buffers of the NLI IC 24.

The 68000 microprocessor also performs the functions associated with digit string collection. In addition, the 68000 microprocessor is
It must receive the A signal from I24 and can calculate the correct dial pulse sequence. During initialization, the 68000 microprocessor runs its own program and each DS.
You must download the P kernel program.

The 68000 microprocessor must perform self-diagnosis and can take appropriate action to identify the faulty DSP kernel and reset the DSP kernel. Each DSP kernel includes a general purpose high speed digital signal processor capable of performing real time operations on digital data being received from the NLI through the PCM highway. Thus, the kernel processor can perform a wide variety of types of application tasks for the system.

The DSP kernel also performs self-diagnostics to verify the integrity of both hardware and software. The 68000 microprocessor periodically commands the DSP kernel to cause the DSP kernel to perform a check of the contents of the program RAM and expects the kernel processor to respond to the discovery.

The 68000 microprocessor 12
Monitors the input buffer to communicate with the DSP kernel. When one kernel processor writes data to the 16-bit register of the 68000 microprocessor 12, one bit in the input buffer is activated. When the 68000 microprocessor 12 detects this activation, it responds by reading the register to collect new information. The read operation then resets the bit and signals the kernel processor that the new data can be written into the register.

The new data from the central controller 20 is the DSP
When reached from card 10, NLI 24 will be 68000
Enable interrupts to microprocessor 12. 68
000 microprocessor 12 in response reads the receive FIFO of NLI 24 while in the interrupt routine.

The kernel processor firmware is a program code existing in the DSP kernel, and defines the hardware environment of the TMS320C25 processor. After the software is downloaded to the DSP kernel, the firmware reads and writes from the PCM data stream, receives instructions from the 68000 microprocessor, and returns the results to the 68000 microprocessor.

The kernel processor is the 6800.
Monitors the input buffer to communicate with the 0 microprocessor. When the 68000 microprocessor writes data to the kernel processor's 16-bit register, a bit in the input buffer is activated.

When the kernel processor polls the input buffer for activation, it responds by reading the 16-bit register to collect new information. The read operation then resets the bit and signals the 68000 microprocessor that new data can be written into the register.

The input pins of the kernel processor are N
8kHz framing pulse signal from LI24 is detected. This signal, when activated, indicates that a new frame of information is
Indicates that the channel counter should be reset to zero.

68000 microprocessor kernel 1
2 is 68000 CPU, 32K x 16 RAM, and 3
It consists of 2K x 16 ROM. Memory chip and another PA
L (programmable array logi
c) When a chip (DSPPALOB) is added to the card, an additional 32K words of RAM can be added to the card. The main information in the ROM is self-boot (self boot), link communication primitive (l
ink communication primiti
ve), and diagnostic tests. All programs from the DSP kernel and the 68000 microprocessor are downloaded through the NLI control link interface that connects to the control complex. This downloadability allows for a great deal of flexibility in later software changes. Also, NLI
24 to communicate control information, transmit serial data, P
CM dial pulse data (PCM dial pulse)
There are also some registers for receiving (se data).

Real-time DMA (direct-memory) communication with each of the DSP kernels 14, 16 and 18 and to the kernel program memory bank.
There are several control registers that have the ability to perform access functions. In future releases of the software, support will be provided for the DMA function.

Each DSP kernel 14, 16 or 18
Appear on different memory addresses for the 68000 microprocessor 12. This allows the 68000 microprocessor 12 to individually load the program memory of each DSP kernel 14, 16 and 18. The output registers of the 68000 microprocessor 12 are the DSP kernels 14, 1
Control the reset mode and hold pins of 6, and 18 individually.

The 68000 microprocessor 12 has the ability to detect or mask bus errors while accessing external memory or other devices. If the above 6
If no data transfer grant was received from the external device accessed by the 8000 microprocessor after a predetermined rest period, then a bus error would have occurred. In this case, an exception handling routine is forced to occur on the 68000 microprocessor. This occurs, for example, when a 68000 microprocessor 12 is trying to access the DSP kernel's memory before placing it in its hold state. The bus error exception handling routine inspects the contents of the stack to determine the defect occurrence location.

The 68000 microprocessor 12 also interfaces with write protected storage circuitry. One 8-bit register is a 68000 microprocessor 1
Two 32K word RAM 34 blocks of 4K words can be protected. An additional 8 lines are available for protection of 32K words of memory that can be added on the DSP card. DSP kernel 14,
Each of 16 and 18 can interrupt the 68000 microprocessor 12.

The circuit configuration is similar for all three DSP kernels. This commonality prevents the generation of kernel special software that limits the types of applications that can be executed on the card.

The DSP kernel is a TMS320C25 (C2 with a 4K × 16 high speed static RAM).
5) Digital signal processor kernel, and 6800
It includes a control register that allows passage of 16-bit information between 0 and the C25, and an address decoder.

The C25 individually addresses 64K programs, data, and I / O space. Program space and some data space for the processor resides in 4K of RAM in the kernel. A data space of the processor is internal to the processor and has a storage capacity of 512 words. The I / O space of the processor accesses the 16-bit read / write register to communicate with the 68000 microprocessor 12 while not in hold, and the 68000 microprocessor 12 has new information in the message register. Status port (status p
ort).

The 68000 microprocessor 12 has the ability to force a hold mode on the C25 processor. While in the hold mode, the C25 processor halts program execution and places all address and data lines in a high impedance state. This mode also allows the 68000 microprocessor 12 to access the program memory of the C25 kernel.

In the NLI kernel, the DSP card has a system backplane (system backp).
circuit self-control device (hereinafter, NS)
C) includes the circuit elements necessary to communicate. This allows the passage of control commands and data to the DSP card, correspondingly indicating the tasks that the card will perform and report. Through the use of the NLI IC and PCM communication circuitry, the DSP card can communicate with the rest of the system.

During both the serial PCM reception and transmission operations of the C25, a switching circuit (commutatin) is used.
g circuit) sequentially sends PCM data to each C2
Divide 5 into groups of 2 channels. Therefore, the lines designated for each C25 are fixed and in a predetermined sequential order. The switching circuitry includes a counter, which is connected to the C25
Generate a pulse to signal the start of transmission or reception of M serial data. The NLI is an ASIC (app
license specific integral
ted circuit) and includes the logic circuits necessary to communicate through the driver and receiver, and through the backplane.

The serial highway carries multiplexed PCM data and control data to and from the DSP card. The control link will carry bi-directional information, but here control information flows from the central controller 20 to the 68000 microprocessor 12 and reporting or status information is 6800 for ease of explanation.
Suppose that flow is from 0 microprocessor 12 to central controller 20.

The software handles all input and output mail to the DSP card. Mail queues are maintained bidirectional to ensure regular flow to and from the DSP card.

Inherent in the DSP card (as well as all other cards that use the NLI bus) is to insert the NLI bus in the state of "switching" PCM samples, and " It is the ability to extract the NLI bus in the "from switch" state. As a system integrity test, a digital test tone from the DAS module is sent to the DSP module for detection through the network link.

A register / transmitter pair is acquired and the tone digit (tone) is acquired.
digit) is transmitted between these two. If the transmitted digits match the received digits, then there is a high probability that both of the pair are working correctly. Since these digits are transmitted through the TSI card via the NLI bus, further tests are performed on the pad / gain function (P
ad / Gain feature). This involves adding padding and / or gain to the transmitted digits and observing whether the receiver recognizes the digits as still valid. In order to check system integrity, the DAS
Both of these tests between the module and the DSP module are performed.

A section of the 68000 microprocessor 12 must maintain contact with each DSP kernel and each channel. One way to achieve this function is to maintain a list of state and reporting tables for each DSP kernel. 68
The 000 microprocessor 12 inspects the status of each device and takes appropriate action.

The firmware is written to indicate the format common to the software within the 68000 microprocessor 12. A one word message is sent between the 68000 microprocessor 12 and the C25. When the 68000 microprocessor 12 resets one DSP kernel, the kernel clears the flag in the message register, invalidating any current data.

The above section deals with the protocol and data transfer between the 68000 microprocessor 12 and the TMS320C25 CPU. C25 and 680
There are two main interfaces to the 00 CPU.

The first of these interfaces is the download interface. It is only used to load the initial program. 680
The 00 CPU resets the C25, puts the C25 in the hold state, and loads the intended application program into its program memory. Second
Is an input / output port interface. The I / O ports on each CPU are tied together and handshaking techniques are used to ensure that communications are transferred correctly between the CPUs. This interface is used to transfer information while the C25 is running.

In the preferred embodiment, there are three separate application programs, these are 68000.
It is downloaded from the microprocessor 12 to the C25. One of these programs is DTMF
It is a tone detection program. The program detects a 40 millisecond DTMF tone and reports this event to the 68000 CPU. The other one is
It is an MF tone detection program. The program is M
1 of 2 tones for F tone detection application
Detect any of the 5 combinations. The last one is measurement. An AC or DC voltmeter and a frequency coefficient device are provided to perform some analog testing within the switch. The program is less than 1,000 words.

All of the above programs have the normality test capability (program memory checksum) executed in the background mode. The main task of the C25 is to perform one of the real-time functions listed above. Each program is time division multiplexed (t
to generate an 8-channel capability. Initial interrupt
For ring), all 8 channels associated with a given C25 are dedicated to performing the same task. From this, ie, it is not possible to have 4 channels of DTMF and 4 channels of measurement on a single C25.

The C25 program uses almost all of its available RAM and most of its CPU time. As a result, the C25 operating system is extremely simple. The PCM sample is
Flexible buffer (elasti) during real-time interrupt
c buffer). The background mode of operation provides for execution of the 68000 CPU interface routines and download programs.

Real-time interrupts occur every 31.25 microseconds. Each interrupt of approximately 2 microseconds is required to store the PCM sample. When the interrupt handling routine is completed, the background task is executed. The interrupt handling routine uses a minimum of 10 to avoid re-execution of the interrupt handling routine.
Instruction cycle
Must be of length. This is because the interrupt on the C25 processor 36 is both edge and level sensitive, and the interrupt pulse is 970 nanoseconds long. Therefore, if the interrupt handling routine completes its task within 10 cycles,
Other interrupt handling occurs.

Upon completion of one background task, the C25 returns to the idle loop to find a new task. The tasks are prioritized in the following order:

1) Processing PCM samples. If there are unprocessed PCM samples in the flexible buffer, the samples are processed according to the application being downloaded. 2) Service for 68000 I / O requests. The I / O status register is checked for instructions from the 68000 and placed in the instruction queue. 3) Check sum testin
g). If there are no other tasks, a few words of program memory are checksummed.

The initialization of the three C25 processors is
POR signal from NLI (power-on reset signal)
It starts with the reception of. The POR signal is automatically
Reset all C25s and put them in hold.
After the 68000 microprocessor 12 has loaded all the software code from the control complex, 680
The 00 microprocessor 12 starts loading each 4K program / data space of the C25. When the loading of the program is completed, the 68000 will display the C
Release the control of 25 reset and hold lines,
The program can be executed at "address>0000".

The first software code executed by the C25 is the status register S of the C25 processor.
It starts with the initialization of T0 and ST1. The following is a list of register settings for the preferred hardware:

FO = 0 Configure a serial port for 16 bits. Command: FORT 0 HM = 1 C25 is executed in hold mode. Not used in this release. Instructions: SHM ITM = 0 Enable interrupts. Enable serial port operation. Command: EINT IMR => 0010 Serial port receive input (ser
ial port recv int is enabled and NLI clock input (NLI clock in) is enabled.
t) and serial port transmission input (trx serial)
Disable lint) (not used). Command: load data loc 0004 with>
FSM = 1 Supplies the frame pulse required for serial port operation. Command: SFSM TXM = 0 Send frame pulse in input.
Order: RTXM

Another process completed by the C25 processor 36 is to load the data space memory internal to the C25 with a constant from the program space memory. The TBLR instruction enables the transfer of this information into the data space memory.

Other software instructions allow the C25 to utilize I / O space to communicate with the 68000 master processor. The C
25 has two input ports and one output port to accomplish this task. Input port 0 and output port 0 are two 16-bit registers that enable data transfer between the 68000 and C25 while both are processing information. Input port 1 acts as a status register for the C25, which controls the transfer operation of the C25 so that no information is lost.

When the C25 writes data to the data register for the 68000 at output port 0, one bit is reset by a flip-flop, signaling the 68000 that data is available. When the 68000 reads this location, the flip-flop will set indicating that more data can be transmitted. This bit can be read by the C25 and is bit 1 in input port 1.

Similarly, the 68000 is added to the C25 by 1.
When writing a word, bit 0 of input port 1 is reset. The C25 periodically polls input port 0 to determine if information is available by testing that bit 0 is a logical "0". The following is the C that performs this function.
25 software samples.

IN STAT, 1; STORE TRANSFER
STATUS IN DATA MEM LOCTN LAC STAT; PUT TRANSFERS
TAT IN ACCUMULATOR ANDK>0001; CHECK FLAG FOR
DATA FROM 68K. 0 = TRUE BGZ NO MSG IN 68K RD, 0; READ I / O PORT
0 FOR MESSAGE AND STORE IT ··· NO MSG: · (Continued)

The PCM data includes the NLI and the C25.
Is serially transferred to and from. The C25 receives and transmits a specified group of channels set in hardware.

[0063]

Table 1 Channels used by NLI C25A 0,1,6,7,12,13,18,19 C25B 2,3,8,9,14,15,20,21 C25C 22,23,4,5 , 10, 11, 16, 17

Therefore, each C25 receives the information of 8 channels. This PCM data has 16 bits (2
Channel) into the C25. The smaller numbered channels here are in the higher byte of the DRR data receive register. Once this register is filled, an interrupt will occur and the two channels of PCM will be available for processing in the DRR. The C25 is interrupted every 31.25 microseconds with new channel information for reception and transmission. There is a channel timing offset between the receive and transmit functions and these interrupt functions do not occur at the same time. The C25 uses a BIO pin, which is one input / output pin on the processor
Synchronize the reception of M.

The BIO pin is a software testable input / output pin used by the C25 for a test for starting the frame pulse. The frame pulse occurs every 125 microseconds and has a duration of approximately 647 nanoseconds. The C25 monitors the state of the BIO pin in a short loop because the duration of the frame pulse is only 970 nanoseconds to determine when the frame starts, and an internal software channel. Reset the counter.

There is a channel count difference between the receive channel and the transmit channel, so two sync frame inputs connect to the C25.

The DSP card is divided into three main subsections and a power supply, which are the DSP kernel, the 68000 kernel, the NLI kernel, and the interface. The 68000 is an intelligent queue of messages.
euing) and communicate with the central control system via the several links. That is D
Controls input to the SP kernel.

The 68000 processor distributes the request message from the mailbox to the appropriate place in the DSP kernel to send the completed task to the DSP.
It is responsible for monitoring the kernel's reporting registers. The processor also checks for changes in the status request issued by the central controller on each channel and forwards the status request to the appropriate working channel.

3 and 4 show circuit element blocks for downloading program memory contents to the DSP kernel. As shown in these figures, the hold signal places the C25 in a high impedance state and activates the hold acknowledge line, which places the memory contents of the C25 within the 68000 memory map. The ROM is 32K × 16.

The program RAM for the 68000 microprocessor 30 is provided as 32K × 16 RAMs 32 and 34. The program RAM can access words or bytes. Two 32K x
8 additional RAM chips and DSPPALO
Extension to 64K words is possible by replacing A with DSPPALOB. The DSPPALOA is
No chip selection for optional RAM space occurs.

Each TMS320C25 processor 36 has four
It has K words of memory, which is accessed by C25 as a program or data space.
That is, the 4K × 16 memory bank 38 is
00 puts the DSP processor in hold, the 68000 address spectrum (add
switch to the (ressect spectrum). Therefore, the 68000 reads or writes the contents of the memory of the C25 in word access format. It is worth noting here that the 68000 puts the C25 in reset mode after downloading new program material in order to put the C25 in a known new state. If one intends to write to these areas of the memory without activating the hold bit for the kernel, it will result in a bus error. The memory is the 68000.
Only word access is possible. If a byte access operation occurs in the memory space, an incorrect data transfer will occur.

The 82C55 I / O port 40 is used to enable write protection for the RAM. Each I / O line protects 4K words of memory from unauthorized write operations. This part is initialized to address OEOOC6H with 80H after a reset has occurred. After that, the address OEOOC2H or OEOOC
Writing a bit "1" at 4H protects a given 4K block of RAM when the write protection function is activated. When a write cycle attempts to access a protected memory location, a bus error occurs signaling the processor of the violation. The 82C55 register as well as the protected memory can be read at any time. If writing to the protected memory or writing to the ROM while the write protection lock is active, the result is a time out bus error (time o).
ut bus error).

16-bit data registers 42 and 4 for communication between the 68000 and the DSP kernel
4 are provided. One of these registers is for reading the content and the other is for writing the data. Because they are clearly distinguished, no single processor will read the same content that is written to the register. Each DSP kernel has an associated set of registers for data transfer. These registers must not be read or written before the appropriate bits in the interprocessor registers have been examined.

The interprocessor register is the 6
Coordinates the transfer of information between the 8000 and the DSP processor on the front card. This register can only be read. Bits in the register are set when a write to a register occurs and set when the register is read. Bits 0-2 in the interprocessor register are active low logic level,
Instructs the 68000 that the C25 has new data written to the register and that it should read its port. After reading the address, the bit indicating the message is reset. Bits 3-5 are the C when active low logic level.
25 indicates that the contents of the data register from the 68000 have not yet been read. This indication causes the pre-C25 to be monitored for whether the register was not read before the timeout expired. However, the data will overwrite any current data stored if it is written to the register. Bits 6-7 are the C25 processor 36 at 68000 when active low logic level.
Indicates that either of the processors A or B has requested the interrupt of the processing routine.

The miscellaneous port controls various devices on the DSP card. Receipt of the POR signal causes all output bits to go to a low logic level, which is active for many of the devices connected to the miscellaneous ports. Different registers are selected for read operations as opposed to write operations. However, both of these operations must be done with word length access.

When a write operation occurs, the next bit is activated. Bit 0 activates a red LED on the faceplate of the card, which indicates that the card is malfunctioning and needs to be replaced. Bit 1 activates the green LED on the faceplate of the card, thereby indicating that the card is operating properly. Bit 2 activates a yellow LED on the faceplate, thereby signaling that removal of the card affects a channel of the system. Bit 3 connects to the back for testing purposes. Bit 4
Deactivates the write protection function at low logic levels, causing a bus error when attempting a write operation to a protected memory location. Bits 5-8 are not used. Bits 10-12, when activated,
Place the DSP kernel in hold mode. Finally, bits 13-15 cause the DSP kernel to reset.

The signal from this port is read back to determine the state of these bits. Reading this address causes the hold and reset states of the C25 kernel, the write protect lock, and the LED and test bit states shown in the preceding paragraph.

The bus error signal is the program RA.
It is used to detect attempts to access write protected areas such as M, EPROM, or unused memory space. When such a situation occurs, the bus error signal is generated and input to the BERR pin (bus error pin) of the processor. This BERR signal is also used to complete the operating bus cycle and start the bus error exception routine.

The bus error signal resulting from a write to a protected RAM area is written to the control register as Writ.
e PRT It is disabled by declaring the OFF ~ (write port off) bit. This allows the processor to write to the protected RAM area without causing a bus error. R
Writing to the OM always results in a bus error. The memory access timer is always activated, and if an invalid memory cycle is detected, even if the Write
PRT Causes a bus error even if the OFF-bit is declared.

These addresses, when written, clear the appropriate C25 interrupt request connecting to the 68000. The 68000 must either write to this port after entering the interrupt routine or continue to perform interrupt functions. C2
5A interrupts at level 4 of the 68000 and C25
B interrupts at the same level 4, and C25C has the above 6800
Interrupt at level 6 of 0. Since both C25A and C25B interrupt at the same level, the interprocessor registers must be read to determine the cause of the interrupt, and then the 680
00 must write to the appropriate address to clear the interrupt.

The 68000 processor is reset upon power up or receipt of a reset command from the control link. The power-on reset (POR ~) signal is at least 1 after the power supply voltage (VCC) reaches 5V DC.
It has been activated for 00 milliseconds. This signal is
Drive both the reset and hold inputs of the 8000 processor to ensure proper start mode.

In normal operation, the serial link from the DSP card is periodically polled by the NSC card to determine activity on the link. If there is no response, this causes the NSC card to have a non-maskable interrupt (Non-Mastable Int).
error) (interrupt level 7) through the DSP
Generate a soft reset on the card. In addition, the inactivity at this point causes the NSC to generate a hard reset through the POR ~ circuitry to reset the entire card.

The non-maskable interrupt from the NLI IC also acts as a watchdog timer on the DSP card. The DSP card must respond to this interrupt to avoid a hard reset from the NSC. Whenever the reset line is activated, all lamps on the front faceplate must be illuminated and extinguished by the 68000 software. Upon receiving the POR ~ signal, the DSP kernel automatically enters a hold and reset state. Check the program memory of C25
You can wake it up at this time.

The generation of an interrupt on the DSP card is
These are the results of the timer interrupt request, the NLI communication interrupt request, the NLI soft reset (monitoring timer) interrupt request, and the C25 interrupt request. An automatic vector interrupt is used on the DSP card to save physical space,
And meet all required interrupts. The interrupt level designation is as follows.

Level 7-NMI-Soft reset from the network link. Level 6-C25 INT-C25C interrupt request. Level 5-NLI INT-Available information from the network link. Level 4-C25 INT-C25B and / or C25
Interrupt request from A. Level 3-Test Int-Interrupt for test technical purposes. Level 2-10 MSEC ~ -1 from the NLI IC
0 millisecond interrupt. Level 1-Time interrupt. This interrupt indicates the presence of the A signaling bit and occurs every 1.5 milliseconds.

All interrupt sources are connected to the priority encoder and the output of the priority encoder is connected to the interrupt priority level pin on the 68000. The 68000 function control output line signal is then decoded as an interrupt acknowledge signal. This IACK signal (interrupt acknowledge signal)
Is input to the VPA read to start the exception handling processing.

Each external memory or I / O access of the 68000 processor requires an asynchronous DTACK signal to complete one cycle. The processor is
Supports various device speeds. These speeds are
ROM and 500 nanoseconds for the 8255, 40 for RAM
0 nanoseconds and about 400 nanoseconds for an input / output device.

The address strobe and address decode signals are gated together to generate the DTACK signal. At the beginning of a processor cycle, the counter loads an equivalent value of 6.4 microseconds and if DTAC
If the K signal is not available during this time, a bus error has occurred, which indicates a failed cycle.

The microprocessor 36 uses the TMS3
20C25, which is a general-purpose high-speed microprocessor. It operates at 40 MHz and has a 100 nanosecond instruction cycle timing clock signal. 40M
The frequency of the Hz clock signal is 10 MHz internally in the C25.
It is divided by z and the resulting divided signal clocks the 68000.

The C25 processor 36 physically divides data, programs and I / O space into three different address banks. The data and program memory spaces, as currently implemented in hardware, are combined as shown below. The 4K × 16 program memory space starts at “address> 0000”. The C
The block of internal memory for 25 is either program space or data space and can be specified by executing software instructions.

The C25 uses three input / output addresses for communication with the 68000. Port 0 is the data register address, which allows 16 bits to be read from and written to the 68000. Port 1 is a read-only address, which produces status information about the messages between the 68000 and the C25.

When the C25 writes data to the 68000 data register at the output port (OUT) 0, 1 bit is reset by a flip-flop to signal to the 68000 that data is available. To do. When the 68000 reads this location, the flip-flop sets to indicate that more data can be sent. The bit is read by the C25 and bit 1 of input port (INP) 1
Is.

Similarly, the 68000 becomes 1 in the C25.
When writing a word, bit 0 of input port 1 is reset. The C25 periodically polls input port 0 to determine if information is available by testing that bit 0 is a "0".

The C25 has the ability to send PCM data to the NLI. The DX pin connected to the drive line of the C25 is a high impedance driver, which driver is sequentially selected by the circuit elements connected to the NLI.

Serial PCM data is clocked into the C25 by the NLI sequence circuitry which generates the receive frame sync pulse (FSR). Proper setting of the pulse and firmware of the C25 clocks two channels of PCM into the C25. Once the receive register is loaded, an interrupt occurs and the data is processed by the C25.

The C25 is the RXF instruction and SX shown below.
By toggling the XF output pin with the F command,
The 68000 processor can be interrupted.
A signal rising edge on the XF line triggers an interrupt to the 68000.

The following C25 software shows how to achieve this behavior.

* Instruction for interrupting 68000. RXF; XF = 0 SXF; XF = 1-generates a rising edge. DONE

The DSP card can support 24 channels of voice and signal tones by connecting to a single NLI. The NLI maps into the 68000 memory as an I / O peripheral with 32 registers. The NLI communicates with the 68000 via interrupt level 5. The NLI is used to transfer data from the network link to the card.
The internal FIFO of is read by the 68000. Upon receiving an interrupt from the NLI, the 680
00 reads the data from the 16-level FIFO. As a result, the interrupt request to the 68000 is cleared. When the incoming data from the FIFO is empty, the processor writes the data read from the FIFO and transmits it over the network link.

The DSP kernel connects to both the receive and transmit serial bit streams of the NLI. The clock information in turn selects each DSP kernel so that each DSP kernel receives 2 out of every 6 channels. Therefore, this function is
Not programmable on some processors. The following table shows the channels assigned to each C25 within one frame.

[0101]

Table 2 Used channels C25A 0,1,6,7,12,13,18,19 C25B 2,3,8,9,14,15,20,21 C25C 4,5,10,11,16,17 , 22, 23

The receive framing line (8 KHz signal) from the NLI informs the DSP kernel when a new frame begins. Another line from the NLI connects to the DSP kernel to send frames,
Interrupt levels 0-2 on the DSP processor indicating the transmit superframe and the receive superframe.
Is specified. These interrupt levels are utilized after the initial software release.

The present invention is not limited to the particular details of the device described above, and other variations and applications are also contemplated. It is possible that changes may be made to the apparatus described above without departing from the true spirit and scope of the claims contained herein. It is, therefore, asserted that the subject matter described above should be construed as illustrative and not in a limiting sense.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of the present invention under the environment of a telecommunication system.

FIG. 2 is a more detailed block diagram of the present invention.

FIG. 3 is a more detailed block diagram of the control portion of the present invention.

FIG. 4 is a block diagram schematically showing an interface in the present invention.

[Explanation of symbols]

 10 DSP Card 12 68000 Microprocessor 14, 16, 18 DSP Kernel 20 Central Controller 22 Serial Control Link and PCM Bus 24 NLI 26 Control Link 30 68000 Microprocessor 32 RAM 34 ROM 36 C25 38 RAM Bank 40 I / O Port 42, 44 Data register

Claims (7)

[Claims] 1. A digital signal processing system for interfacing with a central control means having at least one control port, the processing control means having an interface port connected to the control port of the central control means, Also, at least the first port, the second port, and the third port
And a first port, a second port and a third port respectively connected to the first port, the second port and the third port of the process control unit. At least first kernel means, second kernel means, and third kernel means each having a port for performing software application tasks, each kernel means being connected to a bus means having a plurality of channels. A first kernel means having a plurality of channel ports, a second kernel means, and a third kernel means, wherein the processing control means is responsive to data received from the central control means. Establishing one of a plurality of software application tasks within each of the kernel means. Management system. 2. A digital signal processing system according to claim 1, wherein said bus means has at least 24 channels, and each of said kernel means receives a channel on which each kernel means differs from other said kernel means. Thus, the digital signal processing system is characterized in that it communicates with 8 of the 24 channels. 3. A digital signal processing system according to claim 2, wherein said 24 channels are pulse code modulated and designated by 0 to 23, and said first kernel means are channels 0, 1, 6, 7 , 12, 13, 1
8, 19 and said second kernel means communicates with channels 2, 3, 8, 9, 14, 15, 20, 21;
The third kernel means are channels 22, 23, 4,
A digital signal processing system characterized by communicating with 5, 10, 11, 16, and 17. 4. The digital signal processing system according to claim 1, wherein each of the kernel means includes a processing means. 5. A digital signal processing system interfacing with a central control means having at least one control port, the processing control means having an interface port connected to the control port of the central control means, Also, at least the first port, the second port, and the third port
And a first port, a second port and a third port respectively connected to the first port, the second port and the third port of the process control unit. At least first kernel means, second kernel means and third kernel means each having a port for executing a software application task, each kernel means being connected to a bus means having a plurality of channels A first kernel means having a plurality of channel ports, a second kernel means, and a third kernel means, wherein the processing control means is responsive to data received from the central control means. Accomplishing one of a plurality of software application tasks within each of the kernel means, said bus means having at least 24 channels However, each of the kernel means communicates with eight of the twenty-four channels so that each kernel means receives a different channel than the other kernel means. 6. The digital signal processing system according to claim 5, wherein the software application task includes at least one of DTMF detection, MF detection and measurement, and each of the kernel means includes the processing. A digital signal processing system, wherein any one of the application tasks is individually designated by the control means. 7. A digital signal processing system for interfacing with a central control means having at least one control port, the processing control means having an interface port connected to the control port of the central control means, the processing control means comprising: Further, the processing control means having at least a first port, a second port, and a third port, and the processing control means are respectively connected to the first port, the second port, and the third port. Respectively having a first port, a second port and a third port,
At least a first kernel means, a second kernel means and a third kernel means for executing a software application task, each of said kernel means being a plurality of channels connected to a bus means having a plurality of channels A first kernel means having a port, a second kernel means, and a third kernel means, wherein the processing control means is responsive to data received from the central control means within each of the kernel means. One of a plurality of software application tasks is achieved by the DTMF
Including at least one of detection, MF detection and measurement, the bus means having at least 24 channels, each kernel means such that each kernel means receives a different channel than the other kernel means. 8 of the 24 channels are communicated, the 24 channels being pulse code modulated and 0 to 2
3, the first kernel means communicates with channels 0,1,6,7,12,13,18,19 and the second kernel means communicates with channels 2,3,8,
9, 14, 15, 20, 21 and the third kernel means are channels 22, 23, 4, 5, 10, 1.
1, 16 and 17, each of the kernel means is
A channel port for each kernel means connected to the bus means by a multiplex / demultiplex means for communicating with the channel assigned to each kernel means of each of the four channels; In each of the kernel means, any one of the application tasks is individually designated by the processing control means, and a digital signal processing system.