JPH07117568B2 - Circuit element characteristic measuring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a transistor and a field effect transistor (FF).
The present invention relates to a circuit element characteristic measuring device for measuring circuit element characteristics such as T).

[Prior art]

Conventionally, in order to measure a parameter of a semiconductor sample such as a transistor or a field effect transistor, a function of supplying a desired DC voltage to the sample and measuring a DC current supplied to the sample or a desired DC current to the sample An apparatus (hereinafter referred to as SMU) having a function of supplying and measuring a supply voltage to the sample is used (Japanese Patent Laid-Open No. 58-148506).
reference). When measuring the characteristics of a sample using a conventional measuring instrument that incorporates multiple SMUs that are independent of each other, under the condition that each SMU can be set and measured independently of each other, identification and measurement can be performed in one step. It was extremely effective to complete.

However, transistor DC current gain h _FE and FET
The above condition may not be satisfied, such as when the threshold voltage V _{TH of} is measured. For example, in the case of V _TH measurement, change the output voltage of the SMU connected to the gate terminal by changing the output voltage of the SMU connected to the gate terminal so that the output voltage and output current of the SMU connected to the drain terminal of the FET become the specified values at the same time. Need to measure.

Conventionally, in order to deal with the above need, first, a certain voltage is applied to the gate terminal from the first SMU, and the current flowing from the second SMU to the drain terminal is measured. Then, the measured value and the reference current value are compared, and if the comparison result is not satisfactory, the voltage applied to the gate terminal is changed again, and the above process is repeated.

Therefore, in the above measurement, the comparison calculation process,
Even if the time required for data communication or the like is ignored, there is a drawback in that, in general, 10 steps or more are required for setting and measurement, and the measurement time until the final measurement result is obtained becomes extremely long. Further, as shown in FIG. 4, it is possible to configure a device for measuring the V _TH of the FET by loop-connecting the SMU 401, the adder 402, the integrator 403, and the sample FET 404 having the stray capacitance C _rss . In FIG. 4, the difference signal Δe ₀ between the voltage signal V _M representing the drain current I _D and the reference voltage signal V _MREF.
Is integrated by the integrator 403, and the loop operates so as to be negatively fed back to the gate of the FET 404. Therefore, the loop converges so that V _M = V _MREF. Therefore, if the signal V _MREF is set to a value equal to the signal V _M when the drain current I _D reaches the predetermined value, the predetermined drain current value V _TH can be measured at. However, to ensure the stability of negative feedback, FET4
It is necessary to make the integration constant k of the integrator 403 large enough so that the loop gain becomes 1 or less at the frequency where the phase delay such as the response delay of 04 and the conversion delay of the output current of SMU401 to the output voltage does not exceed 90 degrees. is there. Therefore, it takes a very long time for the drain current I _D to reach a predetermined value, resulting in a very long measurement time.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit element forcing measurement device with a shortened signal setting time.

[Outline of Invention]

The invention relates to a first control means for outputting a first control signal for controlling the output signals of a plurality of signal sources, and the first control signal in relation to a first signal representing the output signal of the signal source. Which relates to a circuit element characteristic measuring device comprising:
The second control means introduces a reference signal means for outputting a reference signal, an amplifying means for outputting a signal related to a difference between the reference signal and the first signal, and an output signal for the amplifying means. Comparing means for controlling the output signal of the first or second variable integration means to be output as the second control signal in relation to the output signals of the variable integration means, the second variable integration means, and the amplification means. It is characterized by consisting of and. As a result, the signal supplied to the sample can be set in a short time.

〔Example〕

 FIG. 3 is a block diagram showing an embodiment of the present invention.

In FIG. 3, the control circuit 105 controls the internal switching operation of the selection circuits 101 and 103 via the bus 115, and the comparison control circuit 102.
Control, A / D conversion operation of the analog-to-digital converter (ADC) 104, control of settings of the SMUs 110 to 113, open / close control of the switches 106 to 109, and the like.

The selection circuit 101 selectively switches the voltage signals V _{1 to} V ₄ representing the output voltages of the SMUs 110 to 113 and the voltage signals V _{M1 to} V _M4 representing the output current, and inputs them to the comparison control circuit 102 as a signal V _in . The comparison control circuit 102 includes an integrator, as described later.
It has a variable DC power supply, an error amplifier, a comparator, a switch, etc., and outputs the signal V _out from the integrator. The variable DC power supply is also used as the reference signal source, as described below, during the search operation of the comparison control circuit 102, the reference signal voltage and the signal V _in is compared. When the comparison result satisfies the predetermined condition, the signal related to the signal V _in is selected by the SMU11.
Returned to 0-113. SMU110 to 112 are FET11 samples
Control circuit 1 for each of the drain D, gate G, and source S terminals of 4
A signal related to the signal from 05 and the signal V _out from the comparison control circuit 102 and the control signal from the control circuit 105 is supplied. In the case of FIG. 3, since the SMU 113 is not connected to the FET 114, it has nothing to do with the measurement.

The selection circuit 103 uses signals V _{1 to} V ₄ , V _{M1 to} V from the SMUs 110 to 113.
_M4 is selected and input to the ADC 104 as the signal V _{A / D.} ADC
Reference numeral 104 converts the signal V _{A / D} into a digital signal and inputs it to a display (not shown). The display value on the display is the value to be obtained.

FIG. 2 is a timing diagram of the circuit element characteristic measuring device of FIG.

The details will be described below with reference to FIGS. 2 and 3.

An example of measuring the threshold voltage V _TH under the condition that the drain-source voltage of the FET 114 is 10 V and the drain current is 1 nA will be described. However, at this time, it is assumed that the expected value voltage range of V _TH is −10V to 0V.

As an initial state, the following settings are made at time t ₀ .
The selection circuit 101 selects the voltage signal V _M1 proportional to the output current of the SMU 110, that is, the drain current, and sets the voltage signal V _M1 to be input to the comparison control circuit 102 as the signal V _in .

In the selection circuit 103, the voltage proportional to the gate voltage of the FET 114 is V
₂ is selected and set to be input to the ADC 104 as the signal V _{A / D.}

The switches 106 and 108 are set to the off state, and the switch 107 is set to the on state.

SMU110 output voltage 10V, output current 2nA, SMU111 output voltage −
10V, output current 1μA, SMU112 output voltage 0V, output current 1mA. The comparison control circuit 102 has an output voltage range of 0 to 10V,
Comparison reference voltage 5V (When drain current is 1nA, signal V _M1
5V), the search speed is 10V / msec., And the integration constant of the integrator is 10msec.

At time t ₁ , the comparison control circuit 102 enters the search mode, starts the search operation, and outputs the ramp signal generated by the variable DC source and the integrator therein as the signal V _out . The signal V _out gradually increases from 0V at this search speed. The output signal V _{02 of the} SMU111 is -10V in response to the signal V _out.
Gradually rises from.

At time t ₂ , the comparison control circuit 102 outputs the signal V _{M1, that} is, the signal V _M1.
When it detects that in has reached 5 V (that is, the drain current is 1 nA), the supply from the internal variable DC source is stopped, the search operation is terminated, and the analog feedback mode is entered. As a result, the comparison control circuit 102 integrates the error signal between the signal V _in and the reference voltage (5 V) and outputs the signal V _out as the SMU111.
Will be supplied to. As a result, the signal V _M1 stabilizes at 5 V (drain current is 1 nA). The signal V _{2 at} this time is FET 11
Corresponds to a threshold voltage V _{TH of} 4. At time t ₃ , ADC 104 A / D converts signal V ₂ corresponding to threshold voltage V _TH and displays the value on a display device (not shown). At this time, signal V _M2
If converted and displayed, the gate current value can be obtained. Time t ₄
In, the control circuit 105 resets the comparison control circuit 102,
The measurement is complete.

FIG. 1 is a detailed block diagram of the comparison control circuit 102.
In FIG. 1, the same parts as those in FIG. 3 are designated by the same reference numerals.

The error amplifier 302 outputs an error signal related to the difference between the output signal of the signal V _in a D / A converter (DAC) 301. The error signal is input to the variable resistor 304 and the comparator 305.
The variable resistor 304 is composed of a commonly used variable resistor or multiplying DAC. The setting of the value of the variable resistor 304 and the switching of its input signal polarity is performed by the control circuit 105 via the bus 115. The comparator 305 is an error amplifier 30.
It is set only when the output signal of 2 crosses the zero potential for the first time, and controls the opening and closing of the switches 309 and 310. The control circuit 105 sets via the bus 115 whether to detect when the output signal of the error amplifier 305 crosses the zero potential from the direction of positive to negative or from negative to positive.

The control of the output signal of the variable DC power supply 303 is performed by the control circuit 105 via the bus 115 and input to the amplifier 306 via the switch 309. The output signal of the variable resistor 304 is input to the amplifier 306 via the switch 310. The amplifier 306, the capacitor 307, the variable DC power source 303, and the variable resistor 304 form an integrator. The output signal of the integrator is output as the signal V _out .

Hereinafter, the operation of the comparison control circuit 102 will be described in detail with reference to FIGS. However, other setting conditions and the like are as described above.

In the initial state at time t ₀ , the switches 308 and 309 are on and the switch 310 is off.

At time t ₁ , the switch 308 is turned off and the comparison control circuit 102 enters the search mode. In this state,
The variable DC power supply 303 outputs a predetermined current determined by the search speed to the amplifier 306. Since the search speed is independent of stability, it can be extremely fast. The current is integrated by the amplifier 306 and the capacitor 307 and output as the signal V _out . On the other hand, the error amplifier 302 outputs an error signal proportional to the difference between the signal V _in and the reference output signal of the DAC 301 (5 V in the present embodiment of zero). As the signal V _out increases, the signal V _M1 or the signal V _in
Rises. When the signal V _in becomes equal to the reference output signal of the DAC 301, that is, at time t ₂ , the comparator 305 detects this and turns the switch 309 off and the switch 310 on. As a result, the comparison control circuit 102 is
Enter feedback mode. In this mode, the output signal of the error amplifier 302 is integrated with a predetermined integration constant by the integrator composed of the variable resistor 304, the amplifier 306, and the capacitor 307, and output as the signal V _out . Therefore, switch 30
Even if an error occurs due to the delay of the switching operation of 9,310, the signal V _{in, that} is, the signal V _M1 is stabilized at a predetermined value (5 V) as described above. As a result, as described with reference to FIG.
A predetermined drain current will flow through 14. Then, as described above, A / D conversion is performed at time t ₃ and time t ₄
At, the switches 308 and 309 are turned on, and the switch 310 is returned to the initial state of off.

In this embodiment, the signal V _out is output in any value, in order to protect the samples, when the signal V _out reaches a predetermined value, it is possible to cut off or suppressing the signal V _out. Further, if the gain of the error amplifier 302 is increased, the variable resistor 304 does not need to be composed of an expensive high-performance element, and the error due to it can be absorbed.

〔The invention's effect〕

According to the present invention, the measurement can be executed in an extremely short time. Even if the stability of the system is sufficiently secured, the measurement can be performed in a short time. Furthermore, even if the expected value voltage range of V _TH is large, it can be quickly set to a predetermined value.

[Brief description of drawings]

FIG. 1 is a block diagram of a comparison control circuit used in the circuit element characteristic device of the present invention. FIG. 2 is a block diagram of the comparison control circuit of FIG. FIG. 3 is a block diagram of the circuit element characteristic measuring device of the present invention. FIG. 4 is a block diagram of a conventional circuit element characteristic measuring device. 101, 103: Selection circuit, 102: Comparison control circuit, 104: ADC, 105: Control circuit, 110 to 113: SMU, 301: DAC, 302: Error amplifier, 303: Variable DC power supply, 304: Variable resistor, 305: Comparison vessel.

Claims (1)

[Claims] 1. A plurality of signal sources (SMU) for supplying an output signal to a sample and a signal representing the output signal, and a setting signal for setting the output signals of the plurality of signal sources. Control means, selecting means for selectively deriving and outputting one of the signals representing the output signal, and outputting a signal V _out related to the signal representing the output signal from the selecting means and a reference signal A comparison control means; and a connection means for connecting the predetermined signal source and the comparison control means for changing the output signal of the predetermined signal source according to the signal V _out. In the circuit element characteristic measuring device, the comparison control means determines the difference between the reference signal source means for outputting the reference signal, the search signal source means for outputting the search signal, and the signal representing the reference signal and the output signal. Relation Integrating means for integrating the signal to
The circuit element characteristic measuring device comprising: a comparing means for selectively switching the signal V _out from the output of the search signal source means to the output of the integrating means in relation to the difference.