JPH07114516A - Program parallelizing method - Google Patents

Abstract

PURPOSE:To reduce the inter-processor communication of a program for parallel computers in a process for converting a program, described in a high-level language, into the program for the parallel computers. CONSTITUTION:The variables of the inputted program are divided and assigned to plural processors. The inputted program 2 is analyzed, the presence of reference to a variable value defined by other processors is detected as to each process, and codes of a program part regarding the inter-processor communication for the reference are generated. When each processor executes the parallelized program 5, the codes of a program part for deciding whether or not reference to the variable value is already performed are generated by an analysis. A program part which performs control so as to perform the inter- processor communication for executing the reference to the variable value when the reference is not performed, or not to perform the reference when the reference is already done, is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for automatically converting a program for a single processor written in a high-level language into a program for a distributed memory type parallel processor, and more particularly,
The present invention relates to a technique for automatically generating, by a computer, a program part for performing communication between processors necessary for a program for a parallel processor.

[0002]

2. Description of the Related Art In order to parallelize a program, that is, from a program for a single processor written in a high level language such as FORTRAN to a program for a distributed memory type parallel processor (hereinafter referred to as "parallelized program").
Call)), it is necessary to add a program part for communication. This is because, in a distributed memory parallel processor system composed of multiple processors, for example, variables are distributed and assigned to each processor, so when one processor refers to a variable defined in another processor, This is because it is necessary to obtain the variable value to be referred to by interprocessor communication.

Therefore, when a program written in a high-level language such as FORTRAN is input and automatically converted into a parallelized program by the computer, the computer changes the code of the program portion for communicating data between processors. It is automatically generated and given to a parallelized program. Further, it is desirable that the generated parallelized programs have substantially the same description when comparing the program parts for each processor.

As described above, regarding the technique for automatically generating a parallelized program including a code for communicating data between processors from a program written in a high-level language,
For example, `` Proceedings of the 1992 ACM International
Conference on Supercomputing ".
In this system, a computer analyzes a program written in a high-level language, detects which data should be communicated at which timing, and automatically inserts a communication code into a parallelized program.

A technique for inputting a program in which a physical phenomenon is described in a high-level problem description language into a computer and converting it into a parallelized program for a parallel processor in which interprocessor communication is described is described in JP-A-4, for example. ―190422.

[0006]

In the above-mentioned prior art,
When generating a parallelized program, the computer generates and adds a communication code in consideration of only the static situation that each processor can understand without actually executing the generated parallelized program. However, when the parallelized program is actually operated, there are various dynamic changes in the situation. Therefore, the necessity of interprocessor communication at a certain position may be determined only when the parallelized program is executed.
Therefore, according to the conventional technique, there is a possibility that unnecessary and unnecessary communication is performed.

In order to improve the execution performance of the generated parallelized program, it is desirable to minimize communication between processors, that is, to prevent useless communication between processors. In the above-mentioned conventional technology, the necessity of communication is determined only when the parallelized program is executed (for example, there is a conditional statement in the original program, and the necessity of communication between processors is determined according to the condition). No mention is made of how to prevent unnecessary communication.

An object of the present invention is to provide a parallelized program that prevents unnecessary interprocessor communication when each processor executes the parallelized program even when the necessity of interprocessor communication is determined only at the time of execution. It is to provide a method capable of automatically converting and generating from a program for a single processor.

[0009]

In order to achieve the above object, the present invention provides a method for inputting a program for a single processor and converting the input program into a parallelized program for a parallel processor by a computer. There
By analyzing the input program, the inter-processor communication that may be necessary when the converted parallelized program is executed by the processor is detected for each processor, and the code for the communication is detected. By analyzing the input step and the first step of generating, for each processor, when the parallelized program is executed by the processor, the necessity of communication with other processors is determined. Second step of generating a code for controlling so that communication is performed only when it is determined that communication is necessary, and a code for the communication and the control for the control in the input program. And a third step of generating a parallelized program added with the code.

It should be noted that the code for the control in the third step is not generated in the program portion determined by the computer that it is always necessary to perform the inter-processor communication, and the inter-processor communication is performed unconditionally. It is good to do so.

Further, a flag for managing whether or not the reference to the variable value has already been executed by the processor is newly provided, a code for updating the value of the flag, and a processor according to the value of the flag. Code for controlling execution of intercommunication may be generated.

For example, the first step includes a control flow analysis step of creating a control flow graph from the input program, which represents a flow of execution of the input program in a directed graph.
From the control flow graph, a data dependence analysis step of creating a data dependence graph expressing the definition / reference relation of variables in the input program in a directed graph, and the definition / reference of each data in the data dependence graph The communication data extraction processing step of creating a communication target data dependence graph and the communication target data dependence graph, and determining the communication point in the program from the communication target data dependence graph. A communication position determination processing step of generating / inserting a code for communication to be inserted at a position to create a communication information list may be provided.

The second step includes a variable definition flag generation processing step for generating a code for setting a predetermined flag in the communication information list in which communication target data of the communication code is defined, and the flag. And a communication conditional expression generation processing step for generating a code of the communication conditional expression for controlling the communication code to be executed only when is set.

Further, a variable definition flag initialization information generation processing step for generating a code for resetting the flag after execution of the communication or a flag referred to in the communication conditional expression is traced backward in the control flow graph. An expression defining the flag may be examined, and if the communication conditional expression is always satisfied, a communication condition reduction processing step of deleting the communication conditional expression and the flag may be provided.

[0015]

According to the program conversion method of the present invention, even when the necessity of inter-processor communication is determined only at the time of execution, the necessity of the inter-processor communication is judged at the time of execution to selectively perform communication. As a result, a computer can automatically generate a parallelized program that prevents unnecessary communication.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration and a schematic process of an embodiment of a computer system for realizing a program parallelizing method according to the present invention. FIG. 2 is a chart showing a detailed procedure of the communication code generation processing 4 shown in FIG. These procedures will be described later in detail.

As shown in FIG. 1, the computer 1 inputs a program 2 for the original single processor and divides the inputted program 2 into a plurality of processors 3
And the program parallelization processing of this embodiment including the processing 4 for generating the communication code is executed for each processor, and the generated parallelization program 5 is output. The program division processing 3 includes a data division processing 31 for dividing data into the processors and a division processing 32 for dividing the processing into the processors. The computer 1 stores in each file the data division information 6, the parallelization program 7 without communication code, and the parallel execution control information 8 generated in the process of processing.

FIG. 3 shows an example of a program for a single processor. FIG. 4 shows an example of a program when the program for a single processor shown in FIG. 3 is parallelized by a conventional program parallelization method. 5 is an example of a program in which the program for the single processor shown in FIG. 3 is parallelized by the program parallelization method of the present invention. FIGS. 10, 12 and 14 show data in the intermediate stage of the communication code generation process 4 in the process of parallelizing the program for the single processor shown in FIG. 3 according to the embodiment of the present invention.

First, the original program 200 for a single processor shown in FIG. 3 is taken as an example, and a program 501 (FIG. 5) parallelized by the present embodiment and a program 500 (FIG. 4) parallelized by the conventional method. ) And will be explained while comparing.

In the original program 200 of FIG. 3, (10), (11), (20), etc. attached to the right side indicate sentence numbers. In the original program 200, the array B is first arrayed in the range from 1 to 100.
The values of each element in (I) are all initialized to 0.0 (sentences 10 and 11). Next, the processing from sentence 21 to sentence 29 is repeated the number of times set in the variable TIME (statements 20 and 30).

In the statements 21 to 24, when the value of the array element B (1) exceeds 1.0, the array index I is 1 to 1.
The value of each element of the array A (I) is updated for the range of 00. Then, in sentences 25-29, the array index I
For the range from 1 to 99, the process of updating the array C (I) (sentence 26) and then updating the value of the array element B (I) (sentence 27) is repeated. Next, in statement 29, the variable N
1 is added to T.

The program parallelization process is a process for generating a program to be executed in parallel by a plurality of processors from such a program for a single processor. For example, since the original program 200 shown in FIG. 3 uses the arrays A, B, and C, these arrays are appropriately divided into a plurality of ranges, and the calculation of each range is assigned to each processor. That is, in each of the update processing of the arrays A, B, and C (statements 11, 23, 26, and 27), each processor has an array index in the range from $ lb to $ ub (where $ lb and $ ub are By assigning the processing of updating a variable for which a different value is set for each processor), a parallelized program is generated in which a plurality of processors execute the processing in parallel.

First, a program generated by the conventional program parallelization processing will be described. Figure 4
3 shows a parallelized program 500 generated by subjecting the original program of FIG. The program 500 is a program executed by each of a plurality of processors. However, as described above, the values of the variables $ lb and $ ub are different for each processor.

In the original program 200 shown in FIG. 3, statements 11, 23, 26, 2 for updating the arrays A, B, C.
The processing of 7 is divided, and each processor will share the processing. For this purpose, the parallelized program 500 shown in FIG.
Then, the DO sentence 10, 22, 25 of the original program 200
Change the loop range of each statement 10-a, 22-
a, 25-a.

In the execution of the conditional statement 21 in the program 500 shown in FIG. 4, all processors are array element B.
Reference the value of (1). Therefore, the program parallelization process generates a communication code (statements 201, 202) for transferring the value of the array element B (1) from the processor owning the array element B (1) to all the other processors. . In executing the statement 27, each processor refers to the value of the array element A ($ ub + 1) that it does not own.
Therefore, the program parallelization process generates communication codes (statements 242 and 243) that transfer this value.

Here, in the program 500 of FIG. 4, whether or not to execute the statement 23 for updating the value of the array A is determined according to the evaluation result of the conditional statement 21. Conditional statement 21
If the statement 23 is not executed according to the evaluation result of, the value of the array A has not been updated. Therefore, the value of A (I + 1) referred to in the statement 27 remains the value referred to in the execution of the statement 27 before that in the repetition of the DO statement 20. 243)
Is essentially unnecessary.

However, in the conventional parallelization processing, the necessity cannot be determined at the time of program parallelization. Therefore, in the conventional method, as shown in FIG. 4, a program for a parallel computer that performs communication regardless of the necessity is generated.

Next, a program generated by the program parallelization processing according to the method of this embodiment will be described. FIG. 5 shows a parallelization program 501 generated by performing the program parallelization processing (FIGS. 1 and 2) according to this embodiment using the original program 200 of FIG.

In the program 501 of FIG. 5, statement 22-a
And whether a block consisting of statement 23 has been executed,
It is managed by the value of the flag A_update_flag. That is, when the block including the statement 22-a and the statement 23 is executed, the flag A_up is set in the statement 240.
Update the value of date_flag to 1. And sentence 2
If the flag A_update_flag is 1 before executing the block from 5-a to the statement 28, inter-processor communication (statements 242 and 243) is executed and the flag A_
When update_flag is 0, conditional statements 241 and 245 for controlling not to execute inter-processor communication (statements 242 and 243) are inserted. This allows
The program 501 parallelized according to the present embodiment does not perform unnecessary inter-processor communication.

Originally, in the program 501 of FIG. 5, whether a certain processor needs to use the array A after performing inter-processor communication in the block composed of the statements 26 and 27 (basic block 4 in FIG. 10). Whether or not that processor has to execute the block of the statement 23 (basic block 3 in FIG. 10) must be determined by another processor that owns the array value to be referenced. However, the program parallelization method according to the present invention is realized based on the fact that the processors that execute in parallel execute the basic blocks in the parallelized programs in the same order. Therefore, whether or not another processor has executed the basic block 3 can be known by substituting whether or not its own processor has executed the basic block 3. Whether or not the basic block 3 is executed by itself can be determined by the value of the flag variable by inserting an executable statement that sets the flag variable at the end of the basic block 3. As a result, as described above, it is possible to determine the necessity of inter-processor communication when executing the parallelized program.

Next, the processing procedure of this embodiment for automatically generating a parallelized program that does not perform such wasteful communication will be described in detail.

The processing procedure of the program parallelization processing of this embodiment will be described with reference to FIG. The computer 1 first inputs the program 2 and performs the program division processing 3. This is the determination of the data division process 31 and the process division 32, that is, the process of the input program 2 and the process of deciding how to divide the data and allocate it to a plurality of processors. The data division 31 creates a table showing how each array in the program is divided and assigned to the processor, as shown in FIG. Division of processing 32
Determines how to divide each executable statement in the program and which processor executes it. For example, as shown in FIG.
A common parallelized source program that generates parallel execution control information 8 indicating how the processors share and execute each DO loop, and further executes each processor by referring to the parallel execution control information 8 7 (FIG. 9) and store each in a file. Any method may be used to determine the processing and how to divide the data. Then, the communication code generation processing 4 is executed to generate the parallelized program 5.

FIG. 8 shows the configuration of a parallel processor that executes the generated parallelized program 5. The parallel processor has the following functions.

(1) It has a plurality of processors 40a to 40d and a network 42 which enables data transfer between the processors.

(2) The processors 40a-40d each have a memory 41a for holding data and programs.
~ 41d.

(3) Each processor has a function of transmitting and receiving data to and from other processors via the communication network 42. Transmission and reception of data is executed by the following two system calls.

(3.1) The data transmission process is executed by the send system call. The send system call is executed with the variable to be transmitted, the processor number of the transmission destination and the data identifier as arguments.

(3.2) The data receiving process is executed by the receive system call. The receive system call is executed with the variables for substituting the received data and the data identifier as arguments. If the data corresponding to the identifier has not arrived when the receive system call is executed,
The processor pauses and waits for the execution of other processing until the data arrives.

Next, the communication code generation processing 4 will be described in detail with reference to the chart of FIG. Here, a case where a communication code is added based on the parallelized program (without communication code) 7 shown in FIG. 9 will be described. However, as shown by the dashed arrow in FIG. 1, the original program 2 shown in FIG.
After performing the division processing 3 of 00, the communication code generation processing may be directly performed.

In FIG. 2, in the communication code generation processing 4, first, the control flow analysis 401 of the program is performed, and the control flow graph 411 that represents the flow of program execution in a directed graph is created. 10 is a conceptual diagram of the control flow graph 411 obtained by performing the control flow analysis 401 on the parallelized source program 7 of FIG. 9, and FIG. 11 shows the data structure of the control flow graph 411. Shown respectively. In FIG. 10, 4100-4
Reference numeral 103 denotes a basic block made up of a series of assignment statements and expressions that are executed sequentially. Arrows 4110-4116
Indicates a branch representing the flow of control between the basic blocks.

Next, the computer 1 performs the data dependence analysis 402 shown in FIG. 2, and the data dependence graph 412 expressing the relationship between the definition and reference of variables in the program by a directed graph.
To create. FIG. 12 shows the original program 20 shown in FIG.
A conceptual diagram of the data dependence graph 412 for 0,
FIG. 13 shows the data structure of the data dependence graph 412. Arrows 4120 to 4124 are data definition /
Indicates the reference relationship. The starting point of each arrow shows where the data is defined, and the ending point shows where the data is referenced. That is, from the table 412 of FIG. 13 obtained by the data dependence analysis shown in FIG. 12, for each array, all the blocks that define the array and the blocks that reference the array can be known. Specifically, in FIG. 13, for example, it can be seen that the array A is defined by the block 4102 (basic block 3) and is referenced at two locations of the block 4103 (basic block 4).

Next, the communication data extraction processing 4 in FIG.
Do 03. This is because each arrow appearing in the data dependency graph 412, that is, the relation of definition / reference of each data in the data dependency graph, has a possibility of communicating between the processors, and the communication target data dependency graph 413 is selected. Is a process for creating. The communication target data dependence graph 413 is a partial graph of the data dependence graph 412.

FIG. 14 shows the data dependence graph 41 of FIG.
2 shows a conceptual diagram of the communication target data dependence graph 413 created from FIG. 2, and FIG. 15 shows the data structure of the communication target data dependence graph 413. Data dependence graph 4 of FIG.
As for arrows 4121 and 4123 in 12, it can be seen that the processor that defines the data is the same as the processor that refers to it. Therefore, these arrows 412
No. 1,4123 is eliminated because inter-processor communication is not required. On the other hand, arrows 4120, 4122 and 4124 in FIG. 12 are taken out as those requiring inter-processor communication. As a result, the communication target data dependence graph 413 shown in FIG. 14 is obtained.

Next, the communication position determination processing 40 in FIG.
Do 4. By this processing, communication data extraction processing 403
Regarding the data dependence that may be used for inter-processor communication, the location of inter-processor communication in the parallelized program is determined, and the required communication code (communication information) for inter-processor communication is located at that location. Insert. In this embodiment, the insertion position is determined so that communication is performed immediately before the basic block that refers to the data to be communicated between processors.

FIG. 16 shows the communication information list 414 obtained from the communication object data dependence graph 413 of FIG.
7 shows the data structure of the communication information list 414. Reference numeral 4141 indicates the communication target data dependence graph 4 of FIG.
It is the communication information generated based on the data dependencies 4120 and 4124 in 13. The communication information 4141 is arranged immediately before the basic block 4101. This communication information 41
41 sends its value to all the other processors when its own processor owns the array element B (1), and B (1) when its own processor does not own the array element B (1). ) Is received from the processor that owns the value).

The communication information 4142 shown in FIG.
Data dependence 41 in the communication target data dependence graph 413 of
22 is communication information generated based on 22. Communication information 41
42 sends the array element A ($ lb) to the processor immediately before the own processor (the processor ID is one smaller than the own processor), and sends the array element A ($ ub + 1) to the processor immediately after the own processor (processor The ID is one larger than that of its own processor).

Next, the computer 1 performs the communication condition determination processing 405 shown in FIG. This is the respective communication information (4141 and 4 in FIG. 16) inserted in the communication position determination processing 404 in FIG.
142) for data 142) (FIG. 12)
And a control flow graph 411 (FIG. 10) are used to determine the conditions under which communication is actually required, and control information for controlling the execution of communication is created. The condition that requires communication is the condition that the data dependence of the arrow appearing in the communication target data dependence graph 413 (FIG. 14) actually occurs during execution, and this is achieved by tracing the control flow graph 411 (FIG. 10). You can ask.

FIG. 18 shows the communication condition determining process 4 shown in FIG.
The detailed chart of 05 is shown. 19 shows information 4055 at an intermediate stage of the communication condition determination processing 405 of FIG.
Hereinafter, the chart shown in FIG. 18 and the information 4 of FIG.
The processing of the communication condition determination processing 405 will be described with reference to 055.

The communication condition determination processing 405 performs the following processing for each piece of communication information in the communication information list 414 as shown in FIG.

In FIG. 18, first, the variable definition flag generation processing 4051 creates code information for setting a flag variable indicating whether or not a variable value to be communicated is defined during program execution. Next, the communication conditional expression generation process 40
52 creates a conditional expression for determining the necessity of the communication at the time of execution.

Further, the variable definition flag initialization code generation processing 4053 creates code information for initializing the variable definition flag when communication is performed. Further, the communication condition reduction processing 4054 removes the trivial condition from the conditional expression created in the communication condition expression generation processing 4052 by referring to the control flow graph 411 to reduce the condition.

More specifically, regarding the communication information 4141 of the communication information list 414 of FIG. 16, since this communication originates from the data dependency 4120 and 4124 (FIG. 14), the basic block 4100 or 4103.
It is understood that the definition of the communication target data B (1) occurs when the data passes through. Therefore, the variable definition flag generation processing 405
1 provides a flag B_update_flag, and sets the value to 1 when passing through the basic block 4100 or 4103. Code information 4154, 4157 (FIG. 1).
9)).

Next, the inter-processor communication is flagged as B_up.
Since it is necessary to execute it only when the date_flag is 1, the communication conditional expression generation processing 4052 in FIG. 18 creates the conditional expression 4155. Next, the variable definition flag initialization information generation processing 4053 creates code information 4156 that initializes the value of the flag B_update_flag to 0 after the communication is executed.

Further, the communication condition reduction processing 4054 is
Regarding the flag B_update_flag that is referred to in the conditional expression, the control flow graph 411 (FIG. 10) is traced backward to check the expression that defines the value. In this example, when the paths 4110 and 4114 of the control flow graph 411 are traced in reverse, it can be seen that the flag B_update_flag is 1 in both cases. This means that in the data structure of the control flow graph 411 shown in FIG.
It can be seen from the fact that the preceding blocks of are only 1 and 4.
Therefore, since it is determined that the conditional expression 4155 is always satisfied, it can be determined that the conditional expression is unnecessary. Therefore, the conditional expression 4155 and the variable definition flag B used for this
Delete _update_flag.

Similarly, the communication information 4142 of FIG. 16 is provided with a flag A_update_flag, and information 4151 (FIG. 19) of a code for setting this value to 1 when the basic block 4102 is passed. Also, the conditional expression 4152 and the flag A_update_fla
Code information 4153 for initializing g is created.

Next, the control flow graph 411 (FIG. 10)
The reverse is followed and the expression which defines the value of the flag A_update_flag is examined. In this case, routes 4112 and 4113 are examined. If route 4113 is followed in reverse,
It can be seen that the value of the flag A_update_flag is 1. However, when the route 4112 is traced in reverse, the value of the flag A_update_flag cannot be determined. This can be seen from the fact that the preceding blocks of the block 4 in FIG. 11 are 2, 3 and 4, but the definition block of the reference block 4 for the array A in FIG. 15 is only 3. Therefore, the conditional expression 4152 and the like are left as they are.

As described above, the communication information list 414 shown in FIG. 16 to the communication control information list 4 shown in FIG.
15 is generated. The communication control information list 415 of FIG.
Then, by the conditional statement 4152 using the flag A_update_flag, each processor determines whether or not to execute the communication code 4142 when the parallelized program is executed. Therefore, the communication between processors is not performed when unnecessary, so that the number of times of communication and the load are reduced. Such a conditional statement is not added to all communication codes, and communication codes that are always judged to be necessary like the communication code 4141 (without adding a conditional statement) unconditionally perform inter-processor communication. Is designed to do. Therefore, the conditional statement is not unnecessarily executed.
FIG. 21 shows the data structure of the communication control information list 415.

Referring again to FIG. 2, the code generation process 46.
0 outputs the parallelization program for the parallel processor as shown in FIG. 5 based on the division of the processing and the communication information determined so far.

In the embodiment described above, the array is one-dimensional. Therefore, the value of the reference flag may be a binary value indicating whether or not interprocessor communication is performed. However, when the array is two-dimensional or more, the array element adjacent to a certain array element has four or more values, so the reference flag is "1" or "
A binary value of 0 "is not sufficient.

Another embodiment of the present invention which addresses this problem will be described. In the present embodiment, the interprocessor communication code generation processing according to the present invention is applied to a case where one array is referred to a plurality of times and the array element indexes to be referred to are different. In this case, the method of determining the necessity of inter-processor communication for each array cannot sufficiently eliminate the useless communication, and the communication target part is divided for one array and the inter-processor communication necessity is divided for each. It becomes necessary to judge whether or not. The case where the communication code generation processing according to the present embodiment is applied to the parallelized program 310 without communication code shown in FIG. 22 will be described below.

The program 310 updates the array A in block 311, and refers to the updated value in blocks 312 and 313. The block 312 is a conditional block, and is executed only when the determination condition of the conditional statement (statement 324) is satisfied. Sequence A is 2 in program 310
They are referenced in one block, but each array element index they refer to is different. That is, in block 312, A (I-1, J), A (I
+1, J), and in block 313, A (I-1,
J), A (I + 1, J), A (I, J-1), A (I,
J + 1).

Here, such a data reference method of the two-dimensional array will be expressed as a data reference pattern in a graph as shown in FIG. In FIG. 23, for example, STENCIL1
Is A (I-1, J), A (I + 1, J), A (I, J-
1) is a reference pattern indicating that 4 points of A (I, J + 1) are referred to. Similarly, STENCIL2 is A (I-1,
J) and A (I + 1, J) are two reference patterns, and STENCIL3 is a reference pattern that references two points A (I, J-1) and A (I, J + 1). If it is expressed using this reference pattern, in the program 310, the block 31
The reference pattern STENCIL2 is referenced in 2 and the array A is referenced in the reference pattern STENCIL1 in block 313. The data to be communicated between the processors can be determined by this reference pattern.
Such a reference pattern can be expressed as an array whose elements are relative indices of reference points. The functions for transmitting and receiving the necessary data with the array representing the reference pattern and the array name of the communication target as arguments are respectively called sendp and recvp.

In the following, first, the program parallelization method according to the present embodiment will be described using an example of the program 310, and then a method for generating such a parallelized program will be described.

FIG. 24 shows a program obtained by parallelizing the program 310 according to this embodiment. In the program, reference patterns related to array A are STENCIL1 and STENC in FIG.
There are two types of IL2. A portion of the array in which each processor only refers and does not perform update processing is called a reference area. When referring to the data in the reference area, each processor needs to receive the data from the other processor through inter-processor communication. The variable A_status_flag holds a reference pattern number corresponding to a portion of the reference area of the array A that has not been updated to the latest value (hereinafter, this is referred to as Dirty). Immediately after the array A is updated, all the reference areas become Dirty, and the Dirty part corresponds to STENCIL1. In this case, the program sets A_status_flag to 1
To The reference pattern of the array A of the block 312 is STEN
Since it is CIL2, communication between processors corresponding to this is performed (statements 3241 and 3242).

By this interprocessor communication, a part of the reference area of the array A has already been communicated, and only the part corresponding to STENCIL3 becomes dirty. To indicate this, the value of the control variable A_status_flag is set to 3 (statement 3243). The reference pattern of the array A of the block 313 is STENCIL1, but at the start of execution of the block 313, the block 312
Is executed and inter-processor communication using STENCIL2 as a reference pattern has already been executed, and there are two cases. When the block 312 is not executed, interprocessor communication with the reference pattern STENCIL1 is necessary. On the other hand, if block 312 has already been executed, STENCIL1 and ST
Interprocessor communication with the reference pattern STENCIL3 is required as a difference from ENCIL2. This is the control variable A_update_fla
Determine the value of g and execute communication (statements 3291 to 329)
7).

The communication code generation process 4 determines, for each basic block having inter-processor data dependency, data that needs communication when the basic block is executed, and generates a program that communicates only the necessary data. From the control flow analysis 401 to the communication position determination processing 404 of FIG.
The procedure is exactly the same as in the first embodiment.

The communication condition determination processing 405 and the code generation processing 406 shown in FIG. 2 are reference patterns first appearing in the program for each array to be communicated, and reference obtained by taking the sum and intersection of these reference patterns. List all patterns and number reference patterns serially. Here, the sum and difference of the reference patterns mean the sum and difference as a set of reference points. Further, a reference pattern obtained by taking the sum of all the reference patterns is U.
In the example of the program 310, the three reference patterns shown in FIG. 23 are obtained.

Next, for each element of the communication information list, with respect to the reference pattern S indicated by the state management variable and the data reference pattern R in the block, the reference pattern R- (U-
S), an execution statement string for performing inter-processor communication (statement 24 in FIG. 5).
1-242, 291-297) are generated. Next, an execution statement string (statements 243 and 298 in FIG. 5) that sets the state management variable to the number of the reference pattern SR is generated. Here, the subtraction symbol means a difference as a set. As a result, the state management variable always holds the number of the reference pattern corresponding to the part that is not updated in the communication area of the array,
Also, in each communication, it operates so as to communicate only the really necessary part.

As described above, the parallelized program as shown in FIG. 24 is generated.

[0071]

According to the program parallelization method of the present invention, the number of communications during parallel execution can be reduced as compared with the conventional method, and therefore the execution load required for communications can be reduced. As a result, the execution performance of the generated parallel computer program can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration and a schematic process of an embodiment of a computer system that realizes a program parallelization method of the present invention.

FIG. 2 is a chart showing an example of communication code generation processing by the computer system shown in FIG.

FIG. 3 is a program list showing an example of a program for a single processor.

4 is a program list in which the program for the single processor in FIG. 3 is parallelized by a conventional program parallelization method.

FIG. 5 is a program list in which the program for the single processor in FIG. 3 is parallelized by the program parallelization method of the present invention.

6 is a table showing an example of data division information 6 shown in FIG.

FIG. 7 is a table showing an example of parallel execution control information 8 shown in FIG. 1.

FIG. 8 is a schematic diagram showing a configuration example of a parallel processor system that executes a parallelized program generated by the present invention.

FIG. 9 is a diagram showing an example of a parallelized program (without communication code) 7 shown in FIG. 1.

10 is a diagram showing an example of a control flow graph 411 shown in FIG.

11 is a table showing a data structure of a control flow graph 411 shown in FIG. The communication condition determination processing flowchart.

FIG. 12 is a diagram showing an example of a data dependence graph 412 shown in FIG.

13 is a table showing a data structure of a data dependence graph 412 shown in FIG.

14 is a diagram showing an example of a communication target data dependence graph 413 shown in FIG.

15 is a communication object data dependence graph 41 shown in FIG.
The table which shows the data structure of 3. A program obtained by parallelizing the program for the single processor of FIG. 13 according to this embodiment.

16 is a diagram showing an example of a communication control information list 414 shown in FIG.

17 is a table showing a data structure of a communication control information list 414 shown in FIG.

FIG. 18 is a chart showing detailed processing of communication condition determination processing 405 shown in FIG.

19 is a diagram showing an example of information at an intermediate stage of the communication condition determination processing 405 shown in FIG.

20 is a diagram showing an example of a communication control information list 415 shown in FIG.

21 is a table showing the data structure of the communication control information list 415 shown in FIG.

FIG. 22 is a program listing showing an example of a program for a single processor including a two-dimensional array.

FIG. 23 is an explanatory diagram showing an example of a two-dimensional array reference pattern.

FIG. 24 is a program list in which the program for the single processor shown in FIG. 22 is parallelized according to the embodiment of the present invention.

[Explanation of symbols]

1 ... Program parallelization processing, 2 ... FORTRA
N program 3 ... Program division processing, 4 ... Communication code generation processing 5 ... Parallel computer program, 403 ... Communication data extraction processing 404 ... Communication position determination processing, 405 ... Communication conditions Decision processing 411 ... Control flow graph, 412 ... Data dependence graph 413 ... Communication Communication target data dependence graph, 414 ...
..Communication information list, 415 ... Communication control information list.

Front page continuation (72) Inventor Chisato Kanano 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Mitsuyoshi Inagai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Sun Tachicho LSI Engineering Co., Ltd.

Claims (13)

[Claims] 1. Inputting a program for a single processor,
A program parallelization method for converting, by a computer, the input program into a parallelized program for a parallel processor, wherein the converted parallelized program for each processor is analyzed by analyzing the input program. The first step of detecting inter-processor communication that may be necessary when executed by the above, and generating a code for the communication, and analyzing the input program, When the processor executes the parallelized program, a code for controlling to perform communication only when it is determined whether communication with another processor is necessary and it is determined that communication is necessary A second step of generating, a code for the communication and a code for the input program, Those containing a third step of generating a parallelized program adds the code for the control. 2. In the second step, the program part which is always required to perform the inter-processor communication,
2. The program parallelization method according to claim 1, wherein the code for the control in the third step is not generated, and the communication by the code for the communication is unconditionally performed. 3. The inter-processor communication that may be required when the second step is executed in parallel by the plurality of processors detected in the first step,
A flag for managing whether or not the condition requiring the communication is established is newly provided, and a code for updating the value of the flag and a code for controlling the execution of communication by the value of the flag are generated. The program parallelizing method according to claim 1, further comprising steps. 4. A control flow analyzing step of creating a control flow graph from the input program, the control flow graph representing a flow of execution of the input program in a directed graph, and the input program from the control flow graph. It is necessary to communicate between the processors regarding the data dependence analysis step of creating a data dependence graph expressing the definition / reference relationship of variables in a directed graph and the relationship between the definition / reference of each data in the data dependence graph. Communication data extraction processing step of selecting an object and creating a communication target data dependence graph, determining a communication point in the program from the communication target data dependence graph, and providing a communication code to be inserted at that position. A communication position determination processing step of generating and inserting to create a communication information list. The program parallelization method according to claim 1. 5. The variable definition flag generation processing step of generating a code for setting a predetermined flag in the second step, where communication target data of a communication code in the communication information list is defined, and the flag. 5. The program parallelization according to claim 4, further comprising a communication conditional expression generation processing step for generating a code of the communication conditional expression for controlling the communication code to be executed only when is set. Method. 6. The program according to claim 5, wherein the second step further includes a variable definition flag initialization information generation processing step of generating a code for resetting the flag after execution of the communication. Parallelization method. 7. In the second step, further, regarding a flag referred to in the communication conditional expression, the expression defining the flag is checked by tracing the control flow graph in reverse, and the communication conditional expression is always satisfied. In this case, the program parallelization method according to claim 6, further comprising a communication condition reduction processing step of deleting the communication condition expression and the flag. 8. Entering a program for a single processor,
A method of converting the input program into a parallelized program for a parallel processor by a computer, comprising the steps of: (a) dividing the variables of the input program and assigning them to a plurality of processors; By dividing the processing of the input program, assigning to the plurality of processors, (c) by analyzing the input program,
Detecting, for each processor, the presence / absence of a reference to a variable value defined in another processor, and generating a code of a program part for inter-processor communication for the reference, (d) the input By analyzing the program
For each processor, when the processor executes the parallelized program, a step of generating a code of a program part for determining whether or not a reference to the variable value has already been executed, and (e) the processor is parallel for each processor. At the time of executing the optimization program, if the reference to the variable value is not executed yet, the inter-processor communication is controlled to execute the reference to the variable value. And a step of generating a program part for controlling so as not to perform inter-processor communication. 9. A method for converting a program for a single processor into a program to be executed by parallel processors by a computer, wherein the processor refers to data that each processor refers to and is updated by another processor. A variable that indicates whether or not the latest value has been acquired is provided, and in the program part that updates the data, the execution statement string that sets the variable to a value that indicates that communication has not been executed, and the program part that communicates the data. The value of the control variable is inspected by the execution statement string that gives a value indicating that communication has been executed, and the value of the control variable is checked by the program part that refers to the data. A program parallelization method characterized by generating an execution statement sequence for acquiring a value. 10. A variable value that is referred to by each processor and updated by another processor is divided into a direct sum of variable value groups that are collectively referred to during execution, and a control variable is provided for each variable value group. 10. The program parallelization method according to claim 9, wherein when the inter-processor communication of the variable value group is performed, an execution statement string that sets the control variable to a value indicating that communication has been executed is generated. 11. A method for converting a program for a single processor into a program to be executed by parallel processors, wherein each processor refers to array data distributed among a plurality of processors and is processed by another processor. With respect to the part to be updated, a control variable indicating whether or not the processor has acquired the latest value is provided, and in the program part that updates the array, an execution statement string that sets the variable to a value indicating that communication has not been executed. , An execution statement string that is used as a value indicating that communication has been completed in the program part that communicates the data
A program part that refers to the data checks the value of the control variable, and when communication of the data is not completed, generates an execution statement string that acquires the latest value of the data through inter-processor communication. Program parallelization method. 12. A portion of the array data referred to by each processor and updated by another processor is divided into a direct sum of an element group which is always referred to as a group during execution, and a control variable is set for each element group. 11. An execution statement string is provided which sets the control variable to a value indicating that communication has been completed when the element group of the array data is communicated.
The described program parallelization method. 13. A portion of the array data referred to by each processor and updated by another processor is divided into a direct sum of an element group that is always collected during execution, and the array is associated with the array. In a program part that provides a control variable for managing whether each element group of data has been communicated, and communicates the element group of the array data,
The execution statement string that sets the control variable to a value indicating that the element group has been communicated, and the value of the control variable is checked in the program part that refers to the element group, and communication of the element group is not completed. 12. The program parallelization method according to claim 11, wherein in the case, an execution statement string for acquiring the latest value of the element group is generated by inter-processor communication.