JPH07111655A - Moving image processor - Google Patents

Abstract

PURPOSE:To obtain high compression and high picture quality by suppressing the expansion of a circuit scale even when skip block compression is added to inter-frame compression. CONSTITUTION:Only an block synchronizing signal is masked by a data selector 24 for an invalid block when an encoding or a compression processing is performed for continuously inputted moving images, the total number of block is counted, a termination signal is generated at a final block and the compression processing is compulsorily terminated. At the time of a decoding, a block map memory 35 is referred to and in the case of a skip block detection, a decoder 28 is compulsorily stopped. Thus, even when the skip block processing at the time of an encoding where a pseudo block of difference 0 is generated is added, an encoder 26 is controlled without changing the data path of the pipeline of an image signal system and a dynamic address is not generated in a decoding addition frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving image processing apparatus for encoding / decoding moving image compression using digital moving images.

[0002]

2. Description of the Related Art Encoding performed in a conventional moving image compression processing apparatus has a frame structure as shown in FIG.
A frame for intra-frame coding and a frame for inter-frame differential coding (inter-frame coding frame 1
The method of mixing B) and B is predominant.

This interframe coding is very effective when the correlation between frames is high as in a moving image such as video. That is, it is known that by inserting the intra-frame coded frame 1A between a plurality of inter-frame coded frames 1B, the compression efficiency is high and the image disturbance can be minimized even if the image is lost. .

FIG. 5 is a diagram showing a configuration example of a conventional moving image processing apparatus. In this moving image processing apparatus, an image signal of a raster scan signal (not shown) output from an image input device such as a camera is converted into a block scan signal by a raster / block conversion circuit 1 for DCT processing. .

Here, as shown in FIG. 4, since the processing is different between the intra-frame coded frame 1A and the inter-frame coded frame 1B, the intra-frame coded frame 1 is first processed.
The description will start from A.

The image signal converted into the block scan signal passes through the data selector 4 and is input to the DCT circuit 5. The image data calculated by the DCT circuit 5 and converted into DCT coefficients is quantized and Huffman-decoded by the encoder 6 according to a preset table, and is recorded in the code memory 7. The data recorded in the code memory 7 is read to an external storage device (hard disk, tape streamer, magneto-optical storage device, etc.) not shown, and at the same time, is input to the decoder 8 and subjected to Huffman decoding and dequantization. Generate DCT coefficients.

The DCT coefficient is input to the IDCT circuit 9. The data converted from the DCT coefficient to the image data by the IDCT circuit 9 is input to the addition circuit 11. This addition circuit 11 performs addition processing for reconstructing the original image from the difference frame in the inter-coded frame 1B. In the case of the intra-coded frame 1A, "0" is selected by the data selector 10. Therefore, the output result does not change. The output of the adder circuit 11 is written to the frame memory 12, and at the same time, is input to the data selector 2, passes through the data selector 2, and is input to the subtraction circuit 3.

Next, the processing of the inter-coded frame 1B will be described. First, the image signal converted into the block scan signal by the raster / block conversion circuit 1 to perform the DCT processing is input to the subtraction circuit 3 and subtracted from the expanded image of the previous frame. With respect to this difference data, the sum of absolute values is calculated for each block in the data processing circuit 14, and when there is no change from the previous image, the sum of absolute values becomes “0”, so the data selector 4 stops the data. If there is a difference image from the previous image, the sum of absolute values is not "0",
It passes through the data selector 4 and is input to the DCT circuit 5. The result determined by the data processing circuit 14 is recorded in the block map memory 15.

The image data calculated by the DCT circuit 5 and converted into DCT coefficients are quantized and Huffman-decoded by a table preset by the encoder 6 and recorded in the code memory 7.

The data recorded in the code memory 7 is read to an external storage device (hard disk, tape streamer, magneto-optical storage device, etc.) not shown, and at the same time, is input to the decoder 8 for Huffman decoding and inverse quantum. To generate DCT coefficients.

The DCT coefficient is input to the IDCT circuit 9. The difference image data converted from the DCT coefficient by the IDCT circuit 9 is input to the addition circuit 11. The adder circuit 11 is an adder circuit for adding the image of the previous frame and reconstructing the image, and the data selector 10 selects the data from the frame memory 12. The output of the adder circuit 11 is written to the frame memory 12 and at the same time input to the data selector 2. This is repeated for the subsequent frames. Here, the data selector 2 selects "0" only when the intra-coded frame 1A is processed.

Next, the decoding of encoded data (moving image) will be described. First, the encoded data is read from an external storage device (hard disk, tape streamer, magneto-optical storage device, etc.) not shown, and the code memory 7 is read.
After being buffered by, the data is input to the decoder 8, Huffman-decoded and dequantized to generate DCT coefficients. That D
The CT coefficient is input to the IDCT circuit 9. The data converted from DCT coefficients into image data by the IDCT circuit 9 is
It is input to the adder circuit 11. In the case of the intra-frame coded frame 1A, "0" is selected by the data selector 10, so that the output result does not change. Inter-frame coded frame 1
In the case of B, the image of the previous frame recorded in the frame memory 12 is selected by the data selector 10,
The adder circuit 11 adds the difference image and outputs it. The block map memory 15 also outputs the identification information to the address generator 16. Then, in the case of a valid block, the address generator 16 sequentially increments the address and gives it to the frame memory 12. However, in the case of a skip block, an address for jumping one block is given to the frame memory 12. The output of the adder circuit 11 is the block / raster conversion circuit 13
Is converted into a raster scan signal and output as an image signal.

[0013]

However, in order to process continuous data as in the moving image processing in the above-described conventional moving image processing apparatus, it is generally known to perform processing by a pipeline. There is.

In the case of processing by such a pipeline, it is complicated in terms of the circuit configuration to provide a judgment circuit as in the conventional example and to execute or stop a part of the data processing.

Further, since the data of the block which is not sent in the skip block at the time of decoding uses the data of the previous image, it is necessary to dynamically change the address of the memory.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a moving image processing apparatus which suppresses the circuit scale expansion even if the skip block compression is added to the inter-frame compression and obtains high compression and high image quality.

[0017]

In order to achieve the above object, a difference value between a current frame input image and a preceding frame decoded image in continuously input moving images is obtained, and the difference value is encoded. A detection unit for detecting the change between the image of the current frame and the image of the previous frame for each block, and a control unit for controlling the compression operation including the end depending on the change amount by the detection unit previous frame. Provided is a moving image processing device.

Furthermore, when the image of the current frame is the same as the image of the previous frame for each block and only the predetermined identification information is sent, the differential moving image encoded by generating the synchronization signal of the block. Provided is a moving picture processing device including a moving picture decoding means for decoding a signal.

[0019]

The moving image processing apparatus having the above-described structure does not perform compression processing by masking only the block synchronization signal for invalid blocks during encoding or compression processing, and masking only the block sync signal for invalid blocks. The number is counted, an end signal is generated in the last block, and the compression process is forcibly ended. When a skip block is detected by referring to the block map memory when decoding a moving image, the decoder operation is forcibly stopped and a block having a difference of 0 is artificially generated. With such a moving image processing apparatus, the encoder can be easily controlled without changing the data path of the pipeline of the image signal system even if the processing of the skip block at the time of encoding is added, and the dynamic frame can be used even in the addition frame of decoding. Address is not generated.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows the configuration of a moving image processing apparatus as an embodiment according to the present invention, and the encoding and decoding processing will be described.

In this moving image processing apparatus, an image signal of a raster scan signal output from an image input device such as a camera (not shown) is converted into a block scan signal by a raster / block conversion circuit 21 for DCT processing. It

Here, as shown in FIG. 4 described above, the processing is different between the intra-frame coded frame 1A and the inter-frame coded frame 1B. Therefore, the intra-frame coded frame 1A will be described first.

The image signal converted into the block scan signal passes through the data selector 24 and is input to the DCT circuit 25. The image data calculated by the DCT circuit 25 and converted into the DCT coefficient is quantized and Huffman-decoded by the encoder 26 according to a preset table, and then recorded in the code memory 27.

The data of one screen recorded in the code memory 27 is stored in an external storage device (hard disk, not shown).
At the same time as being read out to a tape streamer, a magneto-optical storage device, etc., it is inputted to the decoder 28 and subjected to Huffman decoding and dequantization to generate DCT coefficients.

The DCT coefficient is input to the IDCT circuit 29. The data converted from the DCT coefficient to the image data by the IDCT circuit 29 is input to the adding circuit 31. This adder circuit 31 is used for the inter-coded frame 1
In B, an addition process for reconstructing the original image from the difference frame is performed. In the case of the intra-coded frame 1A, "0" is selected by the data selector 30,
The output result does not change. The output of the adder circuit 31 is written to the frame memory 32, and at the same time, is input to the data selector 22, passes through the data selector 22, and is input to the subtraction circuit 23.

Next, the inter-coded frame 1B will be described. First, the image signal converted into the block scan signal by the raster / block conversion circuit 21 to perform the DCT processing is input to the subtraction circuit 23 and subtracted from the compressed and expanded image of the previous frame. With respect to this difference data, the sum of absolute values is calculated for each block in the data processing circuit 34, and when there is no change from the previous image, the sum of absolute values becomes “0”. Stop only. However, if there is a difference image from the previous image, the sum of the absolute values is not “0” and the sum is passed through the data selector 24 and input to the DCT circuit 25.

The result of the presence / absence of the difference image determined by the data processing circuit 34 is the block map memory 35.
Recorded in. FIG. 2A is a timing chart when compressing data (block processing). As shown in the figure, a BSYNC signal indicating the beginning of the block is usually added to the beginning of the block. 2 (b)
3 is a timing chart of a skip block of data. By deleting (masking) the BSYNC signal in this way, the data compression processing can be masked while the image data remains unchanged. Further, the end of the image can be known by giving the total number of blocks of the image to be processed to the data processing circuit 34 in advance and subtracting the number of processed blocks. This signal is given to the encoder 26,
The compression can be terminated.

The signal obtained by adding the block synchronization signal to the image data is operated by the DCT circuit 25 and converted into a DCT coefficient. The image data converted into the DCT coefficient is quantized and Huffman-decoded by a table preset by the encoder 26, and the code memory 2
Recorded in 7. The data of one screen recorded in the code memory is read to an external storage device (hard disk, tape streamer, magneto-optical storage device, etc.) not shown, and at the same time, is input to the decoder 28 for Huffman decoding and dequantization. And generate DCT coefficients. The DCT coefficient is input to the IDCT circuit 29.

The difference image data converted from the DCT coefficient by the IDCT circuit 29 is input to the adding circuit 31. The data selector 30 selects the data from the frame memory 21. The adder circuit 31 adds the image of the previous frame and the image of the difference frame to reconstruct the image. The output of the adder circuit 31 is written into the frame memory 32 and, at the same time, is input into the data selector 22.

This is repeated for the subsequent frames.
Next, a process of decoding encoded moving image data will be described. First, the encoded data is read from an external storage device (hard disk, tape streamer, magneto-optical storage device, etc.) not shown, buffered in the code memory 27, and then input to the decoder 28 for Huffman decoding and dequantization. To generate DCT coefficients. Its DCT
The coefficient is input to the IDCT circuit 29. IDCT circuit 2
The data converted from DCT coefficients into image data in 9 is input to the adder circuit 31. Intra-frame coded frame 1
In the case of A, since the data selector 30 selects "0", the output result does not change.

In the case of the inter-coded frame 1B, the addition circuit 31 is selected by the image data selector 30 of the previous frame recorded in the frame memory 32.
Is added and output with the difference image. When the inter-coded frame 1B is a skip block, the identification information output from the block map memory 35 is the decoder 28.
A stop signal is given to stop the operation for one block.
Further, the sync signal generation circuit 36 generates a pseudo sync signal. At the same time, the data is masked. As shown in FIG. 3, by pseudo-creating a block having a difference value “0”, the subsequent processing can be made the same as usual.

The output is converted into a raster scan signal by the block / raster conversion circuit 33 and output as an image signal. As described above, the moving image processing apparatus according to the present exemplary embodiment does not change the data path of the pipeline of the image signal system even when the processing of the skip block at the time of encoding is added, and thus does not have a complicated circuit configuration. Moreover, the encoder can be easily controlled. Further, since no dynamic address is generated in the addition frame at the time of decoding the moving image data, a sequential write / sequential read type memory can be used and the circuit configuration of the skip block processing is facilitated. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0033]

As described above in detail, according to the present invention, it is possible to provide a moving image processing apparatus which suppresses the circuit scale expansion even if the skip block compression is added to the inter-frame compression and obtains high compression and high image quality. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a moving image processing apparatus as an embodiment according to the present invention.

FIG. 2 is a timing chart for explaining block processing and skip block processing of the moving image processing apparatus of this embodiment.

FIG. 3 is a timing chart for explaining decompression skip block processing of the moving image processing apparatus of this embodiment.

FIG. 4 is a diagram showing an example of a frame structure of a moving image.

FIG. 5 is a block diagram showing a configuration example of a conventional moving image processing apparatus.

[Explanation of Codes] 1,21 ... Raster / block conversion circuit, 2, 4, 1
0, 22, 24, 30 ... Data selector, 3, 23 ... Subtraction circuit, 5, 25 ... DCT circuit, 6, 26 ... Encoder, 7, 27 ... Code memory, 8, 28 ... Decoder,
9, 29 ... IDCT circuit, 11, 31 ... Adder circuit, 1
2, 32 ... Frame memory, 13, 33 ... Block / raster conversion circuit, 14, 34 ... Data processing circuit, 15,
35 ... Block map memory, 16 ... Address generator, 36 ... Sync signal generating circuit.

Claims (2)

[Claims] 1. A current frame image including an encoding unit for obtaining a difference value between a current frame input image and a previous frame decoded image in continuously input moving images, and encoding the difference value. A moving image process, comprising: a detection unit that detects a change from the image of the previous frame for each block; and a control unit that controls the compression operation including the end depending on the change amount of the detection unit previous frame. apparatus. 2. A differential moving image encoded by generating a block synchronization signal when the image of the current frame does not change from the previous frame image for each block and only predetermined identification information is sent. A moving picture processing device, comprising: a moving picture decoding means for decoding a signal.