JPH07111317A - Nonvolatile dynamic random-access memory array and its manufacture - Google Patents

Abstract

PURPOSE: To miniaturize a non-volatile DRAM by a method wherein the threshold voltage of an EEPROM cell remains low when constant voltage is accumulated on a storage capacitor by a DRAM cell, and the threshold voltage reaches a high value when zero voltage is accumulated. CONSTITUTION: When positive voltage is accumulated on a storage capacitor 2 by a DRAM cell, the positive voltage crossing the tunnel dielectric of an n-channel memory device 4 is in a height which is insufficient to tunnel electrons to a floating gate, and the threshold voltage of the n-channel memory device 4 remains in a negative value. On the contrary, when zero voltage is accumulated on the storage capacitor 2 by the n-channel DRAM, the voltage crossing the tunnel dielectric of the n-channel memory device 4 is sufficiently high to tunnel electrons to a floating gate, and the threshold voltage of the n-channel memory device 4 reaches a positive value. As a result, non-volatile DRAM may be in a small cell size.

Description

Detailed Description of the Invention

[0001]

This invention relates to a non-volatile dynamic random access memory cell having an electrically erasable and electrically programmable memory device coupled to opposite sides of a dynamic random access memoryrel and isolation device. The present invention further relates to a memory array of non-volatile dynamic random access memory cells and a method of manufacturing the same.

[0002]

2. Description of the Related Art U.S. Pat. No. 4,115,914 (issued to Harari on Sep. 26, 1978) and U.S. Pat. No. 4,203,158 (Frohman-Bentchkowsky, May 13, 1980). Since the invention of a non-volatile memory cell having both electrically erasable and electrically programmable capabilities, as disclosed in U.S.A. EEPR using the body
Industrial production of OM and non-volatile RAM has become a reality.

Nonvolatile RAM is a hybrid of static random access memory cells and nonvolatile devices. It functions as a static random access memory under normal conditions, and automatically transfers the memory stored in the static random access memory cell to a non-volatile element when the power drops below a certain limit. When power is restored, the memory is automatically retransferred from the non-volatile device to the static random access memory cell.

[0004]

SUMMARY OF THE INVENTION The main object of the present invention is to obtain an improved non-volatile RAM. One drawback of non-volatile RAM is the large size inherent in static random access memory cells. The proposed improved non-volatile RAM is a non-volatile DRAM having a very small size. Non-volatile DRAM cell is a dynamic random access memory cell and an EEPROM connected to the other side of the isolation device.
Have cells.

During normal conditions of stable power, the gate of the isolation device is grounded and the DRAM cell is completely isolated from the EEPROM cell. Therefore, the non-volatile DRAM cell functions exactly as a DRAM cell. When the sensor circuit senses that the power has dropped below a certain limit, the gate of the isolation device and the control gate of the EEPROM cell reach an appropriately high potential, while EEPROM
The select gate of the M cell is still grounded.

When a DRAM cell stores a constant voltage on the storage capacitor, the voltage across the tunnel dielectric of the EEPROM cell is insufficient to tunnel charge carriers to the floating gate of the EEPROM cell, and The threshold voltage remains low. On the other hand, if the DRAM cell has stored zero volts on the storage capacitor, the voltage across the tunnel dielectric of the EEPROM cell is high enough to tunnel charge carriers to the floating gate of the EEPROM cell, and the threshold of the EEPROM cell. Value voltage reaches high value. When power is restored, the EEPROM drain, select and control gates, and isolation device gates reach the appropriate voltages.

The storage capacitor of the DRAM cell is EEPR
If the threshold voltage of the OM cell is low, it will be charged to a constant voltage as before. On the contrary, the storage capacitor of the DRAM cell remains at zero volts as before when the threshold voltage of the EEPROM cell is high. After the charge is restored, the gate of the isolation device reaches ground potential and the DRAM cell is isolated from the EEPROM cell.
To reset the EEPROM cell to its initial state, a voltage of appropriate height is applied to the drain and select gates of the EEPROM cell while grounding the control gate of the EEPROM cell and the gate of the isolation device. By doing so, the threshold voltage of the EEPROM cell is restored to a low value.

Another object of the present invention is to obtain a high density non-volatile DRAM array which is equivalent to a DRAM memory array during normal operation. Yet another object of the invention is to obtain a method of manufacturing a non-volatile DRAM memory array according to three advantageous embodiments of the invention.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred first embodiment of a non-volatile DRAM cell according to the invention is shown in FIG. The non-volatile DRAM cell includes a DRAM having an access transistor 1 and a storage capacitor 2, an EEPROPM having an access transistor 5 and a memory device 4, and a DRAM and an EEPR.
The isolation transistor 3 between the OMs is provided. For convenience of explanation, an n-channel nonvolatile DRAM is used as an example.

Grounded n-channel isolation transistor 3
An n-channel non-volatile DRAM having a gate of 1 functions exactly like a normal n-channel DRAM when the power is stable. However, when the sensor circuit detects that the power has dropped below a certain limit, the gates of the n-channel isolation transistor 3 and the control gate of the n-channel memory device 4 immediately reach a suitable high positive potential and the n-channel access transistor The select gate of 5 remains at ground potential.

When the DRAM cell stores a positive voltage on the storage capacitor 2, the positive voltage across the tunnel dielectric of the n-channel memory device 4 is not high enough to tunnel electrons to the floating gate, n- The threshold voltage of the channel memory device 4 remains negative. On the contrary, when the n-channel DRAM stores a zero voltage on the storage capacitor 2, the voltage across the tunnel dielectric of the n-channel memory device 4 is high enough to tunnel electrons to the floating gate, n The threshold voltage of the channel memory device 4 reaches a positive value. When power is restored, n-channel EEP
The drain of the ROM, the select gate and the control gate, and the gate of the isolation transistor 3 all reach positive values.

If the threshold voltage of n-channel memory device 4 is at a negative value, storage capacitor 2 will be charged to a positive value. Contrary to this, n-channel memory device 4
If the threshold voltage at is positive, the storage capacitor 2 remains at zero volts. Thus, the voltage of the storage capacitor 2 recovers before the power drops below a certain limit. After the voltage of the storage capacitor 2 is restored, the gate of the n-channel isolation transistor 3 reaches the ground potential and the n-channel DR
The AM is separate from the n-channel EEPROM.

To reset the n-channel memory device 4 to its initial state, a suitably high positive voltage is applied to the drain and select gate of the n-channel transistor while grounding the control gate of the memory device. By doing so, the threshold voltage of the n-channel memory device 4 is reset to a negative value.

Second non-volatile DRAM cell according to the present invention
An advantageous embodiment of the is shown in FIG. A non-volatile DRAM cell comprises a DRAM having an access transistor 1 and a storage capacitor 2, an EEPROM having an access transistor 5 and a memory device 4, and a gate shorted to the control gate of the memory device 4
It includes an isolation transistor 3 that isolates the EPROM. The operating principle of this non-volatile DRAM is
It is the same as that of the embodiment.

A third non-volatile DRAM cell according to the present invention.
An advantageous embodiment of is shown in FIG. This non-volatile DRA
The M cell is an access transistor 1 and a storage capacitor 2.
And an EEPROM comprising a memory device 4 and an access transistor 5 having a drain shorted to a select gate and a DRAM and an EEPROM having a gate shorted to the control gate of the memory device 4.
And an isolation transistor 3 for isolating.

FIG. 4 illustrates a method of connecting a non-volatile DRAM cell to a non-volatile DRAM memory array mold according to a third preferred embodiment of the present invention. Similar to a normal DRAM array, the drains of all access transistors 1 in the same row are connected to the same bit line such as B1 and B2, and the gates of all access transistors 1 in the same column are the same word such as W1 and W2. Connected to the line, all capacitors 2 are connected to the same CAP line. Furthermore, the control gates of all memory devices 4 and the gates of all isolation transistors 3 are connected to the same PGM line, and the drains and gates of all access transistors 5 are the same PGM '.
Connected to the wire.

The operation of the DRAM array in this nonvolatile DRAM memory array is the same as that of a normal DRAM array. When the power monitoring sensor circuit on the same chip detects that the voltage drops below a certain limit, the PGM line is placed at an appropriately high potential while holding the PGM 'line at the ground potential. The voltage state of each DRAM storage capacitor 2 is thus stored in the memory device 4 of the same non-volatile DRAM cell. When the power is restored, an appropriate voltage is applied to the PGM line and PGM 'line, the gate of the access transistor 1 is grounded, and the CAP line remains at an appropriate potential. After the voltage state of the storage capacitor 2 is restored, the PGM line and PG
The M'line returns to ground potential. Next, when the PGM 'line reaches an appropriate high potential while keeping the PGM line still at the ground potential, all the memory devices 4 are reset to the initial normally-on state.

The non-volatile DRAM according to the first preferred embodiment of the present invention is implemented by a self-aligned double polysilicon manufacturing method as shown in FIG. The non-volatile DRAM according to the second preferred embodiment of the present invention is implemented by a non-self-aligned double polysilicon manufacturing method as shown in FIG. The nonvolatile DRAM according to the third preferred embodiment of the present invention is implemented by a single polysilicon manufacturing method as shown in FIG.

FIG. 5 is a plan view of a non-volatile DRAM according to a first preferred embodiment of the present invention implemented by a self-aligning double polysilicon manufacturing method, FIG. 6 is a sectional view taken along line AA of FIG. 5, and FIG. It is the BB sectional view taken on the line of FIG. Non-volatile DR
AM is an access transistor 5 and a memory device 4
, An DRAM having an access transistor 1 and a storage capacitor 2, and a separation transistor 3 for separating the EEPROM from the DRAM.

The n-channel non-volatile DRAM is constructed on a P-type substrate 9 such as single crystal silicon. The memory device 4 is disposed above the channel region and is electrically shorted to the floating gate 30, the floating gate 30 separated from the channel region by the gate oxide 21, disposed above the buried drain, and the tunnel dielectric. Additional floating gate 31, floating gate 3 separated from buried drain by body 22
0, and includes a control gate 50 separated from floating gate 30 by inter-gate dielectrics 40, 41, and a buried n + junction 10 that serves as a buried source and drain of memory device 4.

Buried source 10 and buried drain 10
Are arranged below the additional floating gate 31.
The additional floating gate 31 is located on the sidewall of the control gate 50 and isolated from the control gate 50. The shallow junction 11 forms the source / drain of the peripheral transistor. The access transistor 5 includes a selection gate 90,
This gate is located on the substrate between the source and the drain and is insulated from this substrate by the gate oxide 21. The storage capacitor 2 includes a capacitor plate 390, which is located above the buried junction 19 and separated from this junction by a thin gate dielectric 121. Access transistor 1 includes a gate 490, which is located on the substrate between the source and drain and is insulated from the substrate by a thin gate dielectric 121. The isolation transistor 3 comprises a gate 590, which is arranged on the substrate between the source and the drain and is insulated from this substrate by the gate oxide 21.

The metal wiring 80 is connected to the drains of all the access transistors 1 in the same row via the contacts 70. The drains of all access transistors 5 are connected to a common drain diffusion line 525. Doped C
The VD oxide film 60 is under the metal wiring in order to smooth a sharp edge. Thick field oxide 20 serves as a separator between different devices.

When a suitable voltage is applied to the control gate 50 while the buried drain is grounded, electrons tunnel from the buried drain through the tunnel dielectric 22 to the additional floating gate 31. Contrary to this, control gate 5
When an appropriate voltage is applied to the buried drain with 0 grounded, electrons tunnel from the additional floating gate 31 through the tunnel dielectric 22 to the buried drain.

Excessive electrons in the floating gate 30 and the additional floating gate 31 of the EEPROM memory device 4 increase the positive voltage required on the control gate 50 to conduct current through the EEPROM memory device 4. On the contrary, when the floating gate 30 and the additional floating gate 31 of the memory device 4 of the EEPROM are lacking in electrons, E
Since the current is conducted through the memory device 4 of the EPROM, the positive voltage required for the control gate 50 is low. Therefore, the presence or absence of current flowing through the EEPROM memory device 4 at the voltage applied to the control gate 50 indicates whether a 1 or 0 is stored in the EEPROM memory device 4.

Fabrication of the non-volatile DRAM shown in FIG. 5 will now be described in detail. For convenience of explanation, n-channel non-volatile DRA
M is used as an example. A CVD nitride thin film is deposited on the starting oxide grown on the P-type substrate as in conventional n-channel EEPROM fabrication. Next, a photoresist pattern in the active region is formed on the nitride film, and the nitride outside the photoresist pattern is removed by corrosion.

Next, P-type impurity boron is implanted into regions outside the photoresist pattern to enhance substrate doping outside the active regions. This is done to raise the threshold voltage of the parasitic field device and improve isolation between the active regions. The photoresist pattern after the boron implant is stripped and a thick field oxide 20 is grown outside the active area. During field oxidation, active regions 25 and 525 are still protected by the nitride pattern and no oxide grows. After the field oxide 20 has grown,
The nitride of the active regions 25 and 525 and the initial oxide under the nitride are stripped, exposing only the active region of the substrate.

Next, 200A to 1000A of high quality gate oxide 21 is grown on the active regions 25 and 525 to form a photoresist pattern and 3E11 to 3E12 / cm.
Exposing the EEPROM area for a ^two dose boron implant. After stripping the photoresist pattern, first layers 30, 90 and 590 of polysilicon are deposited and doped.

Next, using a photoresist pattern, the first
Pattern the layer polysilicon. After stripping the photoresist pattern, high quality oxides 40 and 45 are grown on the first polysilicon and then high quality nitride films 41 and 46 are deposited and oxidized. Next, a photoresist pattern is formed to protect the EEPROM area and the first polysilicon area while removing the nitride 45 and oxide from the second polysilicon device area. Growing a high quality gate oxide for the second polysilicon device and performing an impurity implant to adjust the threshold of the second polysilicon device.

Next, using a photoresist pattern, 1E
12 to 1E15 / cm ² dose embedded capacitor n +
Expose the storage capacitor region for implantation. After stripping the photoresist pattern, a second layer of polysilicon is deposited and doped. The control gate 50 and the second polysilicon gate pattern 3 using the photoresist pattern
Pattern 90, 490 and peripheral devices.

After stripping the photoresist pattern, FIG.
And as shown in FIG. 9, the oxide layer 51 is formed on the second polysilicon control gate 50 and other second polysilicon patterns 3.
Grow on 90,490. Next, the nitride film 46 outside the second polysilicon control gate is removed by corrosion. Next, as shown in FIGS. 10 and 11, a photoresist pattern is used to expose only the EEPROM and the first polysilicon outside the second polysilicon control gate is etched away. After removing the photoresist pattern, as shown in FIGS. 12 and 13, a seal nitride film 59 is deposited and oxidized.

Anisotropic etching is used to remove all nitride except the seal nitride 58 on the sidewalls of the polysilicon pattern. Next, a photoresist pattern is formed, and a buried n + of 5E13 to 5E15 / cm ² dose is implanted.
The EEPROM area for implant 10 is exposed. After peeling off the photoresist pattern, a new photoresist pattern 69 is formed, and as shown in FIGS.
Expose the tunnel dielectric region of the EPROM drain,
The oxide is corroded away so that the substrate 68 is exposed. Strip the photoresist pattern again, then tunnel dielectric 2
8 is formed.

Next, the seal nitride on the side wall of the floating gate 30 is removed with hot phosphoric acid. An additional polysilicon layer is deposited and doped. Anisotropic etching is used to remove all the additional polysilicon film except the additional polysilicon 31 on the sidewalls of the floating gate 30,
An additional floating gate 31 is formed. Tunnel dielectric region 22 below additional floating gate 31
Becomes the new small tunnel dielectric region.

While removing additional polysilicon from the sidewalls of all other polysilicon patterns using photoresist pattern 67, as shown in FIGS.
Protects the EEPROM area. After stripping the photoresist pattern, a shallow source / drain junction 11 is implanted to obtain the EEPROM shown in FIGS. 18 and 19. The rest of the manufacturing process is similar to that of a conventional n-channel EEPROM.

After growing an oxide on the additional polysilicon and the exposed tunnel dielectric region, the doped CV
A D oxide film is deposited, contacts are opened, a metal film is deposited and patterned.

FIG. 20 is a plan view of a non-volatile DRAM according to a second preferred embodiment of the present invention implemented by a non-self-aligned double polysilicon manufacturing method, FIG. 21 is a sectional view taken along the line AA of FIG. 20 and FIG. It is a -B line sectional view. The non-volatile DRAM includes an EEPROM having an access transistor 5 and a memory device 4, a DRAM having an access transistor 1 and a storage capacitor 2, and a control gate of the memory device 4 and a gate short-circuited to the EEP.
It is composed of a separation transistor 3 for separating the ROM and the DRAM. The n-channel non-volatile DRAM is constructed on a P-type substrate such as single crystal silicon.

The memory device 4 is located above the channel region and is electrically shorted to the floating gate 30, electrically isolated from the channel region by the gate oxide 21 and located above the buried drain. And is disposed above the additional floating gate 31, floating gate 30, and additional floating 31 separated from the buried drain by the tunnel dielectric 22, and separated from these floating gates by inter-gate dielectrics 40 and 41. Control gate 50 and a buried n + junction 10 serving as a buried source and drain of an EEPROM.
including. The buried source and the buried drain are located below the additional floating gate 31 and the control gate 50 and are separated from the control gate 50 by an intergate dielectric 41 and an oxide layer 21. The shallow junction 11 forms the source / drain of the peripheral transistor.

Access transistor 5 includes a select gate 90 disposed on the substrate between the source and drain,
This gate is insulated from the substrate by the gate oxide 21. The storage carrier 2 includes a capacitor plate 390, which is located over the buried junction 10 and is insulated from the buried junction 10 by the intergate dielectric 41 and the thin gate dielectric 24. Accessor transistor 1
Has a gate 490 disposed on the substrate between the source and drain, the gate from the substrate to the gate dielectric 12
Separated by 1. Finally, the isolation transistor 3 comprises a gate 50 which is insulated above the substrate by means of an intergate dielectric 41 and a gate dielectric 24.

Metal wiring 80 connects the drains of all access transistors 1 of the DRAMs in the same row via contacts 70. The drains of all access transistors 5 are coupled to a common drain diffusion 525.
Doped CVD oxide 60 underlies the metal to smooth sharp edges. Thick field oxide 20 aids in isolation between different devices.

When a suitable voltage is applied to the control gate 50 while grounding the buried drain, electrons tunnel from the buried drain through the tunnel dielectric 22 to the floating gate 30 and the additional floating gate 31. On the other hand, when the control gate 50 is grounded and a suitable voltage is applied to the buried drain, electrons tunnel from the additional floating gate 31 through the tunnel dielectric 22 to the buried drain. If there are excess electrons in the floating gate 30 and the additional floating gate 31 of the memory device 4 of the EEPROM, the EEPR
Since the current is conducted through the memory device of the OM, the positive voltage required for the control gate 50 is higher.

On the contrary, if electrons are insufficient in the floating gate 30 and the additional floating gate 31 of the memory device 4 of the EEPROM, the EEPROM is
Since the current is conducted through the M memory devices 4, the positive voltage required for the control gate 50 is low. Therefore, it is EEP whether there is a current conducted through the memory device 4 of the EEPROM at the voltage applied to the control gate 50.
Indicates whether 1 or 0 is stored in the memory device 4 of the ROM.

A method for manufacturing the nonvolatile DRAM shown in FIG. 20 will be described in detail. For convenience of description, n-channel non-volatile DR
AM is used as an example. P-type short crystalline silicon is used as a starting substrate. C on top of the initial oxide grown on the P-type substrate as in the conventional n-channel EEPROM fabrication process.
A VD nitride thin film is deposited. Next, a photoresist pattern in the active region is formed on the nitride film, and the nitride outside the photoresist pattern is removed by corrosion. Next, a P-type impurity boron is implanted into regions outside the photoresist pattern to enhance substrate doping outside the active regions. This is done to raise the threshold voltage of the parasitic field device to improve isolation between the active regions.

After the boron implant, the photoresist pattern is stripped and a thick field oxide 20 is grown outside the active area. During field oxidation, active regions 25 and 52
5 is still protected by the nitride pattern and no oxide grows. After the field oxide growth, the nitride in the active region and the first oxide under the nitride are stripped to expose the substrate only in the active region. Next, 200A to 1000A of high quality gate oxide 21 is grown on the active regions 25 and 525 to form a photoresist pattern and 3E11 to 3E11.
EEPRO for boron implantation at E12 / cm ² dose
Expose the M region. After stripping the photoresist pattern, the first layer of polysilicon 30 and 90 is deposited and doped.

Next, oxide layers 39 and 99 are grown on the polysilicon 30 and 90. Floating gate 30 forming a photoresist pattern and having oxide 39
And gate 90 of the access transistor with oxide 99 and polysilicon is removed from the outside of the photoresist pattern. 20A and 20B after the photoresist pattern is peeled off are shown in FIGS. 23 and 24, respectively.

Next, as shown in FIGS. 25 and 26, a seal nitride film 49 is deposited and oxidized. Anisotropic etching is used to remove all nitride except the seal nitride 48 on the sidewalls of floating gate 30 and gate 90 of access transistor 5, as shown in FIGS. As shown in FIGS. 29 and 30, a photoresist pattern 26 is formed to form 5E13 to 5E15 / cm.
EEPROM for ^2- dose buried n + implant layer 10
Exposing the region and the storage capacitor region.

After stripping the photoresist pattern, a new photoresist pattern is formed to expose the tunnel dielectric region of the drain of the memory device 4 of the EEPROM and the oxide is etched away to expose the substrate. Next in FIG.
1 and 32, a tunnel dielectric 28 is formed and the photoresist pattern is stripped. The tunnel dielectric 28 is formed and the side walls of the floating gate 30 and the gate 90 of the access transistor 5 are sealed with nitride 4.
8 is later removed with hot phosphoric acid. An additional polysilicon layer 38 is deposited and doped as shown in FIGS.

An additional polysilicon 31 on the sidewalls of the floating gate 30 and a gate of the access transistor 5 to form an additional floating gate 31 as shown in FIGS. 35 and 36 using an anisotropic polysilicon etch. All the additional polysilicon film except the additional polysilicon 91 on the side wall is removed. The tunnel dielectric region 22 below the additional floating gate 31 becomes a new small tunnel dielectric region. Oxide layer 39 on floating gate 30 and access transistor 5
The oxide layer 99 on the gate of the gate is then removed and a high quality oxide layer 40 is grown on the floating gate 30, while oxide 23 is also grown on the exposed tunnel dielectric region. High quality nitride films 41 and 47 are deposited and later oxidized.

Next, as shown in FIGS. 37 and 38, a photoresist pattern 56 is formed, and while removing the nitride 41 and the oxide under the nitride 41 in the second polysilicon device region, the EEPROM region and the first region are removed. Protect the polysilicon gate area. A high quality gate oxide of the second polysilicon device is grown and an impurity implant is performed to adjust the threshold of the second polysilicon device. A second layer of polysilicon is then deposited and doped. The pattern of the control gate 50 and the second polysilicon gate is patterned using the photoresist pattern. The control gate formation after resist removal is shown in FIGS. The rest of the manufacturing process is similar to that of a conventional n-channel EEPROM. After forming the second polysilicon pattern,
Shallow source / drain junction 11 implanted and doped CV
A D oxide film is deposited, contacts are opened, a metal film is deposited and patterned.

FIG. 41 shows a non-volatile DRA according to an advantageous third embodiment of the present invention implemented in a single polysilicon process.
42 is a plan view of FIG. 41A-A line, and FIG. 43 is a cross-sectional view of FIG. 41B-B line. The non-volatile DRAM is a DR having an access transistor 1 and a storage capacitor 2.
AM, single polysilicon EEPROM having a drain shorted to the gate of access transistor 5B, and DRAM and single polysilicon EEP with a gate shorted to the diffusion control gate line of memory device 4B.
It is composed of a separation transistor 3 for separating the ROM.

The single polysilicon EEPROM has access transistors 5A and 5B and a diffusion control gate line 4A.
And a memory device 4B. Access transistor 5A is in series with diffusion control gate line 4A and access transistor 5B is in series with memory device 4B. The n-channel non-volatile DRAM is constructed on a P-type substrate such as single crystal silicon.

The memory transistor 4B includes a floating gate 30 located above the conductive channel of the memory transistor 4B, a buried n + 10 bottom plate of the drain coupling capacitor, and a tunnel dielectric region 4C on the diffusion control gate line 4A. The floating gate 30 is separated from the conductive channel and drain buried n + 10 by an oxide 21 and from the buried n + 10 of the tunnel dielectric region 4C by a thin tunnel dielectric 22. The buried n + 10 also serves as the source-drain junction of the memory transistor.

Access transistors 5A and 5B have polysilicon gate 9 located above the conductive channel region.
Including 0. Polysilicon gate 90 is separated from the conductive channels of access transistor 5A and access transistor 5B by gate oxide 21. Embedded n
The + junction 10 serves as the source / drain of the access transistor 5A and the access transistor 5B. In the normal usage, since the access transistor 5A is an enhancement type, there is no leak current passing through the access transistor 5B when the gate 90 is at the ground potential. However, access transistor 5B can be either enhancement type or depletion type.

Isolation transistor 3 has a polysilicon gate 590 located above the channel region, which gate is insulated from the channel region by gate oxide 21. The polysilicon gate 590 is the memory device 4
B diffusion control gate 4A is coupled by a buried contact. Access transistor 1 of the DRAM includes a polysilicon gate 490 located above the channel region, which gate is isolated from the channel region by gate oxide 21.

The storage capacitor 2 of the DRAM has a buried n +
Polysilicon plate 390 disposed over the junction 10.
And the plate is insulated from the buried n + junction 10 by a gate oxide 21. The shallow junction 11 serves as a source / drain junction for the isolation transistor 3 and the access transistor 1. Metal wiring 80 is contact 70
The drains of all access transistors 1 in the same row are coupled via. Similarly, the metal wiring 81 is connected to the contact 17
The drains of all access transistors 5A in the same row are connected through 0. Doped CVD oxide 60 underlies the metal lines to smooth the sharp edges. Thick field oxide 20 aids in isolation between different devices.

When an appropriate positive voltage is applied across the diffusion control gate line 4A and the drain of the memory transistor,
The electrons travel from the floating gate 30 to the diffusion control gate line 4A through the tunnel dielectric 22 in the overlap region 4C between the floating gate and the diffusion control gate line 4A.
Tunnel to. Similarly, by applying a proper positive voltage from the drain of the memory transistor to the diffusion control gate line 4A, electrons are transferred from the diffusion control gate line 4A to the floating gate 30 of the memory transistor 4B through the tunnel dielectric 22 of the tunnel dielectric region 4C. Tunnel.

If there are excess electrons in the floating gate 30 of the memory transistor 4B, a current is led through the memory transistor 4B, so the diffusion control gate line 4A
The higher the positive voltage required is. On the other hand, if the floating gate 30 of the memory transistor 4B lacks electrons, a current is conducted through the memory transistor 4B, so that the positive voltage required for the diffusion control gate line 4A becomes low. Therefore, whether or not there is a current flowing through the memory transistor 4B at the voltage applied to the diffusion control gate line 4A indicates that 1 or 0 is stored in the memory transistor 4B.

A method of manufacturing the nonvolatile DRAM cell shown in FIG. 41 will be described in detail. For convenience of explanation, an n-channel MOS memory array is used as an example. A P-type single crystal is used as a starting substrate. A CVD nitride thin film is deposited on the starting oxide grown on the P-type substrate as in conventional n-channel MOS transistor fabrication. Next, a photoresist pattern in the active region is formed on the nitride film, and the nitride outside the photoresist pattern is removed by corrosion. Next, a P-type impurity boron is implanted into regions outside the photoresist pattern to enhance substrate doping outside the active regions.
This is done to raise the threshold voltage of the parasitic field device and improve isolation between the active regions.

After the boron implant, the photoresist pattern is stripped and a thick field oxide is grown outside the active area. During field oxidation the active regions 25 and 125 are still protected by the nitride pattern and no oxide grows. After the field oxide is grown, the nitride in the active regions 25 and 125 and the starting oxide under the nitride are etched away, exposing only the active region of the substrate.

Next, 200A to 1000A of high quality gate oxide 21 is grown in active regions 25 and 125. After the high quality gate oxide 21 is grown, the threshold voltage of various transistors is adjusted by implanting the appropriate impurities into the channel region while using a photoresist pattern that protects the regions that do not require adjustment. Next in FIG.
4 and FIG. 45, the photoresist pattern 26
To form n-type impurities such as arsenic and phosphorus, 5E13-
Expose areas requiring buried n + implant 10 in the 5E15 / cm ² dose range. The buried n + implant is performed after the gate oxide 21 is grown in order to reduce heavy implants which induce strong oxidation problems. After the embedded n + implantation, the photoresist pattern is peeled off.

Next, as shown in FIGS. 46 and 47, a photoresist pattern 29 is formed to form the tunnel dielectric region 4.
C and gate oxide 21 in tunnel dielectric region 4C is exposed. Next, a high quality tunnel dielectric thin film of 40A to 150A is formed in the tunnel dielectric region 4C. Next, as shown in FIGS. 48 and 49, a photoresist pattern 12 is formed.
9 is formed to expose the buried contact region and the gate oxide 21 is etched away to expose the substrate 270.

Next, the photoresist pattern is peeled off and CV
D Polysilicon film is deposited on the surface. Next, a polysilicon film is doped, and the floating gate 30 of the memory transistor 4B, the poly gate 90 of the access transistors 5A and 5B, the gate 590 of the isolation transistor 3, the gate 490 of the access transistor 1, and the polysilicon plate 3 of the storage capacitor 2 are doped.
Pattern 90 and the gates of the peripheral transistors. The rest of the manufacturing process is similar to that of the conventional n-channel transistor. After forming the polysilicon gate,
The source-drain junction is implanted, the doped CVD oxide film is deposited, the contacts are opened, the metal film is deposited and patterned.

The invention has been described in the form of advantageous embodiments. Various modifications of the advantageous embodiments disclosed herein may be practiced by those skilled in the art with reference to this disclosure without departing from the scope and spirit of the invention. Further, such improvements are considered to be within the scope of the claims. The novel features of the invention are set forth in the appended claims. The invention and other features, together with its advantages, can be readily understood by the foregoing detailed description read in conjunction with the drawings.

[0062]

According to the present invention as described above, the nonvolatile R
AM is a non-volatile DRA with very small cell size
It can be formed into M. Also, during normal operation DRA
High-density non-volatile DRAM equivalent to M memory array
An array can be obtained.

[Brief description of drawings]

FIG. 1 One set of non-volatile DRAM according to the first embodiment of the present invention
Cell schematic. FIG. 2 One set of non-volatile DRAM according to the second embodiment of the present invention
Cell schematic. FIG. 3 One set of non-volatile DRAM according to the third embodiment of the present invention
Cell schematic. 4 is a nonvolatile DRAM array composed of the nonvolatile DRAM cells of FIG. 5 is a plan view of a set of non-volatile DRAM cells implemented by a high density self-aligned EEPROM cell having a self-aligned tunnel dielectric region according to a first embodiment of the present invention. 6 is a cross-sectional view taken along the line AA of FIG. 7 is a cross-sectional view taken along the line BB of FIG. 5 FIG. 8 is a cross-sectional view taken along the line AA of FIG. 9 is a sectional view corresponding to the line BB of FIG. 5 above. 10 is a sectional view taken along the line AA of FIG. 5 showing the first polysilicon etching by the photoresist pattern for protecting the first polysilicon device according to the first embodiment of the present invention. 11 is a sectional view corresponding to the line BB of FIG. 5 above. 12 is a cross-sectional view taken along line AA of FIG. 5 showing the formation of the seal nitride after the formation of the first polysilicon floating gate according to the first embodiment of the present invention. 13 is a sectional view corresponding to the line BB of FIG. 5 above. 14 is a cross-sectional view taken along line AA of FIG. 5 showing oxide removal from the tunnel dielectric region according to the first embodiment of the present invention. 15 is a sectional view corresponding to the line BB of FIG. 5 of FIG. 5 above. FIG. 16 Protect a new floating gate of additional polysilicon on the first polysilicon floating gate sidewall while removing all additional polysilicon on the sidewalls of all other polysilicon patterns according to the first embodiment of the present invention. Sectional drawing corresponding to the AA line of FIG. 5 which shows a photoresist. 17 is a sectional view corresponding to the line BB of FIG. 5 above. 18 is a cross-sectional view taken along the line AA of FIG. 5 showing a new floating gate made of additional polysilicon on the sidewall of the first polysilicon floating gate according to the first embodiment of the present invention. 19 is a sectional view corresponding to the line BB of FIG. 5 above. 20 is a plan view of a set of nonvolatile DRAM cells implemented by a high density self-aligned EEPROM memory cell having a self-aligned tunnel dielectric region according to the second embodiment of the present invention, and a cross-sectional view taken along the line AA of FIG. . 22 is a cross-sectional view taken along the line BB of FIG. 23 is a cross-sectional view taken along the line AA of FIG. 20 showing the formation of the first polysilicon floating gate during the front end processing step according to the second embodiment of the present invention. 24 is a cross-sectional view taken along line BB of FIG. 20 above. FIG. 25 is a cross-sectional view taken along the line AA of FIG. 20 showing seal nitride deposition after forming the first polysilicon floating gate according to the second embodiment of the present invention. 26 is a cross-sectional view corresponding to the line BB of FIG. 20 above. 27 is a cross-sectional view taken along the line AA of FIG. 20 showing the formation of the seal nitride on the sidewall of the first polysilicon floating gate according to the second embodiment of the present invention. 28 is a sectional view corresponding to the line BB of FIG. 20 above. 29 is a cross-sectional view taken along the line AA of FIG. 20 showing the impurity implantation for forming the buried source and the buried drain of the EEPROM according to the second embodiment of the present invention. 30 is a cross-sectional view corresponding to the line BB of FIG. 20 above. 31 is a cross-sectional view taken along line AA of FIG. 20 showing the formation of a tunnel dielectric according to the second embodiment of the present invention. 32 is a sectional view corresponding to the line BB of FIG. 20 above. FIG. 33 is a cross-sectional view taken along the line AA of FIG. 20 showing additional polysilicon deposition after removing the seal nitride from the sidewall of the first polysilicon floating gate according to the second embodiment of the present invention. 34 is a sectional view corresponding to the line BB of FIG. 20 above. 35 shows an additional polysilicon formation of the first polysilicon floating gate sidewall for forming a new floating gate according to the second embodiment of the present invention.
Sectional drawing corresponding to A line. 36 is a sectional view corresponding to the line BB of FIG. 20 above. 37 is a cross-sectional view taken along the line AA of FIG. 20 showing removal of the inter-gate dielectric in the second polysilicon gate device region according to the second embodiment of the present invention. 38 is a cross-sectional view corresponding to the line BB of FIG. 20 above. FIG. 39 is a sectional view taken along the line AA of FIG. 20 showing the formation of the second polysilicon control gate according to the second embodiment of the present invention. 40 is a cross-sectional view corresponding to the line BB of FIG. 20 above. FIG. 41 is a plan view of a single polysilicon nonvolatile DRAM cell implemented in a single polysilicon EEPROM according to the third embodiment of the present invention. 42 is a cross-sectional view taken along the line AA of FIG. 43 is a cross-sectional view taken along the line BB of FIG. FIG. 44 is a cross-sectional view taken along the line AA of FIG. 41 showing a buried n + forming step according to the third embodiment of the present invention. 45 is a cross-sectional view corresponding to the line BB of FIG. 41 above. FIG. 46 is a cross-sectional view taken along the line AA of FIG. 41 showing the tunnel dielectric formation according to the third embodiment of the present invention. FIG. 47 is a sectional view taken along the line BB of FIG. 41 above. 48 is a sectional view taken along the line AA of FIG. 41, showing the buried contact according to the third embodiment of the present invention. FIG. 49 is a cross-sectional view corresponding to the line BB of FIG. 41 above. 50 is a cross-sectional view taken along the line AA of FIG. 41, showing a polysilicon gate forming step according to the third embodiment of the present invention. 51 is a cross-sectional view taken along the line BB of FIG. 41 above.

[Explanation of symbols]

 1 DRAM Access Transistor 2 Capacitor 3 Separation Transistor 4 EEPROM Memory Device 5 EEPROM Access Transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 16/02

Claims (14)

[Claims] 1. Information can be stored as a dynamic random access memory (DRAM), and
In an electrically rewritable nonvolatile dynamic random access memory cell that can also store information as a nonvolatile memory, electrically erasable, and
Electrically programmable memory cell (EEPRO
M), a MOS dynamic random access memory cell (DRAM) and a MOS isolation transistor,
The EEPROM comprises an electrically rewritable nonvolatile MOS floating gate type memory device (4) and a MOS access transistor (5), and the memory device (4) has a first electrode (drain), a second electrode (control gate), A third electrode (source) and a fourth electrode (floating gate) are provided, a tunnel region is provided in the first electrode (drain) below the fourth electrode (floating gate), and the access transistor (5) has the first electrode ( A drain), a second electrode (gate) and a third electrode (source), the third electrode (source) being electrically connected to the first electrode (drain) of the floating gate type memory device (4), The dynamic random access memory cell (DRAM) is a MOS access transistor (1) and a capacitor. Consists (2), the access transistor (1) the first electrode (drain), a second electrode (gate) and a third electrode (source), the capacitor is first
An electrode and a second electrode, the first electrode is electrically connected to the third electrode (source) of the access transistor (1) of the DRAM, and the isolation transistor is the first electrode (drain) and the second electrode (gate). ) And a third electrode (source), the first electrode (drain) is electrically connected to the third electrode (source) of the floating gate type memory device (4), and the third electrode (source) is a DRAM. Of the access transistor (1) is electrically connected to the third electrode (source) of the isolation transistor (3), and the second electrode (gate) of the isolation transistor (3) is grounded so that the DRAMs (1) and (2) are 4) and (5), the second electrode (gate) of the isolation transistor (3) is placed at the first potential of the first polarity, and the floating gate type memory device By placing the second electrode (control gate) of (4) at the second high potential of the first polarity, the charge carriers are: if the third electrode (source) of the access transistor (1) of the DRAM is at ground potential, Tunneling from the first electrode (drain) of the floating gate type memory device (4) to the fourth electrode (floating gate), the third access transistor (1) of the DRAM
If the electrode (source) is at a potential other than the ground potential, the charge carriers do not tunnel from the first electrode (drain) of the floating gate type memory device (4) to the fourth electrode (floating gate), and the access transistor (5) of the EEPROM. ) Is placed at a third potential of the first polarity, and the second electrode (gate) of the access transistor (5) of the EEPROM and the second electrode (control) of the floating gate type memory device (4) DRA by placing the gate) and the second electrode (gate) of the isolation transistor (3) at the fourth potential of the first polarity.
Third electrode (source) of M access transistor (1)
Potential is restored, the second electrode (gate) of the isolation transistor (3) and the second electrode (control gate) of the floating gate type memory device (4) are grounded, and the second transistor (5) of the access transistor (5) of the EEPOM is grounded. By placing the first electrode (drain) and the second electrode (gate) at the fifth high potential of the first polarity, charge carriers are transferred from the fourth electrode (floating gate) of the floating gate type memory device (4) to the first electrode (floating gate). An electrically rewritable nonvolatile dynamic random access memory cell characterized by tunneling to a drain. 2. Information can be stored as a dynamic random access memory (DRAM), and
In an electrically rewritable nonvolatile dynamic random access memory cell that can also store information as a nonvolatile memory, an electrically erasable and electrically programmable memory cell (EEPR
OM), a MOS dynamic random access memory cell (DRAM), and a MOS isolation transistor, and the EEPROM is an electrically rewritable non-volatile MO.
S floating gate type memory device (4)
And a memory device (4) having a first electrode (drain), a second electrode (control gate), a third electrode (source) and a fourth electrode (floating gate). 2 electrodes (control gate)
And a fourth electrode (floating gate) between the drain and the drain, and the access transistor (5) has a first electrode (drain), a second electrode (gate) and a third electrode (source).
A third electrode (source) is electrically coupled to the first electrode (drain) of the floating gate type memory device (4), and the MOS dynamic random access memory cell (DRAM) has a MOS access transistor (1) and The access transistor (1) has a first electrode (drain), a second electrode (gate) and a third electrode (source), and the capacitor (2) has a first electrode and a second electrode. Has and the first electrode is DR
The isolation transistor has a first electrode (drain), a second electrode (gate) and a third electrode (source) electrically connected to a third electrode (source) of the AM access transistor (1), The electrode (drain) is electrically connected to the third electrode (source) of the floating gate type memory device (4), and the third electrode (source) is DRA.
Third electrode (source) of M access transistor (1)
An electrically rewritable non-volatile dynamic random access memory cell characterized in that it is electrically connected to. 3. The second electrode (gate) of the isolation transistor (3) is electrically connected to the second electrode (control gate) of the floating gate type memory device (4). Alternatively, the nonvolatile DRAM cell according to claim 2. 4. The non-volatile according to claim 1, wherein the first electrode (drain) and the second electrode (gate) of the access transistor (5) of the EEPROM are electrically connected. DRAM cell. 5. A first electrode (drain) and a second electrode (gate) of an access transistor (5) of an EEPROM are electrically connected, and a second electrode (gate) of a separation transistor (3) and a floating gate type memory. Non-volatile DRAM cell according to claim 1 or 2, characterized in that the second electrode (control gate) of the device (4) is electrically connected. 6. Information can be stored as a dynamic random access memory (DRAM), and
In an electrically rewritable nonvolatile dynamic tendam access memory that can also store information as a nonvolatile memory, an electrically erasable and electrically programmable memory cell (EEPROM),
MOS dynamic random access memory cell (D
RAM) and MOS separation transistor, EEP
ROM electrically rewritable nonvolatile MOS floating gate type memory device (4) and MOS
A floating gate type memory device (4) comprising an access transistor (5) has a first electrode (drain), a second electrode (control gate), a third electrode (source) and a fourth electrode (floating gate), Fourth
A tunnel region is provided on a first electrode (drain) below the electrode (floating gate), the floating gate type memory device (4) having a substrate of semiconductor material and a first level patterned conductive material; A substrate of semiconductor material has a first type conductive channel region between a second type conductive first region (drain) and a second region (source) formed on the surface of the substrate, The channel region includes an in-semiconductor region capable of conducting a current between the first region (drain) and the second region (source), and the first level conductive material is substantially the first region (train) and the second region (source). ), A fourth electrode (floating gate) extending over the channel region is electrically isolated from the semiconductor substrate by the first-layer dielectric material, and is formed by the second-layer dielectric material. Electrically insulated from the second level patterned conductive material overlying the floating gate and forming the control gate, and further including a side seam-like addition having a tunnel region and a slope of conductive material. The tunnel region is partitioned into the surface of the first region (drain) of the semiconductor substrate, the side surface of the tunnel region is partitioned by the bottom of a part of the length of the side wall of the floating gate, and the dielectric of the first layer. A third layer of dielectric material thinner than the material, a side seam-like addition having a slope of conductive material is disposed along said portion of the length of the sidewall of the fourth electrode (floating gate),
The bottom surface of the seam-shaped additional portion having the inclined portion of the conductive material is in contact with the surface of the third-layer dielectric material that covers the tunnel region, and the seam-shaped additional portion constitutes the fourth electrode (floating gate). The patterned first level conductive material is electrically connected along the entire circumference of the fourth electrode (floating gate), and the MOS access transistor (5) has a first electrode (drain) and a second electrode. A MOS dynamic random access memory cell having a (gate) and a third electrode (source), the third electrode (source) being electrically connected to the first electrode (drain) of the floating gate type memory device (4). (DRAM) comprises a MOS access transistor (1) and a capacitor (2), and the MOS access transistor (1) has a first electrode. Drain), a second electrode (gate)
And a third electrode (source), the capacitor (2) has a first electrode and a second electrode, and the first electrode electrically connects to the third electrode (source) of the access transistor (1) of the DRAM. The MOS isolation transistor has a first electrode (drain), a second electrode (gate) and a third electrode (source) which are connected to each other, and the first electrode (drain) is the third electrode of the floating gate type memory device (4). Electrically connected to an electrode (source), and this third electrode (source) is electrically connected to a third electrode (source) of the access transistor (1) of the DRAM. Rewritable nonvolatile dynamic random access memory cell. 7. The memory cell of claim 6, wherein the third layer dielectric material of the floating gate type memory device has a thickness of 40 to 150 angstroms. 8. The memory cell of claim 6, wherein both the seam-like addition and the patterned first level conductive material of the floating gate type memory device are comprised of doped polycrystalline silicon. . 9. The memory cell of claim 6, wherein the second type conductivity of the floating gate type memory device is n type. 10. The memory cell of claim 6, wherein the first layer dielectric material and the third layer dielectric material of the floating gate type memory device are oxide layers. 11. The memory cell according to claim 6, wherein the conductivity of the floating gate type memory device second type is n-type and is n-type doped with polycrystalline silicon. 12. The memory cell of claim 6, wherein the first layer dielectric material of the floating gate type memory device has a thickness of 200 to 1000 angstroms. 13. A memory array having a large number of electrically rewritable non-volatile dynamic random access memory cells as defined in claim 1 or claim 6, respectively, wherein the memory cells are arranged in rows and columns of a matrix, One word line extends along each row, the gate electrode of each access transistor of the DRAMs in one row is coupled to the word line in the corresponding row, and one bit line extends along each column and one column The drain electrode of each access transistor of the DRAM is connected to the corresponding bit line, one program line extends along each two columns, and the drain electrode and gate electrode of each access transistor of the EEPROMs of both columns correspond to the program 1. Connected to the lines, one program 2 lines spread out along each 2 columns,
Gate and EEPRO of each isolation transistor in both columns
A memory array in which the control gate of each floating gate type memory device of M is connected to a corresponding program 2 line. 14. A memory array having a large number of electrically rewritable non-volatile dynamic random access memory cells as defined in claim 1 or claim 6, respectively, wherein the memory cells are arranged in rows and columns of a matrix, One word line extends along each row, the gate electrode of each access transistor of the DRAMs in one row is coupled to the word line in the corresponding row, and one bit line extends along each column and one column The drain electrode of each access transistor of the DRAM is connected to the corresponding bit line, one program 1 line extends along each two rows, and the drain electrode and gate electrode of each access transistor of the EEPROMs of both rows correspond to the program. Connected to one line, one program two lines spread out along each two lines, each line of both lines The gate of the transistor and EEP
A memory array in which the control gate of each floating gate type memory device of ROM is connected to a corresponding program 2 line.