JPH07110774A - Waiting state control system for virtual machine system - Google Patents

Abstract

PURPOSE:To prevent the actualization of defects inevitably generated in static waiting state control, to eliminate the overhead of a system and to improve the performance of a virtual machine system. CONSTITUTION:At the time of starting a guest OS on virtual machines(VMs) 112 and 113, to the entries of IE mode time measurement, waiting state time measurement and I/O interruption number of times measurement provided inside an SD, a microprogram initializes a measurement entry group, then enters an IE mode and starts the execution of the guest OS in an IE entry processing. Thereafter, the measured results are accumulated in the respective measurement entries inside the SD. A virtual machine control program(VMCP) 111 dynamically sets the value of a waiting control flag inside the SD on or off by using the contents of the measurement entry group every time an SIE is issued.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wait state control method for a virtual computer system, and more particularly to a wait state control method for a virtual computer system for controlling the wait state of the virtual computer during operation of the virtual computer of the virtual computer system. Regarding

[0002]

2. Description of the Related Art In recent years, an information processing apparatus called a virtual computer system has been realized and its use is becoming popular. The virtual computer system is to create a plurality of virtual computers under a single real computer to construct an information processing system. A virtual computer control program (hereinafter referred to as VMCP) is run on the real computer, Operating system (hereinafter referred to as OS) under the control of VMCP
Is configured to operate.

In general, as a usage pattern of a computer for configuring an information processing system, a single OS on a real computer is used.
And a method called a virtual computer (hereinafter referred to as VM or LPAR) that operates a plurality of OSs on a single real computer.

A mode in which a single OS operates on a real computer is called a basic mode, and the hardware resources of the real computer in this method are one or more central processing units (hereinafter referred to as CPU or PIP), It is composed of one shared main memory (hereinafter referred to as MS) and one or more channel paths (hereinafter referred to as CHP). The hardware resources of these real computers are treated as a single resource.

In addition, a plurality of LPARs can be installed on a single real computer.
A mode in which the OS is constructed and a plurality of OSs are operated is called an LPAR mode. Generally, a virtual computer system that realizes and configures a plurality of LPARs on a single real computer runs a program called VMCP on the real computer,
An LPAR, which is a plurality of virtual machines, is created under the control of the CP, and an independent OS is created on each of these LPARs.
Is configured to operate. Therefore, VMCP
Is added with a function of allowing each LPAR to share and use the hardware resources of a single real computer.

As a method of sharing the hardware resource of a single real computer with a plurality of LPARs, a method of allocating the hardware resource by time division under the control of VMCP, and a method of logically dividing the hardware resource A method of exclusively allocating to the LPAR, a method of allocating the above two methods in a mixed manner, and the like are known.

As a conventional technique for allocating the hardware resources of a single real computer to a plurality of LPARs as described above, for example, a publication "Enterp" issued by IBM Corporation is available.
riseSystem ／ 9000 Enterprise System ／ 3090 Processor
Resource / System Manager Planning Guide ”(GA22-7123
-08) etc. are known.

This prior art uses the former one of the above-mentioned two methods as a method of sharing the real CPU, that is, a method of allocating the real CPU to each LPAR in a time-division manner, and using the I / O channel and the MS. As a sharing method in LPAR, the latter of the above two methods, that is,
This is to use a method in which the real CHP and the real MS are logically divided and exclusively allocated to each LPAR.

A configuration example of a virtual computer system according to the prior art and its operation will be described below with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of a virtual computer system to which the present invention is applied, FIG. 7 is a diagram for explaining the configuration of a virtual computer control program used to realize the virtual computer system, and FIG. 8 is Guest OS running
Is a time chart explaining the allocation of real computer resources to the VMCP and guest OS when the VMCP intercepts when the OS enters the wait state from the operating state. Fig. 9 shows the operating guest OS enters the wait state from the operating state. Even if the VMCP is not intercepted, a time chart explaining the real computer resource allocation to the VMCP and the guest OS, FIG. 10 is a flowchart explaining the PIP processing operation when a wait state occurs in the conventional technology, and FIG. 11 is the conventional 3 is a flowchart illustrating an operation process of microprogram control when starting a virtual computer in the technology. 6 and 7, 101 is an MS, 102, 103, 2
10 is a real CPU, 111 and 220 are VMCPs, 112,
Reference numeral 113 is PARA, 121, 122, 131, 132 are logical CPUs, and 230 is a guest OS.

The virtual computer system shown in FIG. 6 is an LPA.
The real CPU is assigned to R by time division of the real CPU, and the PIPA 102 and the PIP are used as the real CPU (hereinafter referred to as PIP).
It is configured by including a real CPU having a multiprocessor configuration (hereinafter, referred to as MP configuration) by two PIPs of B103. Then, the PIPA 102 and PIPB 103
Are connected to MS 101, respectively, and P
The IPA 102 and PIPB 103 are also connected to each other.

On the PIPA 102 and PIPB 103, a VMCP 111 capable of controlling the MP configuration is operating, and two LPARs, that is, LPARA 112 and LPARB 113 are generated under the control of this VMCP. LPARA 112 and LPARB 113 are LIPAA 121, LIPAB 122 and LI, respectively.
It has an MP configuration with PBA 131 and LIPBB 132.

Therefore, the O operating on the LPARA 112
The S controls the LIPAA 121 and the LIPAB 122, and the OS operating on the LPARB 113 is LIPBA.
131 and LIPBB132 are controlled. Also, L
IPAA121 and LIPBA131 are PIPA10
2 only, LIPAB122 and LIPBB1
32 operates only on PIPB 103.

Next, referring to FIG. 7, VMCP and PIPs in the virtual computer system configured as described above.
And, the relation of the operation of the guest OS operating on each PIP will be described.

In FIG. 7, the PIP 210 runs a VMCP 220 on it and is connected to the VMCP 220 via an interface 251. The interface 251 is a normal hardware-to-software interface having the same relationship as the hardware running on the basic mode and the software running on the hardware.

The VMCP 220 controls the PIP 210,
Also, it manages allocation of hardware resources of the PIP 210 and execution control of the guest OS 230, and the interface 25
1 and PIP2 via interface 252 respectively
10 and the guest OS 230.

The guest OS 230 is a guest OS that operates on the VMCP, and V guest via the interface 252.
It is connected to the MCP 220.

The procedure for activating and operating the guest OS 230 in the above is performed as described below, and the application program of the user runs under the control of the guest OS 230.

First, the PIP 210 starts up the VMCP 220 using the normal initial program load function. After that, the VMCP 220 uses its own initial program loading function to start the guest OS 230 operating on the VM. At this time, VMCP22
0 starts and starts the guest OS 230, and thus starts the guest OS 230 via the interface 252. After that, the application program of the user runs under the control of the guest OS 230.

The VMCP 220 described above is the interface 2
In order to boot the guest OS 230 via 52, SI
The E instruction is used. The SIE instruction is a part of the IE function, and its general specification is, for example, a publication "IBM System / 370 Extended Architecture In" issued by IBM Corporation.
The details are described in "Terpretive Execution" (SA22-7095).

If any interception condition is detected while the guest OS 230 is running, the guest O
The SIE instruction being executed by S230 is intercepted,
Control is via the interface 252 to the VMCP 220
Passed to. The interception is a part of the IE function, and its general specification is described in detail in, for example, the aforementioned publications issued by IBM Corporation.

When the interception from the guest OS 230 is reported, the VMCP 220 analyzes the interception factor and executes the corresponding interception process. The interception process in this case is, for example, waiting state interception or instruction interception. In the case of waiting state interception, the guest OS 230 executes a process of passing control to the VMCP 220 via the interface 252, and in the case of instruction interception, the VMCP 220.
Performs the simulation processing of the intercepted instruction, and again executes the guest OS 2 via the interface 252.
Start 30.

When an interrupt factor for some host is detected while the guest OS 230 is running, the SIE instruction being executed is interrupted and control is performed by the interface 25.
2 to VMCP 220. VMCP220
Analyzes the interrupt factor and executes the corresponding interrupt process. The interrupt process in this case is, for example, the guest OS 2
An external interrupt that indicates the allocation time to 30 has expired, or
It is a program interrupt. If it is an external interrupt indicating that the allocation time to the guest OS 230 has expired, the VMCP 220 controls the other guest OS 2 via the interface 252.
If it is a program interrupt, the VMCP 220 performs a program interrupt simulation process and restarts the guest OS 230 via the interface 252.

Next, the handling of the guest program operating on the logical central processing unit when the guest program enters the wait state from the operating state will be described.

Generally, a program operating on the central processing unit operates in either an operating state or a wait state. The operating state is a state in which the central processing unit is sequentially executing instruction processing,
In this case, the program status word of the central processing unit (hereinafter P
The wait state control flag of SW) is set to "0". The wait state is an idle state in which the central processing unit is not executing instruction processing. In this case,
The wait state control flag of the PSW of the central processing unit is set to "1".

For general specifications of the operating state and wait state of the central processing unit, for example,
Publication "IBM Enterprise System Architectu"
The details are described in re / 390 Principles of Operation ”(SA22-7201-00).

Next, in the virtual machine control program configured as shown in FIG. 7, real machine resource allocation to VMCP and guest OS when VMCP intercepts when guest OS enters wait state from operating state This situation will be described with reference to the time chart shown in FIG.

When the guest OS is dispatched on the VMCP and is operating, as shown in FIG.
, A time-divided section 302 of real computer resources,
Section 303, section 305, and section 306 are distributed.
Then, of the sections allocated to the guest OS, the section 302
And section 305 is in the operating state, and section 3
03 and the section 306 are in a wait state.

In section 301, the VMCP 220
As a pre-processing for running the guest OS 230,
A guest OS to be dispatched is selected from a plurality of guest OS groups. The VMCP 220 is a guest OS
As a preparation for activating 230, a state description (hereinafter, referred to as SD) which is an operand of the SIE instruction is initialized in a predetermined manner. The general specifications of SD are described in detail in the aforementioned publications. And VMC
The P220 issues an SIE instruction using SD as an operand to activate the guest OS 230. At that point, PIP
The operation of 210 moves to the section 302.

In the section 302, the guest OS 230 runs as a VM in the operating state. When the guest OS 230 running on the VM turns on the wait flag in the guest PSW by an interrupt generated during instruction processing or an LPSW instruction, the PIP operation shifts to the section 303 at that point.

In the section 303, since the wait flag in the guest PSW is turned on, a wait state interception factor is detected, wait state interception occurs, and control is performed from the guest OS 230 on the VM to the VMCP 220. Will be returned. At that point, operation of PIP 210 moves to interval 304.

In section 304, the VMCP 220
The interception code that causes the control to be returned from the guest OS 230 on the VM to the VMCP 220 is analyzed, and preparations are made to perform interception processing for each code. This processing is called interception first level processing. Next, the VMCP 220 receives the second interception.
Perform level processing.

The specific processing content of this processing is that the processing corresponding to each of the various interception codes is performed separately. If the interception code indicates the wait state interception, the wait state interception is caused. Except for the guest OS, one guest OS to be dispatched is selected from a plurality of guest OS groups and activated. The illustrated example shows a case where there is no guest OS to be dispatched and the VMCP 220 is idle.

When the VMCP 220 is in the idle state, an input / output interrupt (hereinafter referred to as I / O) to the guest OS 230 which has caused the wait state interception is generated.
Interrupt), the VMCP 220 sends this I /
An O interrupt is accepted, and an I / O interrupt simulation is performed to pass this I / O interrupt to the guest OS 230. This I / O interrupt simulation processing is, specifically, a sub-hold which holds the input / output interrupt factor from the input / output interrupt parameters stored in the prefix area (hereinafter referred to as PSA) of the VMCP 220 secured in the MS. The channel is obtained, the input / output interrupt parameter corresponding to this sub-channel is stored in a predetermined position of the PSA of the VM in which the guest OS 230 is operating, and the PSW in SD at the time of interception is stored in the PS of the VM.
Store in the location of A's old PSW and then PS of the VM
After storing the data of the new PSW position of A in the PSW position of the SD of the VM, SI is used as an operand.
This is a process of issuing the E command and activating the guest OS 230 on the VM. At the end of this process, the PIP 210
The operation of moves to section 305.

In the section 305, the guest OS 230
Executes the processing for the I / O interrupt in the operating state, and subsequently executes the application program. When the wait flag in the guest PSW is turned on by the interrupt generated during the instruction processing or the LPSW instruction, the guest OS 230 running on the VM shifts the operation of the PIP 210 to the section 306.

In the section 306, the wait flag in the guest PSW is turned on, the wait state interception factor is detected, the wait state interception occurs, and the control is performed by the guest OS 2 on the VM.
Returned from 30 to VMCP 220. At that point, PI
The operation of P moves to section 307.

In the section 307, the same processing as in the section 301 is performed, and thereafter, the guest OS executes the processing by repeating the sections 301 to 306.

Next, in the virtual machine control program configured as shown in FIG. 7, even when the guest OS enters the wait state from the operating state, the VMCP
VMCP and guest O when not intercepted
The state of real computer resource allocation to S will be described with reference to the time chart shown in FIG.

When the guest OS is dispatched on the VMCP and is operating, as shown in FIG. 9, the guest OS is
, A time-divided section 402 of real computer resources,
Sections 403, 405, and 406 are distributed.
Then, of the sections allocated to the guest OS, the section 40
2, section 404 and section 406 are in the operating state, and section 403 and section 405 are in the waiting state.

In section 401, the VMCP 220
As a pre-process for running the guest OS 230, one guest OS to be dispatched is selected from a plurality of guest OS groups. The VMCP 220 is a guest OS
As a preparation for activating 230, SD, which is the operand of the SIE instruction, is initialized in a predetermined manner, the SIE instruction is issued using the SD as the operand of the SIE instruction, and the guest OS 230 is activated. At that point, PIP210
The operation of moves to section 402.

In the section 402, the guest OS 230 runs as a VM in the operating state. In the guest OS 230 running on the VM, the wait state flag in the guest PSW is turned on by an interrupt generated during instruction processing or an LPSW instruction. At that point, PI
The operation of P210 moves to section 403.

When the wait state flag in the guest PSW is turned on in the section 403, the PIP 210
The wait state is entered without transferring control to the VMCP 220. In this state, I / O to the guest OS 230
When an interrupt comes in, the PIP 210 accepts this I / O interrupt and performs I / O interrupt processing to pass the I / O interrupt to the guest OS 230. That is, the PIP 210
Specifically, the I / O interrupt parameter is stored in the PSA of the guest OS 230, the guest PSW is stored in the old PSW position of the PSA of the VM, and then the VM is stored.
Data of new PSW position of PSA of VM guest PS
A process of loading the W and activating the guest OS 230 on the VM is performed. At that point, the PIP 210 operates in section 404.
Move on to.

In the section 404, the guest OS 230
Executes a process for an I / O interrupt in the operating state, and subsequently executes an application program. And the guest OS2 running on the VM
In 30, the wait flag in the guest PSW is turned on by an interrupt generated during instruction processing or an LPSW instruction. At that point, the PIP operation moves to section 405.

When the wait state flag in the guest PSW is turned on in the section 405, the PIP 210 enters the wait state and performs the same operation as in the section 403, and when the I / O interrupt to the guest OS 230 is input, the PIP
The 210 receives this I / O interrupt, and the guest OS 23
Perform I / O interrupt processing to pass the I / O interrupt to 0. At that point, PIP operation moves to interval 406.

In section 406, guest OS 230
Performs the same processing as in the case of the section 404, and thereafter, by repeating the sections 402 to 406, the guest OS is
continue processing.

Next, the operation of the PIP when the wait state occurs will be described with reference to the flow shown in FIG. Usually, this processing is realized by a micro program, and the illustrated flow example also shows a case where the processing is realized by a micro program.

(1) When the wait state flag of PSW is set to "1", the PIP 210 causes a microprogram break-in by hardware logic,
Start the wait state processing microprogram. Microprogram break-in by hardware logic is the start address of the microprogram processing that is currently being executed when the hardware logic requires specific processing of the microprogram for some reason. Is a hardware function that starts execution from. From this step processing, the microprogram starts wait state processing (step 501).

(2) The wait state processing microprogram tests whether the PIP 210 is running in the translation execution mode (hereinafter referred to as the IE mode). Details of the IE mode are described in the aforementioned publications. If the PIP 210 is not traveling in the IE mode, the process goes to step 504 described later (step 502).

(3) PIP2 in the test of step 502
If 10 is running in IE mode, the wait state processing microprogram tests whether the wait control flag in SD is on. If the wait control flag in SD is on, the procedure goes to step 504, and if not, the procedure goes to step 505 (step 503).

(4) If the wait control flag in SD is ON in the test of step 503, the wait state processing microprogram tests whether there is a completion type interrupt factor. If there is no completion type interrupt factor, re-execute the test in this step. This state is called a wait loop state. When in this wait loop state, P
IP 210 is in a wait state. If there is a completion type interrupt factor, the wait state processing microprogram
A microprogram execution end order (hereinafter referred to as EOP) is issued to accept the completion type interrupt factor and the wait state process is completed (step 504).

(5) If the wait control flag in SD is ON in the test of step 503, the wait state processing microprogram performs wait state interception processing and passes control to VMCP. In the wait state interception process, the registers that have been operating in the IE mode up to the present are stored in SD, the IE mode is turned off, and execution is started from the instruction next to the SIE instruction. The general specification of interception processing is, for example,
It is described in detail in the aforementioned publication (step 505).

As is apparent from the above description, FIG.
The case of executing step 505 in the above is the operation of the PIP described by the time chart shown in FIG.
On the other hand, the case of executing step 504 in FIG. 10 is the PIP operation described with reference to the time chart shown in FIG.

Next, referring to the flow shown in FIG. 11, V
The processing procedure when the guest OS enters the wait state from the operating state while the guest OS is dispatched on the MCP and is operating will be described with respect to a case where the VMCP is not intercepted and a case where it is intercepted.

(1) The VMCP initializes SD, which is the operand of the SIE instruction, in a predetermined manner in preparation for starting the guest OS. At this time, the value of the wait state control flag which has already been designated from the outside is also set in SD. The value of the wait state control flag designated from the outside is a static value (step 601).

(2) The VMCP issues an SIE instruction using the SD initialized in step 601 as an operand, and activates the guest OS on the VM (step 60).
2).

(3) The guest OS runs in an operating state on the VM (step 603).

(4) The guest OS running on the VM enters the wait state from the operating state (step 604).

(5) The microprogram starts wait state processing. The wait state processing microprogram tests whether the PIP is running in IE mode, and if the PIP is running in IE mode, tests whether the wait control flag in SD is on.
In this case, the PIP is assumed to be traveling in the IE mode. If the wait control flag in SD is on, the procedure goes to step 606, and if not, the procedure goes to step 610 (step 605).

(6) If the wait control flag in SD is ON in the test of step 605, the wait state processing microprogram enters the wait loop state while testing whether there is a completion type interrupt factor. . After that, when the wait state processing microprogram detects the presence of an I / O interrupt factor which is a completion type interrupt factor as a result of the test, it issues an EOP to accept the completion type interrupt factor and cancels the wait state. (Step 606).

(7) PIP performs EOP at step 606.
Is issued, the existing I / O interrupt process is started. In the I / O interrupt processing here, the guest current PSW is stored in the old PSW area in the PSA of the guest OS, and the related I / O interrupt parameters are stored in a predetermined area in the PSA of the guest OS, and the guest This is a process of loading the data of the new PSW area in the PSA of the OS into the guest current PSW. The above-mentioned processing is performed by the I / O interrupt processing microprogram, and the PIP is switched from the wait state to the operating state by the replacement of the PSW. Therefore, the PIP processing status is step 603.
(Step 607).

(8) If the wait control flag in the SD is off in the test of step 605, the wait state processing microprogram performs wait state interception processing and passes control to VMCP. Due to the wait state interception process, the registers that have been operating in IE mode up to the present are stored in SD, and IE
After turning off the mode, execution begins at the instruction following the SIE instruction (step 610).

(9) When the control is passed by the wait state interception, the VMCP selects one VM to be dispatched next, that is, one guest OS from a plurality of VM groups. Then step 60
The other guest OS is booted by using the SIE command in the same procedure as 1. If an I / O interrupt factor for the guest OS that caused wait state interception occurs while another guest OS is being executed, the process proceeds to the next step 612 (step 611).

(10) The PIP activates the I / O interrupt process in response to the generation of the I / O interrupt factor for the guest OS that caused the wait state interception in step 611. The I / O interrupt processing here is performed by the host current P
Store SW in the old PSW area in PSA of VMCP,
Further related I / O interrupt parameters are VMCP's P
This is a process of storing in a predetermined area in the SA and loading the data of the new PSW area in the PSA of the VMCP into the guest current PSW. The above-mentioned processing is performed by the I / O interrupt processing microprogram, and by replacing this PSW,
The PIP activates the I / O interrupt process for the guest OS that caused the wait state interception (step 612).

(11) The VMCP performs an I / O interrupt simulation process in order to pass the I / O interrupt for the guest OS that has caused the wait state interception received in step 612 to the guest OS. This I
In the I / O interrupt simulation process, the guest OS
Guest current PSW in SD corresponding to
Stored in the old PSW area in A and related I / O
A process of storing the interrupt parameter in a predetermined area in the PSA of the guest OS and storing the data of the new PSW area in the PSA of the guest OS in the PSW area in SD is performed. Then, the processing from step 601 is repeated (step 613).

As described above, in the conventional wait state control, the wait control flag is provided in the SD of the SIE instruction, and it is tested whether the flag is on. If it is on, the IE mode remains as it is. If the wait loop state is entered and if it is off, a wait state interception is caused to exit the IE mode and control is passed to the VMCP. In this case, the control for turning on or off the wait control flag in the SD is performed by a command that the populator inputs from the console device of the VMCP.

The case where the wait control flag in the SD is turned on is a case where an application program having a large number of I / O interrupts is run, and for many terminal devices such as a time sharing system. It is specified when quick response is required. in this case,
Since an I / O interrupt is directly input to the guest OS, it has an advantage that the responsiveness to the I / O device is good, but on the other hand, it is in a wait loop state in the IE mode, which causes a waste of hardware resources. Will have.

The case where the wait control flag in SD is turned off is a case where an application program with a small number of I / O interrupts and a long CPU running time runs, for example, as in batch processing for scientific and technological calculations. ,
It is specified when a prompt response is not required for a limited number of I / O devices. In this case, there is an advantage in that the hardware resources are not wasted because the wait loop state is not entered in the IE mode, but on the other hand, the I / O interrupt is not directly input to the guest OS, and the input / output device is not input. It has the disadvantage of poor responsiveness.

[0068]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The control for turning on or off the weight control flag is performed by a command input from the console device of the VMCP by the operator, and only static value change can be performed. In addition, the above-mentioned conventional technique is
In the case where the wait control flag in D is turned on, it has the advantage that the response to the input / output device is good, but it has the disadvantage that the hardware resources are wasted. In the case where the switch is turned off, there is an advantage that the hardware resources are not wasted, but there is a disadvantage that the responsiveness to the input / output device of the system is poor.

For this reason, the above-mentioned conventional technique is characterized by an application program in which a large number of I / O interrupts occur.
A system in which an I / O interrupt is generated less frequently and an application program with a longer CPU running time runs at the same time, or the two types of application programs described above run in time series and the running time fluctuates. In the case of a system, the above-mentioned disadvantages are inevitably brought about, and they become apparent as system overheads, and these overheads have the problem of degrading the performance of the virtual computer system.

The object of the present invention is to solve the above-mentioned problems of the prior art, prevent the occurrence of the above-mentioned inevitable disadvantages, eliminate the system overhead due to this disadvantage, and improve the performance of the virtual computer system. It is to provide a wait state control method for a virtual computer system that can be improved.

[0071]

According to the present invention, the object is to set the wait state time and the number of I / O interrupts of the guest OS to be started in a unit of a fixed time when the VMCP starts the guest OS. As a result, VMCP dynamically sets ON or OFF of the wait control flag in SD.

That is, the purpose is to add a function of measuring the time in the IE mode, the wait state time in the IE mode and the number of I / O interrupts for the guest OS on each VM, and the measured time group is used as a parameter. As a VM
This is accomplished by dynamically setting the value of the wait control flag in SD, which is accompanied with it, to ON or OFF each time the CP issues an SIE instruction.

[0073]

According to the wait state control method of the virtual computer system according to the present invention, the IE mode time measurement entry, the wait state time measurement entry, and the I / O interrupt are stored in SD, which is the operand of the SIE instruction for activating the guest OS on the VM. A count measurement entry is provided. And SIE
During the instruction entry processing, the entry processing microprogram initializes these measurement entry groups and then enters the IE mode to start the execution of the guest OS.

After that, when the guest OS enters the wait state, the wait state processing microprogram starts measuring the wait state time, and when exiting the wait state, stops measuring the wait state time and waits for the measured wait time. The state time is accumulated in the wait state time measurement entry in SD. Similarly, when the guest OS receives the I / O interrupt, the I / O interrupt processing microprogram counts up the I / O interrupt count measurement entry in the SD. Further, in the exit processing of the SIE instruction, the exit processing microprogram accumulates the IE mode time in the IE mode time measurement entry.

The present invention uses the contents of the IE mode time measurement entry, wait state time measurement entry, and I / O interrupt count measurement entry obtained by the above-described procedure, each time the VMCP issues an SIE instruction, The value of the wait control flag in the SD of the SIE instruction can be dynamically set to on or off, and as a result, it is possible to prevent the inconvenience of the inevitable occurrence in the static wait state control.
Since the system overhead caused by this disadvantage can be eliminated, the performance of the virtual computer system can be greatly improved.

[0076]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a wait state control system for a virtual computer system according to the present invention will be described in detail below with reference to the drawings. The virtual computer system to which the present invention is applied has the same configuration as described with reference to FIG. 6, and its program configuration is the same as that described with reference to FIG.

FIGS. 1 to 4 are flowcharts for explaining the processing operation of the microprogram for realizing the wait state control method of the virtual computer system according to the present invention.
Is a flow chart for explaining the processing operation of the entry processing of the SIE instruction (hereinafter referred to as IE entry processing), and FIG.
FIG. 3 is a flowchart for explaining the processing operation when the wait state bit of SW is set to “1” and a wait state breakin is generated.
FIG. 4 is a flowchart for explaining the processing operation when the O interrupt is generated, and FIG. 4 is a flowchart for explaining the processing operation of the exit processing of the SIE instruction (hereinafter referred to as IE exit processing). FIG. 5 is a flow chart for explaining the processing operation of VMCP according to the embodiment of the present invention.

First, referring to the flow shown in FIG.
E instruction entry processing (hereinafter referred to as IE entry processing)
The processing operation of the microprogram for performing will be described.

(1) When the SIE instruction is issued, its S
IE entry processing is performed as part of the execution of the IE instruction. The processing performed here is a characteristic processing of the present invention, and the IE time measurement entry set in the SD,
This is a process of initializing the wait time measurement entry and the I / O interrupt count measurement entry to zero. These measurement entries are used in each processing step described later (step 711).

(2) After completion of the above-mentioned initialization processing, the microprogram processing similar to the IE entry processing in the case of the conventional technique is executed. This processing is, for example, various validity checks, loading of guest execution parameters specified by SD into the guest hardware register, and switching of the processing mode to the IE mode. Finally, the EOP is issued to start the guest OS.

Next, referring to the flow shown in FIG.
The processing operation of the microprogram when the wait state bit of W is set to "1" and the wait state breakin is generated will be described.

(1) When the wait state flag of the PSW is set to "1", the PIP causes the microprogram break-in by the hardware logic and activates the wait state processing microprogram. And P
It is tested whether the IP is operating in IE mode. Then, if the PIP is not operating in the IE mode, the process proceeds to step 724, and if it is operating in the IE mode, the process proceeds to step 722 (step 721).

(2) If it is determined in step 721 that the PIP is running in the IE mode, the wait state processing microprogram tests whether the wait control flag in SD is on. If the wait control flag in SD is turned on, the procedure proceeds to step 723, and if not, the procedure proceeds to step 727 (step 722).

(3) If it is determined in step 722 that the wait control flag is ON, that is, PIP is IE
If the mode is running and the wait control flag in SD is running, the wait state processing microprogram starts measuring the wait state time (step 72).
3).

(4) After the processing of step 723 is completed, or when the PIP is not operating in the IE mode in the test of step 721, the wait state processing microprogram tests whether there is a completion type interrupt factor. Then
If there is no completion type interrupt factor, this test is re-executed repeatedly. As a result, the wait loop state is entered (step 724).

(5) If there is a completion type interrupt factor in the test of step 724, the wait state processing microprogram tests whether the PIP is operating in the IE mode. If the PIP is not operating in IE mode, the wait state processing microprogram issues an EOP to accept the completion type interrupt factor and completes the wait state processing (step 725).

(6) If the PIP is operating in the IE mode in the test of step 725, that is, if the PIP is IE
If the mode is running and the wait control flag in SD is running, the wait state processing microprogram stops measuring the wait state time, and the obtained wait state time is the content of the wait time measurement entry in SD. Add to. As a result, the elapsed time in the wait state is accumulated in the wait time measurement entry in SD. afterwards,
Since the wait state processing microprogram accepts a completion type interrupt factor, it issues an EOP to complete the wait state processing (step 726).

(7) When the wait control flag is determined to be off in the test of step 722, that is, PIP
However, if the vehicle is running in the IE mode and the wait control flag in SD is off, the wait state processing microprogram performs wait state interception processing and passes control to VMCP. In the wait state interception process, the registers that have been operating in the IE mode up to the present are stored in SD, the IE mode is turned off, and execution is started from the instruction next to the SIE instruction. Details of this process will be described later with reference to FIG. 4 (step 727).

Next, the processing operation of the microprogram when an I / O interrupt is generated for the guest OS will be described with reference to the flow shown in FIG.

(1) When an I / O interrupt is generated for the guest OS, the PIP initiates a microprogram break-in by hardware logic and activates an I / O interrupt processing microprogram for the guest OS. Then, the PIP is operating in the IE mode and tests whether it is an I / O interrupt for the VM currently being dispatched. If it is not an I / O interrupt for the currently dispatched VM, go to step 734 and execute I / O for the currently dispatched VM.
If it is an interrupt, go to step 732 (step 73).
1).

(2) If the I / O interrupt for the VM currently dispatched in the test in step 731 is an I / O interrupt processing microprogram, the I / O interrupt count measurement entry in the SD stores "1". Is added to count up this entry (step 732).

(3) I / O interrupt processing The microprogram directly executes I / O interrupt processing for the guest OS. In the I / O interrupt processing here, the guest current PSW is stored in the old PSW area in the PSA of the guest OS, and the related I / O interrupt parameters are stored in the guest OS PSW.
This is a process of storing in a predetermined area in the SA and loading the data of the new PSW area in the PSA of the guest OS into the guest current PSW. After that, EOP is issued and the guest OS I
The / O interrupt handler is activated (step 733).

(4) If the test in step 731 was not an I / O interrupt for the VM currently dispatched, the I / O interrupt processing microprogram determines
Perform exit processing. In the IE exit processing, the registers that have been operating in the IE mode up to the present are stored in SD, and the IE mode is turned off. The IE exit process will be described in detail later with reference to FIG. 4 (step 734).

(5) The PIP activates I / O interrupt processing. The I / O interrupt processing here stores the host current PSW in the old PSW area in the VMCP PSA, and further stores the related I / O interrupt parameters in a predetermined area in the VMCP PSA, and then stores the VMCP PSA. New PS in
This is a process of loading the data in the W area into the guest present PSW. The above-described processing is performed by the I / O interrupt processing microprogram, and the I / O interrupt handler of the VMCP is activated by this PSW replacement.

Next, referring to the flow shown in FIG. 4, SI
The microprogram processing operation of E instruction exit processing (hereinafter referred to as IE exit processing) will be described.

(1) When an interception or a host interrupt occurs in the IE mode, the IE exit process is executed as a part of the execution of the SIE instruction. The processing performed here is a characteristic processing of the present invention. The IE mode time measured up to that point is accumulated in the IE time measurement entry set in the SD, and the guest wait state is entered. When it comes, it is a process of accumulating the elapsed time of the wait state in the wait time measurement entry in SD. When the entry is not made from the wait state of the guest, the wait time elapsed time is not accumulated in the wait time measurement entry in the SD. I in SD
Since the / O interrupt count measurement entry has already been updated, update processing is not performed in this step (step 741).

(2) The registers up to the present time, which have been operating in the IE mode, are stored in SD, the host execution parameters are loaded into the host hardware register, and then the IE mode is turned off (step 742). .

By executing the processing procedure of the microprogram according to the flow of FIGS. 1 to 4 described above, the SIE
IE time measurement entry set in SD of instruction,
Each of the wait time measurement entry and the I / O interrupt count measurement entry is measured.

Next, the operation of the wait state control according to the embodiment of the present invention will be described with reference to the flow shown in FIG. The wait state control according to the embodiment of the present invention is shown in FIG.
The process step described below has been added to the process described in step 601 described as the related art in 1 in which the VMCP initializes SD, which is the operand of the SIE instruction, in a predetermined manner in preparation for starting the guest OS. It is a thing. In addition, here, VMC
A control method for dynamically setting the value of the wait control flag in the SD that is additionally initialized to ON or OFF each time P issues an SIE will be described.

(1) First, the VMCP is the S of the SIE instruction.
It is tested whether the setting mode of the wait control flag in D is the automatic setting mode. If it is the automatic setting mode, go to step 820. If it is not the automatic setting mode, go to step 850. Here, the automatic setting mode of the weight control flag in the SD is a characteristic mode of the present invention, in which the VMCP monitors the running state of the VM to turn on or off the weight control flag in the SD by an operator intervention. This mode is set to None. A mode in which the wait control flag in SD is not the automatic setting mode is a mode in which the value of the wait state control flag designated from the outside is set in SD as it is, and is called a manual setting mode. The manual setting mode has the same function as in the conventional technique (step 810).

(2) If the setting mode of the wait control flag in SD is the automatic setting mode in the test of step 810, VMCP indicates the unit time of the IE mode time until now corresponding to the VM to be dispatched. (Hereinafter referred to as IETIME) is taken out from the table managed by VMCP. IETIME refers to IE mode time during any real time interval. Next, VMCP
Retrieves the unit time of the wait time in the IE mode up to the present (hereinafter referred to as IEWAITTIME) corresponding to the VM from the table managed by the VMCP. I
EWAITIME indicates a wait time between arbitrary real time intervals. Furthermore, the VMCP indicates the unit number of I / O interrupts in the IE mode up to the present (hereinafter, referred to as IEIOCNT) corresponding to the VM as VMCP.
Retrieved from the table managed by. IEIOCNT indicates the number of I / O interrupts during an arbitrary real time interval.
The aforementioned IETIME, IEWAITIME and IEIO
All ICNTs are created by VMCP from the parameter group obtained by the microprogram processing procedure described with reference to FIGS. The arbitrary real time intervals are all set with the same timing and interval (step 820).

(3) VMCP multiplies IEWAITTIME by 100 and divides the product by IETIME. Then, the resultant quotient (hereinafter referred to as WAITRATE) is compared with the threshold value of the weight ratio (hereinafter referred to as WAITLMT) set in the system in advance. WAI
If RATE is greater than WAITLMT Step 8
Go to 40. If WAITRATE is less than or equal to WAITLMT, go to step 870 (step 83).
0).

(4) VMCP divides IEWAITTIME by IEIOCNT. And the resulting quotient (below,
IOIRATE) and an I / O interrupt rate threshold value (hereinafter referred to as IOILM) preset in the system.
(T). IOIRATE is IOILM
If smaller than T, go to step 860. IOIRAT
If E is greater than or equal to IOILMT, step 870.
(Step 840).

(5) If the setting mode of the wait control flag in SD is not the automatic setting mode in the step 810 of the destination, that is, if the wait control flag in SD is the manual setting mode, VMCP is designated from the outside. In order to set the value of the wait state control flag that has been set to the wait control flag in the SD as it is, the value of the wait state control flag is tested by testing whether the value of the wait state control flag specified from the outside is on. When is ON, the process goes to step 860, and when the value of the wait state control flag is OFF, the process goes to step 870 (step 850).

(6) In steps 830 and 840, the WAI
RATE is greater than WAITLMT and IOI
If RATE is smaller than IOILMT, and if the value of the wait state control flag designated externally in step 850 is ON, the VMCP sets the wait control flag in SD to "1" (step 860).

(7) In steps 830 and 840, the WAI
If RATE is equal to or less than WAITLMT, or if IOREATE is equal to or greater than IOILMT, and if the value of the wait state control flag externally specified in step 850 is OFF, VMCP
Sets the wait control flag in SD to "0" (step 870).

(8) After the processing of steps 860 and 870 is completed, the VMCP issues the SIE instruction with the SD of the SIE instruction initialized by the processing of steps 810 to 870 as an operand, and the guest O on the VM.
Start S. With this, after that, guest O on VM
S runs (step 880).

In the processing in the wait control flag automatic setting mode described above, WAITRATE is set to WAITLM.
If it is larger than T and IOIRATE is smaller than IOILMT, the wait control flag in SD is set to "1".
However, the present invention is not limited to the WAITR.
If ATE is greater than WAITLMT, or I
The wait control flag in SD may be set to "1" when either one of the conditions when OIRATE is smaller than IOILMT is satisfied.

In addition, IETIME and IEWAITIM as parameters used to set the above-mentioned wait control flag in SD to "0" or "1".
The values of the parameters that are the bases for creating E and IEIOCNT may be determined by a method input by an operator from the outside, or may be determined by a method internally created by VMCP under a certain algorithm. Further, it may be determined by a method in which the above two methods are used in combination.

In the above-described embodiment of the present invention, when the wait control flag in SD is set to "0" or "1", IETIME indicating an IE mode time during an arbitrary real time interval, an arbitrary A parameter indicating the running state of the guest OS at that time, ie, IEWAITTIME indicating the wait time between the real time intervals, and IEIOCNT indicating the unit number of I / O interrupts in the IE mode up to the present corresponding to the VM. The value to be set in the wait control flag in the SD can be dynamically determined based on the relationship between the values of this parameter.

As a result, according to the embodiment of the present invention, in comparison with the prior art in which only a static value change can be performed, hardware resources are saved in the case where the wait control flag in SD is turned on. It is possible to correct the problem of waste, and to correct the problem of poor response to the input / output device when the wait control flag in the SD is turned off. As a result, one embodiment of the present invention can prevent the inconvenience that naturally occurs in the static wait state control from manifesting itself, and can eliminate the system overhead caused by this inconvenience, thus significantly reducing the size of the virtual computer system. It is possible to improve various performances.

[0112]

As described above, according to the present invention, V
Each time the MCP issues an SIE, the running state of the VM can be reflected and the value of the wait control flag in SD can be dynamically set to on or off. As a result, inevitably in the static wait state control. It is possible to prevent the occurrence of the disadvantages caused by the above, remove the system overhead caused by these disadvantages, and improve the performance of the virtual computer system significantly.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a processing operation of entry processing of an SIE instruction according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation when a wait state bit of PSW is set to “1” and a wait state break-in is generated in the embodiment of the present invention.

FIG. 3 is a flowchart illustrating a processing operation when an I / O interrupt is generated for a guest OS according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating a processing operation of an exit process of an SIE instruction according to the present invention.

FIG. 5 is a flowchart illustrating a VMCP processing operation according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a virtual computer system to which the present invention is applied.

FIG. 7 is a diagram illustrating a configuration of a virtual computer control program used to realize a virtual computer system.

FIG. 8 is a time chart illustrating allocation of real computer resources to a VMCP and guest OSs when an operating guest OS is intercepted by a VMCP when the operating OS enters a wait state.

FIG. 9 is a time chart for explaining allocation of real computer resources to VMCP and guest OS when the operating guest OS does not cause VMCP to intercept even if it enters a wait state from the operating state.

FIG. 10 is a flowchart illustrating a PIP processing operation when a wait state occurs in the conventional technique.

FIG. 11 is a flowchart illustrating an operation process of microprogram control when a virtual machine is started up in a conventional technique.

[Explanation of symbols]

101 main storage device (MS) 102, 103, 210 real CPU 111, 220 virtual computer control program (VMC)
P) 112, 113 Virtual machine (PARA) 121, 122, 131, 132 Logical CPU 230 Guest operating system (guest O
S)

Claims (3)

[Claims] 1. A plurality of logical central processing units are constructed on the central processing unit by a virtual computer control program, comprising at least one central processing unit and a main storage unit connected to the central processing unit. And has a function of switching between the wait state of the guest program being continued as it is or the virtual computer control program intercepting it when the guest program operating on the logical central processing unit enters the wait state from the operating state. In the virtual machine system, the logical central value is set by using one or both of a ratio of an operating state time of a guest program and a wait state time and the number of input / output interrupts to the guest program occurring during the wait state of the guest program. On the processor When the operating guest program enters the wait state from the operating state, the function to switch the wait state of the guest program as it is or to intercept it to the virtual machine control program is dynamically turned on or off. Wait state control method for virtual computer system. 2. A wait processing part of a microprogram and its associated hardware installed in the central processing unit measures the operating state time and wait state time of the guest program and waits for the guest program with respect to the parameters. 2. The wait state control method for a virtual computer system according to claim 1, wherein the number of input / output interrupts to the guest program generated during the state is measured. 3. A function for switching whether the guest program operating on the logical central processing unit is allowed to continue the wait state of the guest program or to be intercepted by the virtual computer control program when the guest program enters the wait state from the operating state. 3. The wait state control method for a virtual computer system according to claim 1, further comprising a control mode that is statically turned on or off.