JPH07110066B2 - Digital electronic still camera - Google Patents

Description

TECHNICAL FIELD The present invention relates to an electronic still camera, and more particularly to a digital electronic still camera that stores a video signal representing a still image in the form of digital data in a storage device.

BACKGROUND ART For example, in an electronic still camera described in JP-A-59-183592, a memory is detachably connected to a camera body having an image pickup optical system and a solid-state image pickup device, and a video signal representing a still image picked up by the image pickup device is transmitted. It is stored in this memory in the form of digital signals. The memory in which the video signal is stored is removed from the electronic still camera and loaded into the reproducing device, and the video signal read from the memory by the reproducing device is reproduced as a visible image on the screen of the video monitor.

In general, the solid-state imaging device mounted on a camera has a color filter having a pixel arrangement and spectral transmittance unique to each device. For example, a combination of pixel arrays of cyan (Cy), magenta (M), yellow (Ye) and green (G), a combination of pixel arrays of red (R), green (G) and blue (B), Cy, There are many combinations of W (white), Ye, and G pixel arrays, and the arrays are different for each pixel, and pixels of the same color are arrayed in the vertical direction of the screen. .

Therefore, in the above-mentioned Japanese Laid-Open Patent Publication, color separation information that defines the pixel arrangement and spectral characteristics of the solid-state imaging device mounted on the camera is stored in the memory together with the video signal in the form of a code each time one image is captured by the camera. It has a memorizing method. The reproducing apparatus is provided with a color separation processing program corresponding to the type of solid-state imaging device in order to perform appropriate color separation of video signals. This is the relative positional relationship between the pixel array of the image pickup cell array used in the camera and the segment array of the color filter, the phase relationship between the drive timing of the image pickup device, the drive timing of the analog-digital converter and the write timing of the memory. This is because the pixel signal of the correct color cannot be reproduced when the video signal is reproduced by the reproducing apparatus unless the above is specified correctly. In view of this, in the Japanese Patent Laid-Open Publication No. Sho, when a video signal is read from a memory and an image is reproduced, a color separation processing program suitable for the image is accessed from the color separation information of the image, and color separation processing is performed according to the program. .

However, there are many types of image pickup devices, and in order to configure the playback device so that it can properly play back video signals shot by digital electronic still cameras of all types, it is necessary to use colors that are compatible with these various types of image pickup devices. It is necessary to store the separation processing program in the memory of the playback device.
Providing a variety of color separation processing programs requires a large capacity memory for the reproducing apparatus, which complicates the configuration and increases the price. The type of imaging device tends to increase further, and it will be more and more difficult for the reproducing apparatus to deal with all of them.

In order to solve such a problem, it is conceivable to store a video signal in the form of a component signal in a memory from a digital electronic still camera. However, since the amount of data in the form of component signals is large, there is a problem that the memory requires a large capacity.

Aim The present invention provides a digital electronic still camera that does not impose a burden on the video signal processing in the reproducing apparatus due to the difference in the type of the solid-state imaging device as in the prior art and can reduce the memory capacity. The purpose is to

DISCLOSURE OF THE INVENTION According to the present invention, a digital electronic still camera, in which a color image signal representing a still image is stored in a semiconductor memory device in the form of digital data, has an image pickup device, and picks up an image of a field to capture an object. An image pickup means for outputting a color image signal representing a field in a dot sequential manner, a signal processing means for converting a color image signal output from the image pickup means into a component signal and outputting the component signal in the form of a digital signal, and an output from the signal processing means. The data compression means for compressing the component signal to be output and outputting it to the semiconductor memory device, and the image pickup means, the signal processing means and the data compression means are controlled so that the image pickup means performs the image pickup, and the signal processing means converts the component signal into the component signal. And the data compression means to perform the data compression of the component signal and the writing to the semiconductor memory device. Control means for supplying a control signal for

In this specification, the term “component signal” is used.
Is used in a concept opposite to a composite video signal, that is, a composite signal, and may take the form of, for example, three primary color signals, or may take the form of a luminance signal and a color difference signal.
Of course, even if these signals are point (pixel) sequential signals,
Alternatively, a line-sequential signal may be used.

Description of Embodiments Embodiments of a digital electronic still camera according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown an embodiment of a digital electronic still camera according to the present invention, which is a camera 10 having an image pickup section 12 and a memory 90 detachably connected thereto via a connector 14. Have and. In the figure, the element portion on the left side of the connector 14 is mounted in a single housing as a digital electronic still camera.

The memory 90 is, for example, an SRAM semiconductor memory integrated circuit (I
C) A rewritable digital storage device mounted in the form of a “module” such as a card or a cartridge, and has a data input / output line 92, an address, and a read / write line.
Control lines 94, including write enable, chip select, strobe, clock, etc., are connected to camera 10 via connector 14. The connector 14 may have a power supply line for the memory 90. In the memory 90, for example, when an image of one frame is represented by 1 M to 1.5 M bits of data, an SRAM having a storage capacity of 16 M bits per chip will realize a storage device for taking 24 frames with two chips.

The imaging unit 12 is necessary for capturing a still image such as an imaging lens 16, an aperture stop 18, a shutter 20, an imaging device 22, a photometry / distance measurement mechanism, a viewfinder (not shown) and their drive mechanism as shown in the figure. Has an element, the focus of the imaging lens 16,
Control of the diaphragm 18 and opening / closing of the shutter 20 are controlled by the control circuit 24 via a control line 26. As the imaging device 22, for example, a solid-state imaging device such as CCD or MOS, or an imaging tube is advantageously applied. In the case of a solid-state image pickup device, a color filter 28 is attached to the image cell array at that time, and a video signal color-modulated in response to a clock received from the synchronization generation circuit 30 through the drive line 32 is sequentially output to the output 34 in a dot (pixel) sequence. Output at. An appropriate color segment array is used for the color filter 28.

The video signal output 34 of the imaging device 22 is connected to the input of an analog-digital converter (ADC) 36, which converts the analog-format video signal of the input 34 into corresponding digital data of 8 bits, for example. Then, it is a signal conversion circuit that outputs the output 38. Output 38 is signal processing circuit 40
Connected to the input of. As will be described later in detail, the signal processing circuit 40 separates the video signal of the input 38 into RGB color signals, and performs necessary video signal processing such as white balance adjustment and gradation (γ) correction on it. After that, it outputs to the output 42 or further the luminance signal Y and the color difference signal R-
It is a video signal processing circuit which forms Y and BY and outputs them to the output 42. The output 42 is connected to the input of the band compression circuit 80.

The band compression circuit 80 is a data compression circuit that data-compresses the color signal RGB or the luminance signal Y of the input 42 and the color-difference signals R-Y and B-Y and outputs the data to the output 82 thereof. Band compression circuit
As a data compression method performed in 80, one or more of orthogonal transform coding, adaptive coding, DPCM, predictive coding, block coding, vector quantization, and the like are used. The output 82 of the band compression circuit 80 is connected to the connector 14 of the device.

The control circuit 24 is a control function unit that controls the operation of the entire apparatus in response to an instruction signal from the operation display unit 44 through the signal line 52, and the control signal is transmitted via the control line 46 to the synchronization generation circuit 30. , The analog-to-digital converter 36 via the control line 48, the signal processing circuit 40 via the control line 50, and the band compression circuit 80 via the control line 84. It is connected to the. The control circuit 24 also monitors the condition of each part of the apparatus by these control lines 46, 26, 48, 50, 84.

The control circuit 24 also has the function of controlling mainly the writing of the memory 90, and includes control lines 54 including its write address, write enable, chip select and clock.
Is connected to connector 14.

The synchronization generating circuit 30 is controlled from the control circuit 24 through the control line 46, and outputs to the output 32 a drive signal such as a clock or an address necessary to drive the imaging device 22 and output a video signal from its output 34. It is a synchronizing signal generating circuit for outputting.

The operation display unit 44 has a shutter release button and various manual operation buttons such as automatic / manual setting, exposure setting, white balance adjustment, etc., for inputting an operator's instruction to the apparatus, and this is input by a signal line 52. It has a function of giving to the control circuit 24 and a display function of receiving a signal from the control circuit 24 from the signal line 52 to show the signal to the operator.

As the signal processing circuit 40, for example, as shown in FIG. 9, the one having a color separation unit 100, a white balance adjustment unit 102, and a γ correction unit 104 is advantageously applied. The input 38 is connected to the color separation unit 100. The color separation unit 100 converts the dot-sequential video signal obtained at the input 38 into respective color signals, for example, red (R), green (G) and blue (B) according to a pixel clock received from the control circuit 24 through the control line 50. It is in the functional part that separates. This color separation is performed according to the arrangement of the filter segments of the color filter 28 of the image pickup device 22. The arrangement of the filter segments can be any.

This color-separated color signal is then sent to the white balance adjustment unit 102.
Entered in. The white balance adjusting unit 102 is a functional unit that responds to the control line 50 from the control circuit 24 and corrects the deviation of the white balance due to the color temperature of the light source when the image is captured by the imaging device 22. The color signal whose white balance has been
Entered in 4. The γ correction unit 104 is a functional unit that corrects a shift in gradation due to the non-linear characteristics of the imaging device 22.
The output of the γ correction unit 104 is connected to the output 42 of the signal processing circuit 40.

FIG. 10 shows another configuration example of the signal processing circuit 40. This configuration example is different from the configuration of FIG. 9 in that a matrix 106 is further arranged between the output of the γ correction unit 104 and the circuit output 42 in the configuration example shown in FIG. The matrix 106 outputs three signals from the color signals R, G, B obtained from the γ correction unit 104 to the luminance signal Y and the color difference signals RY, BY.
2 is a signal forming function unit that outputs each to 2. Therefore, the luminance signal Y and the color difference signals RY and BY are output to the output 42 of the signal processing circuit 40.

The signal processing circuit 40 shown in FIG. 9 and FIG. 10 may be configured by a digital processor system, for example, to process digital color signals, but it may also be an analog arithmetic circuit for processing analog color signals. It may be any of the above. Such signal processing circuit
40 is advantageously implemented, for example, on a single integrated circuit chip. When applied to the signal processing circuit 40 in the embodiment shown in FIG. 1, the one realized by a digital processing system is applied.

The band compression circuit 80, for example, in the case of performing data compression by orthogonal transform coding, as shown in FIG.
Blocking circuit 142, orthogonal transformation circuit 144, coding circuit 146
Those with are advantageously applied. Blocking circuit 142
Input 42 is connected to. The blocking circuit 142 converts the RGB signal or Y, RY, BY signal of its input 42 into
Each block is divided into a predetermined number of blocks.

Blocking can be performed by, for example, displaying an image 260 as shown in FIG. 16A.
It is divided into a plurality of regions 262, 262, 262, ..., That is, blocks as shown in FIG. 16B. One block 262 shown in FIG. 16B is preferably composed of, for example, 16 × 16 = 256 pixels, but it may be a block composed of a predetermined number of pixels according to the number of pixels forming the image signal. Good.

The image signal of each pixel that is blocked by the blocking circuit 142 is input to the orthogonal transformation circuit 144 through the signal line 150. The orthogonal transform circuit 144 performs an orthogonal transform on each block of the pixel signal that has been divided into blocks. The pixel signal of each block has the value of the level of each pixel before the orthogonal transformation, as shown in FIG. 17A, for example. In the example of the figure, the uppermost leftmost pixel has a level of 120 in digital data, the rightmost pixel thereof has a level of 127, the third pixel has a level of 108, and the second pixel from the top. The leftmost pixel in the is 107 levels, the rightmost pixel is 1
There are 20 levels.

By orthogonally transforming this, for example, data as shown in FIG. 17B is obtained. As the orthogonal transform, the Hadamard transform,
Cosine transform, Fourier transform, etc. are known. In the data as shown in FIG. 17B which has been subjected to the orthogonal transformation, the horizontal axis corresponds to the horizontal frequency component of the original screen, and the vertical axis corresponds to the vertical frequency component of the original screen. Further, in the data array, the data of the low frequency component is arranged toward the upper left, and the data of the high frequency component, that is, the data having a large difference value with the adjacent pixel is arranged toward the right or the lower side.

As described above, in general images, the low-frequency component occupies a large component in terms of electric power, and the high-frequency component appears only in a small component. A large value appears in the section, and decreases toward the right and downward.

The signal subjected to the orthogonal transformation in the orthogonal transformation circuit 144 is sent to the coding circuit 146 through the signal line 152, and the coding circuit 146
Is encoded in. The encoding is performed by assigning a predetermined number of bits to each piece of matrix data as shown in FIG. 17B. For example, the number of bits as shown in FIG. 17C is allocated, 8 bits are assigned to the data 200 of FIG.
6 bits for 0, 130, 150, data 100, 90, 40, 70,
4 bits for 80, data 50, 50, 10, 5, 10, 60, 20
2 bits are assigned to each of these, and these data are encoded. The number of bits is not assigned to the data arranged to the right and below the data. That is, in the data after the orthogonal transformation, the data arranged to the right or below the predetermined range is ignored and is not stored.

The reason why only such low frequency components are stored and the high frequency components are ignored is that, in a general image, most of the low frequency components are low frequency components, so even if the high frequency components are ignored, the image can be generally reproduced. is there.

Output 82 of data encoded in the encoding circuit 146
Are connected to the connector 14.

The operation will be described. Memory 90 to camera by connector 14
The camera is attached to 10, and the operation display unit 44 is operated to perform the shooting operation of the subject. The one-frame subject image captured by the image capturing device 22 by opening the shutter 20 by operating the shutter release button is output from the image capturing device 22 in accordance with the clock supplied from the synchronization generating circuit 30 through the clock line 32.
It is output in the form of a dot-sequential video signal to 34.

The control circuit 24 energizes the analog / digital converter 36 and the signal processing circuit 40 in accordance with the synchronization signal generated by the synchronization generation circuit 30. Then, the dot-sequential video signal is converted into corresponding digital data by the analog / digital converter 36 and input to the signal processing circuit 40. Signal processing circuit
In 40, the color separation unit 100 separates RGB color signals, the white balance adjustment unit 102 adjusts the white balance, and the γ correction unit 104 performs γ correction. The video signal thus subjected to various signal processing is output to the output 42 in the form of color signal R, G, B or luminance signal Y, color difference signal RY, BY data, that is, in the form of component signal data. To be done.

The band compression circuit 80 blocks the component signal input from the input 42 by the control signal from the control circuit 24 in the blocking circuit 142, orthogonally transforms it in the orthogonal transformation circuit 144, encodes it in the encoding circuit 146, and outputs it. 82
Output to.

The control circuit 24 outputs control signals such as a write address, write enable, chip select and clock to the memory 90 through the control line 54. In sync with this, the memory
Video signals input to the data line 92 are sequentially written in 90 sequential storage positions. In this way, the video-compressed video signal data of one frame of image is stored in the storage area of the memory 90 in the form of component signal data.

When the video signal stored in the memory 90 in the device of this embodiment is stored in the form of, for example, an RGB color signal, the first
Reproduction is performed by the reproduction device 120 having the configuration illustrated in FIG. The reproducing device 120 has a connector 122 to which the memory 90 is detachably connected, so that its read data line 96 can be connected.
Are connected to the band compression / decoding circuit 86.

The band compression / decoding circuit 86 is a band compression circuit 80 of the apparatus of FIG.
This is a circuit for returning the data compressed in step S1 to the original data. When the data compression is performed by the orthogonal transformation, the band compression decoding circuit 86 preferably includes the decoding circuit 164, the orthogonal inverse transformation circuit 166, and the block synthesis circuit 168 as shown in FIG. To be done. The decoding circuit 164 restores the input data as shown in FIG. 17C to data as shown in FIG. 17B and outputs it to the orthogonal inverse transform circuit 166, and the orthogonal inverse transform circuit 1
66 performs orthogonal inverse transformation on this to return it to the data shown in FIG. 17A. The block synthesis circuit 168 synthesizes the block data into the original data for one screen and outputs it to the output 160.

The output 160 of the band compression / decoding circuit 86 is connected to the matrix 126 via the digital-analog converter (DAC) 124. Further, the control line is connected to the control circuit 128 via the control line 162.

When the output 160 of the component video signal data from the band compression / decoding circuit 86 is an RGB signal, it is converted into an analog signal by the digital / analog converter 124, and the matrix 126 outputs the luminance signal Y and the color difference signal RY. , BY
Is converted to. This is input to the encoder 130, converted into a composite video signal, and output to the device output 132.

If the component video signals from the band compression / decoding circuit 86 are Y, RY, and BY signals, the matrix 12
6 is omitted and the output from the DA converter 124 is directly encoded by the encoder 13
You can enter 0.

An image output device such as a video monitor 134 and / or a printer is connected to the device output 132, whereby the composite video signal of the output 132 is output as a visible image.

Each element of the reproducing device 120 is controlled by the control circuit 128. The control circuit 128 supplies a control signal for reading to the control line 94 of the memory 90 according to a predetermined fundamental frequency in response to an instruction from the operator input from the operation display unit 136. As a result, the video signal data of the designated frame is read from the memory 90. Since this video signal data is in the form of a component signal, for example, an RGB color signal, it is decoded into data before compression by the band compression / decoding circuit 86, and thereafter, by the video signal processing circuit including the matrix 126 and the encoder 130. Converted to composite video signal and output 132
Is output from. As a result, the image represented by the video signal is visually displayed on the video monitor 134.

According to the present embodiment, the video signal is thus stored in the memory in the standard signal format as the RGB signal or the Y, RY, BY signal. Therefore, in the reproducing apparatus, it is possible to appropriately reproduce the image without performing signal processing such as color separation depending on the type of the imaging device.

Therefore, there is no need for various types of color separation processing programs corresponding to various types of imaging devices, which are required in the conventional reproducing apparatus, and the configuration including the memory of the reproducing apparatus is simplified. That is, there is no increase in the load of video signal processing in the reproducing apparatus due to the difference in the type of solid-state imaging device.

In addition, since the band compression circuit 80 performs data compression such as orthogonal transformation on the RGB signal or the Y, RY, and BY signals, the data amount of the signal can be reduced, and as described above. The memory capacity can be reduced despite the storage in the form of component signals.

In another embodiment of the digital electronic still camera according to the present invention shown in FIG. 2, a switch circuit 56 is connected to three outputs 42 of a signal processing circuit 40, and an output 58 thereof is connected to an input 58 of a band compression circuit 80. Has been done. Output from band compression circuit 80 82
Is connected to the data line 92 of the connector 14. The other structure is the same as that of the embodiment shown in FIG. In the following figures, elements similar to those shown in FIG. 1 are designated by the same reference numerals.

In the camera of FIG. 2, the switch circuit 56 is a control circuit.
It is a selection circuit that selectively takes three selective connection positions in response to the control output 60 of 24. The control circuit 24 uses this control line 60.
A switching signal corresponding to the clock is output to the pixel. Therefore, the switch circuit 56 has three components of the signal processing circuit 40.
The color-separated color signals R, G, B, or the luminance signal Y, the color difference signals RY, BY data obtained at the output 42 of the book, that is, the component signal data are output to the band compression circuit 80 in a dot-sequential manner. To do. Data-compressed output from band compression circuit 80 58
Is written to the data line 92 of the memory 90 through the connector 14 as dot-sequential video signal data.

In the device shown in FIG. 2, the input of the band compression circuit 80.
Since 58 has one input, the band compression circuit 80 may be provided with one blocking circuit 142, one orthogonal transformation circuit 144, and one encoding circuit 146, as shown in FIG.
It is not necessary to provide three of these as shown in Fig. 3. Therefore, the block formation, the orthogonal transformation, and the encoding can be performed in a common circuit, so that the device can be simplified.

In FIG. 14, the encoding circuit 146 is provided with a table changeover switch 146a for changing over the table used for encoding. That is, it is effective to allocate different bits to each component signal in consideration of the ratios of the low-frequency component and the high-frequency component in the signal, so that different coding tables are used according to the component signals. For example, the signals output from the signal processing circuit 40 to the switch 56 are the luminance signal Y and the color difference signals RY and B-.
If it is Y, the luminance signal Y includes a relatively high frequency component, and the color difference signals RY and BY include a relatively low frequency component. Therefore, the luminance signal Y and the color difference signal are included. R-
Switching may be performed so that different encoding tables are used for Y and BY.

For example, since the color difference signals R-Y and B-Y include relatively low frequency components, the orthogonally transformed data is the 17th B
Concentrate to the upper left as shown. Therefore, in the encoding circuit, the switch 146a of the encoding circuit 146 is switched so that the encoding is performed by allocating the number of bits concentrated in the upper left direction as shown in FIG. 17C.

On the other hand, since the luminance signal Y contains a relatively high frequency component, the orthogonally transformed data is as shown in FIG. 17D, which is dispersed to the right and below as compared with the data in FIG. 17B. To be done. Therefore, the switch 146a of the encoding circuit 146 is switched to perform encoding so that the data is encoded by allocating the number of bits spread to the right and downward as shown in FIG. 17E.

Also, when the component signal is an RGB signal,
Since the G component signal has a greater contribution to the luminance signal than the R or B component signal, it is preferable to store a large amount of data. Therefore, for the G signal, for example, the number of bits as shown in FIG. 17E is assigned and stored including the data of the high frequency component, and for the signals of the R and B components, for example, the bit numbers as shown in FIG. 17C are stored. Allocate and store only the low frequency component data.

Further, for data compression in the band compression circuit 80, a buffer memory is provided between the signal processing circuit 40 and the switch 56, and the data output from the signal processing circuit 40 is temporarily stored in the buffer memory and output to the switch 56. You may do it.

In another embodiment of the present invention shown in FIG. 3, the video signal output 38 of the imaging device 22 is directly connected to the input 38 of the signal processing circuit 40, and the three outputs 42 of the circuit 40 are three analog signals.
It differs from the embodiment of FIG. 1 in that it is connected to the inputs of three band compression circuits 80 via a digital converter 62. Therefore, the signal processing circuit 40 has a circuit configuration in which the video signal output from the imaging device 22 is processed as an analog signal. Similar to 36, the analog-digital converter 62 is a signal conversion circuit for converting the analog component video signal obtained at the input 42 into corresponding digital data of, for example, 8 bits and outputting it at the output 64. is there.

An embodiment of the present invention in which a switch circuit 56 is provided between these three band compression circuits 80 and the connector 14 and one output of the switch circuit 56 is connected to the data line 58 of the connector 14 is shown in FIG. ing. In this embodiment, 3 of the band compression circuit 80 is used.
The switch circuit 56 is connected to the output 82 of the book, and its output 58 is connected to the data line 58 of the connector 14, which is different from the embodiment of FIG. Therefore, in this embodiment, unlike the embodiment shown in FIG. 3, data is written from the data line 92 of the memory 90 to the dot-sequential video signal data through the connector 14.

Still another embodiment of the digital electronic still camera according to the present invention shown in FIG. 5 is the three outputs 42 of the signal processing circuit 40.
1 is different from the embodiment shown in FIG. 1 in that a line-sequentializing circuit 72 is connected to the output of the connector 14 and two outputs 74 thereof are connected to the data line of the connector 14 via a band compression circuit 80. Signal processing circuit 40
In this embodiment, the circuit configuration shown in FIG. 10 for outputting the video signal data in the form of the luminance signal Y and the color difference signals RY and BY data at its output 42 is advantageously used. The line-sequentializing circuit 72 receives a control signal synchronized with the horizontal synchronizing signal from the control circuit 24 through the control line 76, and in response thereto, digital data of the color difference signals RY and BY input from the output 42. The signal conversion circuit outputs to the output 74 in the form of scanning line sequential color difference signal data which is alternately repeated for each horizontal scanning line. As a result, the input 74 of the band compression circuit 80 is
The data of the luminance signal Y and the line-sequential color difference signals R-Y / B-Y are input as component signals. Band compression circuit
Although 80 is not shown in the case of performing orthogonal transformation,
A block circuit, an orthogonal transform circuit and two coding circuits are preferably applied. The component signal compressed in the band compression circuit 80 is stored in the memory 90.
Written in.

The video signal thus written in the memory 90 in the form of the line-sequential color difference signal is reproduced by the reproducing device 120 illustrated in FIG. In the reproducing device 120, the luminance signal Y and the color difference signals R-Y / B-Y read line-sequentially from the memory 90 are decoded by the band compression decoding circuit 86 and DA-converted by the DA converter 124. In the case where the band compression / decoding circuit 86 performs an inverse orthogonal transform, although not shown, one having two decoding circuits, two orthogonal inverse transform circuits and two block synthesizing circuits is advantageously applied.

This device differs from the circuit configuration of FIG. 11 in that it has a line-sequential synchronizing circuit 138 for synchronizing the color difference signals RY and BY, and does not have the matrix 126. The data of the color difference signals R-Y and B-Y read from the band compression / decoding circuit 86 in the scanning line sequential manner is converted into an analog signal by the DA converter 124, and then is transmitted to the line sequential synchronization circuit 138. The color difference signals of the missing scanning lines are interpolated and synchronized. Using this and the luminance signal Y, a composite video signal is formed by the encoder 130 and output from the device output 132.

FIG. 6 shows an embodiment in which the line-sequencing circuit 72 and the band compression circuit 80 are connected between the signal processing circuit 40 and the switch 56 shown in FIG. The output 58 of the switch 78 is directly written in the memory 90 via the connector 14. The two outputs 74 of the line-sequencing circuit 72 are input to the band compression circuit 80, data-compressed by the band compression circuit 80, and then connected to the connector 14 via the switch circuit 78. Switch circuit 78
Is the control output 60 of the control circuit 24, similar to the switch circuit 56.
Is a selection circuit which selectively takes two selective connection positions in response to. As a result, the luminance signal Y and the data of the line-sequential color difference signals R-Y / B-Y are written in the memory 90 in a dot-sequential manner.

Referring to FIG. 7, an AD converter 62 is connected between the line-sequencing circuit 72 and the band compression circuit 80 shown in FIG. 6, and the AD converter 62 between the image pickup unit 12 and the signal processing circuit 40 shown in FIG. An embodiment is shown with the AD converter 36 removed. The two outputs 74 of the line-sequencing circuit 72 are connected to the band compression circuit 80 through the two AD converters 62. The line sequentializing circuit 72 outputs the color difference signal RY output from the output 42 of the signal processing circuit 40 in the form of an analog signal.
And BY are analog signal operation circuits that use scanning line sequential signals. The line-sequential luminance signal Y and line-sequential color difference signals RY / B-Y in the form of analog signals are converted into AD converter 62.
Are converted to corresponding digital signal data by the band compression circuit 80, compressed by the band compression circuit 80, converted into a dot-sequential signal by the switch 78, and stored in the memory 90 as a dot-sequential signal.

Referring to FIG. 8, the switch 78 of FIG. 7 is omitted, and the output 82 of the band compression circuit 80 is directly passed through the connector 14,
An embodiment is shown in which writing to memory 90 as a line-sequential signal is performed.

The video signal stored in the memory 90 by these devices is read out from the memory 90 by a reproducing device having substantially the same configuration as shown in FIG. 11 or FIG. 12 and is visible to an output device such as a video monitor 134. It is output as an image.

In this embodiment, the semiconductor memory is described as being detachable via the connector, but the semiconductor memory may be fixedly mounted in the electronic camera.

Effect According to the present invention, the video signal is thus stored in the memory in the standard signal format as the video signal called the component signal. Therefore, the reproducing apparatus can appropriately reproduce the image without performing signal processing such as color separation depending on the type of the video device.

Moreover, since the data compression is performed on the component signal by the data compression means, it is possible to reduce the capacity of the memory although the component signal is stored in the format of the component signal.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a digital electronic still camera according to the present invention, and FIGS. 2 to 8 are the same functions as FIG. 1 showing another embodiment of the digital electronic still camera according to the present invention. Block diagrams, FIGS. 9 and 10 show configuration examples of signal processing circuits used in these embodiments. The circuit shown in FIG. 9 outputs three primary color signals, and the circuit shown in FIG. Block diagram showing an example of a signal processing circuit for outputting a signal and a color difference signal, FIG. 11 and FIG. 12 are functional blocks showing a configuration example of a reproducing device for reproducing a video signal stored in a memory according to these embodiments. FIG. 13 is a block diagram showing a configuration example of the band compression circuit in FIGS. 1, 3, and 4, and FIG. 14 is a block diagram showing a configuration example of the band compression circuit in FIG. FIG. 15 shows the band compression decoding circuit of FIG. FIG. 16A is a block diagram showing a configuration example, FIG. 16A is a diagram showing an example of an image before being divided into blocks, FIG. 16B is a diagram showing an example of dividing an image into blocks, and FIG. 17A is a pixel of one block. FIG. 17B is a diagram showing an example of data, FIG. 17B is a diagram showing an example of data obtained by orthogonally transforming the pixel data of FIG. 17A, and FIG. 17C is a diagram showing an example of the number of bits to be allocated in encoding the data of FIG. 17B. FIG. 17D is a diagram showing an example of data obtained by orthogonally transforming other pixel data, and FIG. 17E is a diagram showing an example of the number of bits to be allocated in encoding the data of FIG. 17D. Explanation of symbols of main parts 12 …… Imaging section 24 …… Control circuit 36,62 …… Analog / digital converter 40 …… Signal processing circuit 56,78 …… Switch circuit 80 …… Band compression circuit 90 …… Memory 142 ...... Blocking circuit 144 …… Orthogonal transformation circuit 146 …… Encoding circuit

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Claims (7)

[Claims] 1. A digital electronic still camera in which a color image signal representing a still image is stored in a semiconductor memory device in the form of digital data, wherein the camera has an imaging device, and an image of a field is captured to capture the object. An image pickup unit for outputting a color image signal based on pixels representing a field in a dot-sequential manner, and a color image signal based on pixels output in a dot-sequential manner from the image pickup unit for inputting each pixel from the input color image signal R, G, B primary color signals synchronized with each other are obtained, and the obtained synchronized three primary color signals are used as component signals,
Signal processing means for outputting the component signal in the form of a digital signal; data compression means for data-compressing the component signal output from the signal processing means and outputting the data to the semiconductor memory device; Controlling the means and the data compression means to cause the image pickup means to perform image pickup, and to cause the signal processing means to perform simultaneous conversion into the component signal,
A digital electronic still camera, comprising: control means for causing the data compression means to perform data compression of the component signal and supplying a control signal for writing to the semiconductor memory device. 2. The camera according to claim 1, further comprising means for supplying the semiconductor memory device with the compressed component signal output from the data compression means in the form of a dot-sequential signal. A digital electronic still camera characterized by including. 3. A digital electronic still camera according to claim 1 or 2, wherein the data compression means includes an orthogonal transformation means and an encoding means. 4. A digital electronic still camera in which a color image signal representing a still image is stored in a semiconductor memory device in the form of digital data, wherein the camera has an imaging device, and an image of a field is captured to capture the object. An image pickup unit for outputting a color image signal based on pixels representing a field in a dot-sequential manner, and a color image signal based on pixels output in a dot-sequential manner from the image pickup unit for inputting each pixel from the input color image signal Signal processing means for obtaining the three primary color signals of R, G, and B synchronized with each other, converting the obtained three primary color signals into component signals, and outputting the component signals in the form of digital signals to the semiconductor memory device. The signal processing means has a matrix which receives the obtained three primary color signals and forms a luminance signal and a color difference signal for each pixel to form the component signal. The camera further includes a data compression unit that compresses the component signal output from the signal processing unit and outputs the compressed component signal to the semiconductor memory device, and the imaging unit, the signal processing unit, and the data compression unit. And the signal processing means to perform simultaneous conversion into the three primary color signals, the data compression means to perform data compression of the component signal, and the semiconductor memory device. And a control means for supplying a control signal for writing to the digital electronic still camera. 5. A digital electronic still device according to claim 4, wherein said signal processing means includes line-sequentializing means for alternately outputting said color difference signals in a horizontal scanning line-sequential manner. camera. 6. The camera according to claim 4 or 5, wherein the camera further stores the compressed component signal output from the data compression means in the form of a dot sequential signal. A digital electronic still camera, characterized in that it comprises means for supplying the device. 7. The camera according to any one of claims 4 to 6, wherein the data compression means is
A digital electronic still camera characterized by including orthogonal transformation means and encoding means.