JPH07109987B2 - AD conversion circuit - Google Patents
AD conversion circuitInfo
- Publication number
- JPH07109987B2 JPH07109987B2 JP8030387A JP8030387A JPH07109987B2 JP H07109987 B2 JPH07109987 B2 JP H07109987B2 JP 8030387 A JP8030387 A JP 8030387A JP 8030387 A JP8030387 A JP 8030387A JP H07109987 B2 JPH07109987 B2 JP H07109987B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- conversion
- circuit
- switch
- resolution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば電圧の変化を検出して制御信号を形成
する場合に使用して好適なAD変換回路に関する。The present invention relates to an AD conversion circuit suitable for use in the case of detecting a change in voltage and forming a control signal, for example.
本発明はAD変換回路に関し、入力信号の電圧の上昇に従
つて参照用の低電位を上げて行くことにより、特に高電
位近傍での分解能が高められるようにするものである。The present invention relates to an AD conversion circuit, which raises the reference low potential as the voltage of an input signal rises, thereby enhancing the resolution especially near the high potential.
例えばNiCdバツテリーの急速充電を行う場合に、バツテ
リーが満充電に達した後に充電を続けていると過充電と
なつて爆発等の危険がある。For example, when performing rapid charging of NiCd battery, if the battery is continuously charged after reaching the full charge, there is a risk of overcharge and explosion.
これに対してNiCdバツテリーの端子電圧を観察している
と、第２図に示すように端子電圧は満充電になるまで
（期間Ａ）は上がり続けると共に、満充電後（期間Ｂ）
にさらに充電（電流を流す）を続けると端子電圧は降下
し始める。On the other hand, when observing the terminal voltage of the NiCd battery, as shown in FIG. 2, the terminal voltage continues to rise until it is fully charged (period A), and after it is fully charged (period B).
If the charging is further continued (current flows), the terminal voltage starts to drop.
そこでNiCdバツテリーの端子電圧を観測し、この電圧が
ピークに達した後に所定電圧ΔＶ下がつたことを検出
し、この検出信号にて充電を停止させることが提案され
た。Therefore, it has been proposed to observe the terminal voltage of the NiCd battery, detect that the voltage drops by a predetermined voltage ΔV after this voltage reaches a peak, and stop the charging with this detection signal.
この場合に端子電圧の観測にはいわゆるAD変換回路を用
いてこのビツトの信号の変化を検出する方法がマイクロ
コンピユータ等との組合せにおいて有効である。In this case, a method of detecting a change in the bit signal by using a so-called AD conversion circuit is effective for observing the terminal voltage in combination with a micro computer or the like.
ところがこの場合に、例えば28.5Vのピーク電圧を検出
するために８ビツトのAD変換回路を用いるとその分解能
は100mV以上になつてしまう。一方上述の過充電の検出
を行う降下電圧ΔＶは40mV程度が適当である。従つてこ
のような構成では適切な検出を行うことができなかつ
た。またこれだけのためにさらに多ビツトのAD変換回路
を用いることは製造コスト等の面で好ましくない。However, in this case, if an 8-bit AD conversion circuit is used to detect the peak voltage of 28.5V, the resolution becomes 100 mV or more. On the other hand, it is appropriate that the drop voltage ΔV for detecting the above-mentioned overcharge is about 40 mV. Therefore, in such a structure, proper detection cannot be performed. In addition, it is not preferable to use the AD conversion circuit having a larger number of bits for this reason in terms of manufacturing cost.
ところでAD変換回路の分解能を高める方法は種種提案さ
れている。例えば第３図においては、入力信号の電圧の
最大値に相当する電圧VBを複数の抵抗器R1〜Rnが直列に
接続された分圧回路で分圧し、この各抵抗器の両端の電
圧を連動スイツチSW1,SW2を介してそれぞれAD変換回路
の参照用の高電位Vcc及び低電位Vssとして用いる。これ
によれば、入力信号のレベルに応じて連動スイツチSW1,
SW2を順次切換えて行くことにより、各抵抗器の両端間
の電圧を例えば256等分した値の分解能を得ることがで
きる。By the way, various methods have been proposed for increasing the resolution of the AD conversion circuit. For example, in FIG. 3, the voltage V B corresponding to the maximum value of the voltage of the input signal is divided by a voltage dividing circuit in which a plurality of resistors R 1 to R n are connected in series, and the voltage across the resistors is divided. The voltage is used as a high potential Vcc and a low potential Vss for reference of the AD conversion circuit via the interlocked switches SW 1 and SW 2 , respectively. According to this, according to the level of the input signal, the interlocked switches SW 1 ,
By sequentially switching SW 2 , it is possible to obtain a resolution of a value obtained by dividing the voltage across each resistor by 256, for example.
ところがこの回路の場合に、任意の抵抗器によるAD変換
値が最大値を越えたときに、例えばCPUの出力によつて
連動スイツチSW1,SW2をその上の抵抗器に切換えるよう
にされているが、このとき入力信号のピーク値がこの切
換え点の近傍にあると、このピーク値から降下した電圧
の検出が容易に行えない場合が生じる。However, in the case of this circuit, when the AD conversion value by an arbitrary resistor exceeds the maximum value, for example, the output of the CPU is used to switch the interlocking switches SW 1 and SW 2 to the resistor above it. However, if the peak value of the input signal is near this switching point at this time, the voltage dropped from this peak value may not be easily detected.
これに対して本願出願人は先に、入力信号のレベルに応
じて分解能の変化される回路を提案している（特公昭57
-10,612号公報、特公昭57-53,698号公報参照）。しかし
ながらこの回路の場合、実施例からも明らかなように入
力信号のレベルが上がるに従つて分解能は下がる方向に
制御されており、上述した本願の目的に達するものでは
なかつた。On the other hand, the applicant of the present application has previously proposed a circuit whose resolution is changed according to the level of the input signal (Japanese Patent Publication No.
-10,612, Japanese Patent Publication No. 57-53,698). However, in the case of this circuit, the resolution is controlled so as to decrease as the level of the input signal rises, as is apparent from the embodiments, and the above-mentioned object of the present application was not reached.
以上述べたように従来の技術では、入力信号の電圧が高
いときに分解能を高くすると共に、その切換えを円滑に
行うことができないなどの問題点があつた。As described above, the conventional technique has a problem that the resolution cannot be increased when the voltage of the input signal is high and the switching cannot be performed smoothly.
本発明は、AD変換（回路（２））の参照用の高電位Vcc
を複数の分圧点を有する分圧回路（３）で分圧し、この
分圧回路の各分圧点の出力をスイツチ（４）で選択して
上記AD変換の参照用の低電位Vssとして用いるように
し、入力信号の電圧の上昇に従つて上記スイツチを順次
高電位の分圧点に切換えて行くことにより、上記AD変換
の分解能が段階的に上げられるようにしたことを特徴と
するAD変換回路である。The present invention provides a high potential Vcc for reference of AD conversion (circuit (2)).
Is divided by a voltage dividing circuit (3) having a plurality of voltage dividing points, and the output of each voltage dividing point of this voltage dividing circuit is selected by a switch (4) and used as a low potential Vss for reference of the AD conversion. In this way, the AD conversion is characterized in that the resolution of the AD conversion can be stepwise increased by sequentially switching the switch to a voltage dividing point of high potential according to the rise of the voltage of the input signal. Circuit.
これによれば、入力信号の電圧の上昇に従つて分解能が
高められると共に、この切換えが常にオーバーラツプを
持つて行われるので、極めて円滑な切換えを行うことが
できる。According to this, the resolution is enhanced as the voltage of the input signal rises, and this switching is always performed with an overlap, so that extremely smooth switching can be performed.
第１図において、AD変換の参照用の高電位Vccの供給さ
れる入力端子（１）がAD変換回路（２）のVcc入力に接
続されると共に、上述の入力端子（１）が抵抗器R1〜Rn
の直列接続からなる分圧回路（３）を通じて接地され
る。この分圧回路（３）の各分圧点及び接地端がスイツ
チ（４）の各固定接点に接続され、このスイツチ（４）
の可動接点がAD変換回路（２）の参照用の低電位Vssの
入力に接続される。In FIG. 1, the input terminal (1) to which a high potential Vcc for reference of AD conversion is supplied is connected to the Vcc input of the AD conversion circuit (2), and the above-mentioned input terminal (1) is a resistor R. 1 to R n
Is grounded through a voltage dividing circuit (3) composed of a series connection. Each voltage dividing point and the grounding end of this voltage dividing circuit (3) are connected to each fixed contact of the switch (4), and this switch (4)
Is connected to the input of the reference low potential Vss of the AD conversion circuit (2).
さらに被測定用の入力信号の供給される入力端子（５）
がAD変換回路（２）のAD変換入力に接続され、AD変換出
力が例えばCPU（６）に接続される。そしてこのCPU
（６）にてAD変換値に応じて充電停止等の制御信号の形
成が行われると共に、例えばAD変換値が最大値の50％を
越えたときにスイツチ（４）を順次高電位側の分圧点に
切換える制御信号が形成される。Further, an input terminal (5) to which an input signal for measurement is supplied
Is connected to the AD conversion input of the AD conversion circuit (2), and the AD conversion output is connected to, for example, the CPU (6). And this CPU
At (6), a control signal such as charging stop is formed according to the AD conversion value, and, for example, when the AD conversion value exceeds 50% of the maximum value, the switch (4) is sequentially changed to the high potential side. A control signal is generated which switches to the pressure point.
従つてこの回路において、例えば８ビツトのAD変換回路
（２）を用いる場合にVccを例えば28.5Vとして、ｎ＝10
とすると各抵抗器R1〜Rn-1の降下電圧を例えば2.56Vに
することができる。なおこの場合に抵抗器Rnの降下電圧
は5.46Vとされ、ここでこの抵抗器Rnを可変抵抗器とし
て各抵抗器R1〜Rn-1の降下電圧が所望の値となるように
調整することができる。Therefore, in this circuit, when using, for example, an 8-bit AD conversion circuit (2), set Vcc to, for example, 28.5V and n = 10.
Then, the voltage drop of each of the resistors R 1 to R n-1 can be set to 2.56V, for example. In this case, the voltage drop of the resistor R n is set to 5.46 V, and the resistor R n is used as a variable resistor so that the voltage drop of each of the resistors R 1 to R n-1 becomes a desired value. Can be adjusted.
そしてこの回路において、スイツチ（４）が図面の１番
下の固定接点に接続されているときはVcc-Vss間に28.5V
が供給されて分解能は100mV以上になるが、この状態でA
D変換値が最大値の50％を越えて次の固定接点に切換え
られると、Vcc-Vssは2.56×９＝23.04Vとなり、分解能
は90mVになる。さらにスイツチ（４）が順次上の固定接
点に換えられるに従つて分解能は80mV,70mV……と変化
され、図面１番上の固定接点に接続されているときはVc
c-Vss間は2.56Vとなつて分解能は10mVになる。And in this circuit, when the switch (4) is connected to the fixed contact at the bottom of the drawing, it is 28.5V between Vcc and Vss.
Is supplied and the resolution becomes 100 mV or more, but in this state A
When the D conversion value exceeds 50% of the maximum value and is switched to the next fixed contact, Vcc-Vss becomes 2.56 × 9 = 23.04V and the resolution becomes 90 mV. Further, the resolution is changed to 80mV, 70mV, etc. as the switch (4) is sequentially changed to the fixed contact on the upper side, and when it is connected to the fixed contact on the top of the drawing, Vc
Between c-Vss is 2.56V and the resolution is 10mV.
すなわちこの回路において入力信号の電圧の上昇に従つ
てスイツチ（４）が順次切換えられて行くことにより、
AD変換の分解能が段階的に上げられる。そして例えば上
述の条件でスイツチ（４）が１番上の固定接点に接続さ
れている状態でAD変換値がピーク値から「４」下がつた
とき、あるいはスイツチ（４）が上から２番目の固定接
点に接続されている状態で値が「２」下がつたときに40
mVの電圧降下がCPU（６）で判別され、充電停止時の制
御を行うことができる。That is, in this circuit, the switch (4) is sequentially switched as the voltage of the input signal rises,
The resolution of AD conversion is gradually increased. For example, when the switch (4) is connected to the uppermost fixed contact under the above conditions and the AD conversion value falls by "4" from the peak value, or the switch (4) is the second from the top. 40 when the value is "2" lower when connected to the fixed contact
The voltage drop of mV is determined by the CPU (6), and control can be performed when charging is stopped.
また上述の回路において、スイツチ（４）の切換えは常
に変換される範囲の略中央で行われ、AD変換の範囲がオ
ーバーラツプされているので、切換えが極めて円滑に行
われ、良好なAD変換を行うことができる。Further, in the above-mentioned circuit, the switch (4) is always switched in the approximate center of the conversion range, and the AD conversion range is overlapped, so that the switching is performed very smoothly and good AD conversion is performed. be able to.
この発明によれば、入力信号の電圧の上昇に従つて分解
能が高められると共に、この切換えが常にオーバーラツ
プを持つて行われるので、極めて円滑な切換えを行うこ
とができるようになつた。According to the present invention, the resolution is enhanced as the voltage of the input signal increases, and this switching is always performed with an overlap, so that extremely smooth switching can be performed.
第１図は本発明の一例の構成図、第２図、第３図は従来
の技術の説明のための図である。 （１）（５）は入力端子、（２）はAD変換回路、（３）
は分圧回路、（４）はスイツチ、（６）はCPUである。FIG. 1 is a configuration diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining a conventional technique. (1) (5) is an input terminal, (2) is an AD conversion circuit, (3)
Is a voltage dividing circuit, (4) is a switch, and (6) is a CPU.
Claims (1)
有する分圧回路で分圧し、 この分圧回路の各分圧点の出力をスイツチで選択して上
記AD変換の参照用の低電位として用いるようにし、 入力信号の電圧の上昇に従つて上記スイツチを順次高電
位の分圧点に切換えて行くことにより、 上記AD変換の分解能が段階的に上げられるようにしたこ
とを特徴とするAD変換回路。1. A high potential for reference of AD conversion is divided by a voltage dividing circuit having a plurality of voltage dividing points, and the output of each voltage dividing point of this voltage dividing circuit is selected by a switch to refer to the above AD conversion. It is used as a low potential for the above, and the resolution of the AD conversion can be increased stepwise by switching the switch to the voltage dividing point of the high potential in sequence as the voltage of the input signal rises. AD conversion circuit characterized by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8030387A JPH07109987B2 (en) | 1987-03-31 | 1987-03-31 | AD conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8030387A JPH07109987B2 (en) | 1987-03-31 | 1987-03-31 | AD conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63246032A JPS63246032A (en) | 1988-10-13 |
| JPH07109987B2 true JPH07109987B2 (en) | 1995-11-22 |
Family
ID=13714505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8030387A Expired - Lifetime JPH07109987B2 (en) | 1987-03-31 | 1987-03-31 | AD conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07109987B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05143221A (en) * | 1991-11-20 | 1993-06-11 | Smk Corp | Resistance pressure-sensitive type tablet |
| JPH05143222A (en) * | 1991-11-20 | 1993-06-11 | Smk Corp | Tablet position detecting method |
| JPH05143223A (en) * | 1991-11-20 | 1993-06-11 | Smk Corp | Tablet position detecting method |
| US5475335A (en) * | 1994-04-01 | 1995-12-12 | National Semiconductor Corporation | High voltage cascaded charge pump |
-
1987
- 1987-03-31 JP JP8030387A patent/JPH07109987B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63246032A (en) | 1988-10-13 |
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