JPH07106971A - D/a converter - Google Patents

Abstract

PURPOSE:To improve the conversion accuracy of a current cell matrix type D/A converter. CONSTITUTION:An n-bit digital signal is supplied, and the constant current cells are arranged in a matrix shape for conversion of higher (m) bits of the digital signal. The remaining (n-m) bits consist of the constant current cells with reduced weights. Furthermore a decoding circuit which decodes the higher (m) bits is replaced with a storage circuit 2 or 3 that can transmit an optional signal. In such a constitution, an optimum constant current cell can be selected for a D/A converter and the D/A conversion accuracy is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to a current cell matrix type D / A converter.

[0002]

2. Description of the Related Art Conventionally, a current cell matrix type D / A converter is disclosed in a document "30 MHz 10 bit CMOS.
D / A converter "Matsushita Electronics Industrial (ICD88-6 / v
o1, 88, No. 10 pp. 39-46), it has a structure as shown in FIG.

This current cell matrix type D / A converter is an example of a current cell matrix type D / A converter for converting a 9-bit digital signal into an analog signal.
Among the digital inputs of the bits, the upper 6 bits pass through the current cells arranged in the matrix, and the lower 3 bits perform the digital-analog conversion through the weighted constant current reduction.

Next, the configuration and connection of the D / A converter will be briefly described with reference to FIG. 6, and the D / A converter has a 9-bit digital input terminal (19 to 25). Of these, the upper 3 bits of the signal (D8, D7,
D6, but D8 is input to the upper bit) Y decoder 3 '. The Y decoder 3'has a 7-bit output, and this output is input to the Y latch circuit group 46. The output of the Y latch circuit group 46 is input as the row selection control signal of the first current cell group 1.

On the other hand, the middle 3-bit signal (D5, D4, D3, where D5 is the higher bit) of the 9-bit input is input to the X decoder 2 ', and the output of the X decoder 2'is 7
It has a bit output and is input to the X latch circuit group 47. The output of the X latch circuit group 47 is the first current cell group 1
Is input as a selection control signal in the column direction.

The remaining low-order 3 bit signals (D2, D1, D0, where D2 is the high-order bit) of the 9-bit input are input as the data input of the second latch circuit group 48.
The 3-bit data output of the second latch circuit group 48 is input to the switch circuit group 49 having this as a control signal input.

A constant current source 33 having a current value (1/2) · I and a constant current source 34 having a current value (1/4) · I
And each of the constant current sources 35 having a current value (1/8) · I are connected to the analog output terminal 29 or the power supply terminal 28 by the control signal via the switch circuit group 49. An output load resistor 42 having a resistance value (2/3) · R is connected between the power supply terminal 28 and the analog output terminal 29.

Next, the internal circuit of each block will be described. The signal level between blocks is abbreviated as "0" for Low level and "1" for High level.

First, the structure of the first current cell group 1 will be described.

This first current cell group 1 is composed of a total of 63 current cells (1-1 to 1-63), and these current cells are arranged in both the row and column directions as shown in FIG. They are arranged in a matrix.

Further, these current cells (1-1 to 1-6)
Referring to FIG. 2 showing the detailed portion of 3), this configuration uses the output signal or the power source output from the latch circuits (11 to 18) of the Y latch circuit group 46 as one input and the other input as the X latch. Any one output of circuit group 47 or GND
2 input logical product circuit (1-A), the output of the 2-input logical product circuit (1-A) and the output signals output from the latch circuits (11 to 18) of the Y latch circuit group 46, or An OR circuit (1-B) having GND as an input, this logic circuit (1-B), and an output of this logic circuit (1-B) through a control signal input and a switch circuit (1-D) to a power supply terminal 28 or a constant current source (1-C) having a current value I connected to the analog output terminal 29.

Next, the digital input signals (D3, D4, D5) input to the digital input terminals (22-24) are set to 7
The operation of the X decoder 2'for decoding into a bit signal will be described.

When the digital input signals (D3, D4, D5) are (D5, D4, D3) = (0, 0, 0), the output signals (109-115) of the X decoder 2'are all "1". Become. Then, each time the digital input signal is increased by one step, when (D5, D4, D3) = (0, 0, 1), only the output signal 109 of the X decoder 2'is "0", and the other output signals ( 110-115) becomes "1", and (D5, D
4, D3) = (0, 1, 0), only the output signals (109, 110) of the X decoder 2'are "0", the other output signals (111-115) are "1", and (D5, D4, D
3) = (0,1,1), X decoder output signal (10
9 to 111) only "0", other output signals (112 to 11)
5) is "1" ... (D5, D4, D
3) = (1,1,1) when X decoder output signal 109
~ 115 are all X decoder output signals in the form of "0". Thus, when the digital input signal is increased by one step, the X decoder output signals (109 to 115) sequentially change from "1" to "0".

Further, digital input terminals (25 to 27)
The operation of the Y-decoder 3'for decoding the digital input signals (D6, D7, D8) input to the terminal into a 7-bit signal will be described.

When the digital input signals (D8, D7, D6) are (D8, D7, D6) = (0, 0, 0), the output signals (100 to 106) of the Y decoder 3'are all "1". Become. Then, every time the digital input signal is increased by one step, when (D8, D7, D6) = (0, 0, 1), only the output signal 100 of the Y decoder 3 ′ becomes “0”,
The other output signals (101 to 106) become "1" and (D
8, D7, D6) = (0, 1, 0), only the output signal 100 of the Y decoder 3'is "0" and the other output signals (10
1 to 106) becomes “1”, and (D8, D7, D6) =
When it is (0, 1, 0), the output signal (10
0, 101) only "0" other output signals (102-10)
6) becomes “1”, and (D8, D7, D6) = (0,
In case of 1, 1), the output signal of the Y decoder 3 '(100 to 1)
02) only becomes "0", the other output signals (103 to 106) become "1", and the digital input signals (D8, D7, D) are sequentially input.
6) changes step by step, (D8, D7, D6)
= (1,1,1), the output signal (1
00 to 106) all Y-decoder output signals in the form of "0". In this way, when the digital input signal is increased by one step, the output signal of the Y decoder 3 '(100 ...
106) sequentially changes from “1” to “0”.

Further, latch circuits (4 to 18, 30 to 3)
2) latches the input data and outputs the logic as it is. However, the latch circuits (11 to 18) are circuits for latching 2-input data.

Furthermore, switch circuits (43 to 45,
1-D), depending on the control signal "1" or "0",
The constant current sources (33 to 35, 1-C) serve as signals that determine how to draw current from the power supply terminal 28. The constant current source (33 to 35, 1-C) draws a current from the power supply terminal 28 directly via the switch circuit (43 to 45) or the power supply via the load resistor 42. There are two ways to draw the current from the terminal 28.

These two operations are performed by the switch circuit (1-
In the case of D), when the input control signal is "0", the former operation described above is selected, and when it is "1", the latter operation is selected. In the former operation, the constant current source is the power supply terminal 28.
Since a current is directly drawn from the power supply terminal 28, the potential difference between the power supply terminal 28 and the analog output terminal 29 is not changed.

On the other hand, in the latter operation, a current is drawn from the power supply terminal 28 via the load resistor 42, so that a potential difference is generated between the power supply terminal 28 and the analog output terminal 29. Regarding the operation of the switch circuits (43 to 45), the switch circuit (1-
When the control signal is “0”, the switch circuit (43 to 45) operates so that the current path is between the constant current source (33 to 35) and the load resistor 42, which is completely opposite to the operation of D). A current is drawn from the power supply terminal 28, and when the control signal is "1", the switch circuit (43 to 45) operates so that a direct current path is formed between the constant current source (33 to 35) and the power supply terminal 28, and the current is supplied. Pull.

Next, the selection order of the current cells (1-1 to 1-63) forming the first current cell group 1 will be described. Here, when the internal constant current source (1-C) of the current cells (1-1 to 1-63) draws a current from the power supply terminal 28 via the switch circuit (1-D) and the load resistor 42. , A current cell that applies a voltage to the analog output terminal 29, this current cell is called a "selected state current cell". Conversely, when a current is directly drawn from the power supply terminal 28, it is called a "non-selected state current cell". To call.

From the above description of the operation of the switch circuit (1-D), the X decoder 2'and the Y decoder 3 ', the digital input signal is (D8, D7, D6, D5, D4, D3) =
When (0, 0, 0, 0, 0, 1), the current cell (1-1)
In the non-selected state, the current cells (1-2 to 1-63) are in the selected state. Digital input signals are (D8, D7, D6, D
5, D4, D3) = (0, 0, 0, 0, 1, 0), the current cells (1-1, 1-2) are in the non-selected state and the current cells (1-3 to 1-63) Is selected. Similarly, (1-3), (1-4), (1-5) of the current cells each time the digital input signal is increased by one step ...
.. (1 to 63) becomes the non-selected state. Digital input signals (D8, D7, D6, D5, D4, D
3) = (1,1,1,1,1,1,1), all the current cells (1-1 to 1-63) are in the non-selected state.

Finally, the normal operation of this prior art D / A converter will be described.

Digital input signals (D8, D7, D6, D5, D4, D3, to the digital input terminals (19 to 27))
D2, D1, D0) = (1, 0, 0, 1, 0, 0, 1,
It is assumed that the input is 0, 1).

The digital input signal of the lower 3 bits is (D
Since 2, D1, D0) = (1, 0, 1), the control signals input from the latch circuits (30-32) to the switch circuits (43-45) are (1, 0, 1), respectively. .
The switch circuit 43 is in the non-selected state, and the switch circuit 4
4 is in the selected state and the switch circuit 45 is in the non-selected state, so that the constant current sources 33 and 35 directly draw current from the power supply terminal 28, and the constant current source 34 passes through the load resistor 42 and the power supply terminal 28. Draw the current from.

The middle 3-bit digital input signal input to the X decoder 2'is (D5, D4, D3) = (1,
0, 0), the output signal (11
3 to 115) are "1", and the output signals (109 to 112) of the remaining X decoder 2'are "0". Y decoder 3 '
Upper 3 bits of the digital input signal (D8,
Since D7, D6) = (1, 0, 0), the output signals (104 to 106) of the Y coder 3'are "1" and the remaining Y.
The output signal (100 to 103) of the decoder 3'becomes "0". Then, regarding the row and column selection control signals of the current cells input to the respective current cells (1-1 to 1-63),
The output signals (109 to 115 and 100 to 106) of the aforementioned X decoder 2'and decoder 3'are obtained via the latch circuits (4 to 10 and 11 to 18). Therefore, regarding the column of the first current cell group 1, the current cells (1
-61, 1-62, 1-63), the current cells arranged in the same column as the current cells
One input of A) becomes "1". Similarly, one input of the AND circuit (1-A) in the current cells arranged in the same column as the current cells of the remaining current cells (1-56 to 1-60) becomes "0".

Further, regarding the row of the first current cell group 1,
For the current cells arranged in the same row of the current cells of the current cells (1-47, 1-55, 1-63), one input of the logical sum circuit (1-B) becomes "1". Similarly, the remaining current cells (1-7, 1-15, 1-23, 1-31, 1
-39), one input of the OR circuit (1-B) of the current cells arranged in the same row as each current cell is "0"
Becomes

Regarding the signal inputted to one input of the AND circuit (1-A) which is another row selection signal relating to the row of the current cells, the current cells (1-7, 1-15, 1-2)
3, 1-31), the current cell arranged in the same row is "0"
And similarly the current cells (1-39, 1-47, 1-5
5, 1-63), the current cell arranged in the same row is "1".

From these, the row selection signals of the current cells input to the logical sum circuit (1-B) and the logical product circuit (1-A) are the current cells (1-47, 1-55, 1-63). The current cell in the same row as "1" becomes "1" at both inputs of the logical product circuit (1-A) and the logical sum circuit (1-B). Therefore, according to the logical sum theorem, the output of the logical sum circuit (1-B) is "1".
And the switch circuit (1-
D) is in the selected state, and gives the potential difference of the analog output terminal 29.

On the other hand, the current cells (1-7, 1-15, 1-
23, 1-31), the inputs of the AND circuit (1-A) and the OR circuit (1-B) are both "0" in the current cell in the same row. −
The output of B) becomes "0", the switch circuit (1-D) of the corresponding current cell is in the non-selected state, and does not affect the potential difference of the analog output terminal 29.

In the current cells arranged in the same row as the remaining current cells (1-39), one input of the logical sum circuit (1-B) is "0" and one input of the logical product circuit (1-A). Becomes "1". The selection and non-selection of the current cells arranged in the same row as the current cell (1-39) cannot be determined only by the row selection signal, but depends on the column selection signal. Therefore, the current cell (1-37, 1-37, where the column selection signal is "1")
1-38, 1-39) are in the selected state, and the remaining current cells (1-32 to 1-36) are in the non-selected state.

The selective non-selected state of each current cell of the first and second current cell groups is the current cell, (1-37 to 1-6).
3) and the constant current source 34 are in the selected state. Therefore, the potential difference between the analog output terminal 29 and the power supply terminal 28 (VDD
−Vout) is given by the equation (1) from the product of the sum of the current values of the constant current sources in the current cells in the selected state and the resistance value (2/3) R of the load resistor 42.

[0032]

By the above operation, a series of digital-analog conversions are performed, and the 9-bit digital input signals (D8, D7, D6, D5, D) are supplied to the analog output terminal 29.
4, D3, D2, D1, D0), an analog output signal Vout having a resolution corresponding to the above can be obtained.

[0034]

However, in the conventional current cell matrix type D / A converter, each current cell in the first current cell group for converting the higher order digital input signal is selected. The order has been determined by the signal output method of the X, Y decoder.

On the other hand, this current cell matrix type D / A
In the converter, it is said that the selection order of the current cells in the current cell group is selected as randomly as possible to improve the integral linearity error. This integral linearity error is an important item in the characteristic evaluation of the D / A converter,
It shows the difference (error) between the ideal and the actual digital / analog conversion output for each input code.

The reason why the integrated linearity error is improved by randomly selecting the current cells is that the current value of the constant current source in the current cells varies on the IC chip. Therefore, X, so that the selection order of the current cells is as random as possible.
The wiring from the Y decoder output to the latch circuit and the wiring between the output of the latch circuit group and each current cell were devised (see the above-mentioned document "30 MHz 10-bit CMOS").
D / A converter "Matsushita Electronics Industrial (ICD88-6 / v
ol, 88, No. 10 pp. 39-46) or
Reference "A 10-bit 80MHz CMOS D /
A Converter "Toshiba (see CICC'91 Technical Report, pp. 26.5.1 to 26.5.2).

However, since the countermeasure by this wiring is on the mask, it is effective only for the statistical variation result of the current cells in the manufacture of the IC chip, and the order of selecting the current cells is all the chips. Are the same,
It cannot be said that the effect is large with respect to the difference in the variation of the current cell for each IC chip.

In particular, the difference in the variations of the current cells of the IC chip mounted in the plus chip package is remarkable, and even if the above-mentioned wiring measures are taken to improve the integral linearity error, it is slightly less than 9 to 10 bits. Digital
Satisfying the analog conversion accuracy was the best, and there was a problem in improving the conversion accuracy.

[0039]

A D / A converter according to the present invention comprises an n-bit (n is a positive integer) digital input terminal,
An analog output terminal, a memory circuit that receives the upper m bits (m is a positive integer) of the n-bit digital input terminal as an input and has an arbitrary number of outputs, and a memory circuit that receives all outputs of the memory circuit 1 latch circuit group, a first current cell group that receives all outputs of the first latch circuit group as control signal inputs, and (n
-M) A power supply terminal and the analog output terminal are connected through a second latch circuit group that receives all of the bits as data inputs and a switch circuit group that receives the outputs of all of the second latch circuit groups as control signal inputs. And a second current cell group. The D / A conversion device of the present invention is the integer n
Also, m and m may have a relationship of n ≧ m and m ≧ 2. Still further, in the D / A conversion device of the present invention, the m-bit input is high Y bits and low X bits.
Bits (X and Y are natural numbers) and m =
It is also possible to adopt a configuration of X + Y. Further, the memory circuit of the D / A conversion device of the present invention may be configured by a first memory circuit having the X bit as an address input and a second memory circuit having the Y bit as an address input. it can. Furthermore, the first latch circuit group of the D / A conversion device of the present invention includes an X-latch circuit group that receives all the outputs of the first memory circuit as input, and all the outputs of the second memory circuit. The D / A conversion device according to the present invention may have a current value of (2 ^m ) or (2 ^m-1 ). I (real number), and these current cells use the output of the Y-latch circuit group as a row selection control signal and X
The output of the latch circuit group may be arranged in a matrix as a column selection control signal, and further, D of the present invention may be used.
The current cell of the A / A converter has a 2-input logical product in which an arbitrary output of the Y latch circuit group is one input and the other input is an arbitrary output of the X latch circuit group, and this 2-input logical product. The output of the product is one input and the other input is the Y
-Connect one to the power supply terminal and the analog output terminal via a two-input logical sum that is an arbitrary output of the latch circuit group and a switch circuit that uses the output of the two-input logical sum as a control signal input, and the other It can also be configured with a constant current source having the current value I (real number) connected to GND. Further, in the D / A conversion device of the present invention, the second current cell group has current values of (1/2) · I, (1/4) · I, (1/8)
.I, ... (1/2 ^nm ) .. It is composed of (n−m) constant current sources having I. One of these constant current sources is connected to GND and the other end is connected to the switch circuit group. It can also be configured to be connected.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a D / A conversion device according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2, the D / A conversion device of this embodiment is a current cell matrix type D / A conversion device having a 9-bit digital signal input.
Bits are converted by a current cell matrix of 3 bits in row direction × 3 bits in column direction, and the remaining lower 3 bits are converted by a weighted constant current source.

This D / A converter is an EEPROM-X which is a ROM capable of electrically erasing the memory circuits X and Y.
2 and EEPROM-Y3
It has the same components as those of the / A converter, and the same components are designated by the same reference numerals. Further, the connection of each component is almost the same as that of the conventional D / A conversion device, and therefore detailed description thereof will be omitted.

Differences between the D / A converter of the first embodiment and the conventional D / A converter will be described below.

In the D / A converter of this embodiment, the X decoder 2 '(see FIG. 6) has an EE having a memory circuit control signal input 118 and a data input bus 117.
It is replaced with PROM-X2, and the data output (108-115) of this EEPROM-X2 is all current cells (1-
The column selection control signal is input to 0 to 1-63). (FIG. 6 showing a conventional D / A conversion device)
Then, the same column as the current cell (1-56) is GND116.
It was. ) Similarly, for the Y decoder 3 ', similarly, the memory circuit control signal 118 and the data input / output bus 117 are used.
Replaced with an EEPROM-Y3 having
ROM-Y3 data output (100-A, 100-B,
..., 107-A, 107-B), and the row selection control signal is input to all the current cells (1-0 to 1-63). (In FIG. 6, the current cell (1
-63) and the same row as the current cell (1-7) have one row selection control signal input at the VDD power supply terminals 28 and G, respectively.
It was ND116. ) Next, D / A of this embodiment
Conversion device EEPROM-X2 and EEPROM-Y
The function of No. 3 will be described.

These EEPROM-X2 and EEP
Writing data to and deleting data from ROM-Y3
This is performed by the signal operation of the memory circuit control signal 118 and the data input / output bus 117. The EEPROM is a non-volatile memory that retains data even when the power is turned off, so if you store data to improve the characteristics, the EEPROM
Data rewriting to M is not necessary. Further, since data can be electrically erased, arbitrary data can be rewritten after packaging.

Next, the selection order of the current cells (1-0 to 1-63) in the first current cell group 1 of the D / A converter of the present invention and the distribution of the integral linearity error due to the selection order are described. Explain the relationship. First, the selection order of the current cells (1-0 to 1-63) is initially as described below.

The upper 6-bit digital input signal is (D
8, D7, D6, D5, D4, D3) = (1,1,1 ,,
In the case of 1, 1, 1), only the current cell (1-0) is selected and the current is drawn from the analog output terminal 29 side.

Then, one step down, the digital input signals (D8, D7, D6, D5, D4, D3) = (1,
1, 1, 1, 1, 0), the current cell (1
-0) and only the current cell (1-1) are selected, the digital signal sequentially changes by one step, and the digital input signal becomes (D8, D7, D6, D5, D4, D3) =
When it becomes (0, 0, 0, 0, 0, 1), the current cells (1-0 to 1-62) are selected, and finally the digital input signal is (D8, D7, D6, D5). , D4, D
3) = (0,0,0,0,0,0),
All of the current cells (1-0 to 1-63) are selected.

That is, the selection order of the current cells is such that the digital input signals are (D8, D7, D6, D5, D4, D3).
= (1,1,1,1,1,1,1) → (0,0,0,0,
When changing to 0, 0) at every step, the current cells (1-0, 1-1, 1-2, 1-3, ...
.., 1-63) are sequentially added, that is, the analog output voltage Vout is selected to decrease.

Next, the integral linearity error characteristic when manufacturing currents of the current values of the constant current sources of the respective current cells are varied with respect to the selection order of these current cells will be described.

Regarding the above-mentioned current cell selection order, assuming that this selection method is a statistically optimum current cell selection order in consideration of manufacturing, in the case of the conventional example, the X and Y decoder 2 is used. The signal connection wirings from'and 3'to the first current cell group 1 were rearranged to cope with this.

However, as in the conventional example, the method of improving the integral linearity error characteristic by the wiring rearrangement based on the statistical data has one sample even if the best statistical measure is taken. For one, it cannot be said that the order of selecting the current cells is appropriate.

The reason for this is that each current cell (1-0 to 1-6
It will be described with reference to FIG. 4 which shows what [LSB] the current value error distribution situation of 3) corresponds to.

In FIG. 1, the X-axis direction indicates the row direction of the first current cell group 1, and the Y-axis direction indicates the column direction. That is, in the same form as the arrangement of the current cells shown in FIG. 1, the ideal current I is set to 0, and the error is shown. As for the unit, the length corresponding to the mark on the vertical axis corresponds to an error of 1 LSB. FIG. 4A is a result of measurement performed on a certain manufactured one-chip IC.
(B) shows statistically the error results of each of a large number of manufactured chips.

The ideal current value I of each current cell (1-0 to 1-63) and each statistical current cell (1-0 to 1) in manufacturing.
It is assumed that the variation distribution of −63) is shown as in FIG. At this time, the integrated linearity error of the present D / A converter when the current cells for converting the upper 6 bits are sequentially selected from the current cell (1-63) to the current cell (1-0) is as follows. The locus indicated by a white circle “◯” 57 shown in FIG. 5 is obtained. However, in FIG. 5, the conversion error of the lower 3 bits is neglected because it is considerably small. In addition, the ideal conversion for integrated linearity error is usually one in which the zero-scale and full-scale offsets are ignored, and a straight line is drawn between the analog output at the zero point and the analog output at the full-scale point of the actual sample. There is. This ideal conversion is shown by the broken line 60 in FIG. The statistical integral linearity error for the wavy line is about (-4 LSB) to + (2
It becomes a value within LSB).

However, the current value of the constant current source of each current cell (1-0 to 1-63) for a certain sample is shown in FIG.
In the case of the case of (a), if the same order as the selection order of the current cells described immediately above is used, the integrated linearity error distribution of this sample is as shown by the polygonal line 58 in FIG. The integrated linearity error at this time is about (-5 LSB) ~
(+ 3LSB). In the conventional example, this FIG.
The sample having the characteristic of (a) cannot improve the integral linearity any more, and may become a defective sample.

However, regarding the row selection order of the first current cell group 1, the digital input signals of the upper 6 bits are (D8, D7, D6, D5, D4, D3) = (1,
In the case where the current cell (1-0, 0, 0, 0, 0, 0, 0) changes in every step, the current cell (1-0,
1-1, 1-2, 1-3, ..., 1-
63) to which current values are sequentially added, in other words, current cells (1-0 to 1-7, 1-8 to 1-45, 1-16).
~ 1-23, 1-24 to 1-34, 1-32 to 1-3
9, -40 to 1-47, 1-48 to 1-55, 1-56
Although the order is from 1 to 63, the wavy line 5 in FIG.
The selection order of the current cells shown by 9 is (1-0 to 1-
7), (1-32 to 1-39), (1-8 to 1-1)
5), (1-40 to 1-47), (1-24 to 1-3)
1), (1-16 to 1-23), (1-48 to 1-5)
5) and (1-56 to 1-63), the integrated linearity error of this sample is about (-3 LSB) to +
(3 LSB).

EEPR so that the selection order is as described above.
Data is stored in OM-Y3, and further EEPROM
By storing the optimum current cell selection order for -X2 as well, the integrated linearity error can be further improved and a highly accurate digital-analog conversion characteristic can be obtained.

Next, referring to FIG. 3 showing the configuration of the D / A converter of the second embodiment of the present invention, in this second embodiment, the EEPROM as the memory circuit in the first embodiment is used. The configuration is replaced with SRAM, and the other components are the same as the components of the first embodiment, so they are only shown in the figure, and a detailed description of the configuration and operation is omitted.

Since this SRAM has a high data access time, it is possible to perform digital-analog conversion at a higher speed than in the first embodiment.

[0061]

As described above, according to the current cell matrix type D / A converter of the present invention, the rows and columns of the current cells input to each current cell in the current cell group which is in charge of the conversion of the higher order bits are conventionally provided. The decoding circuit that was generating the selection control signal of No. 1 was replaced with a storage circuit capable of storing arbitrary data, such as an EEPROM or SRAM. This memory circuit capable of writing and reading arbitrary data makes it possible to arbitrarily set the selection order of each current cell in the current cell group for each IC chip.

Therefore, it is possible to obtain an optimum current cell selection sequence that improves the digital-analog conversion characteristics for each IC chip.

In the D / A converter of the present invention, the data indicating the selection order of each constant current cell can be arbitrarily set for each IC chip, and this data can be written after packaging. Therefore, it is possible to improve the deterioration of the characteristics caused by the assembly of the package and the like, which leads to the improvement of the yield.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a D / A conversion device according to a first embodiment of the present invention.

FIG. 2 is a first D / A conversion device according to the related art and the present invention.
Current cells (1-0 to 1-63) constituting the current cell group 1 of
It is an internal block diagram.

FIG. 3 is a block diagram showing a configuration of a D / A conversion device according to a second embodiment of the present invention.

FIG. 4 is an LSB of a current value error distribution state of each current cell (1-0 to 1-63) in the first embodiment shown in FIG. 1;
It is a figure which shows (ideal amount by the change of the minimum bit) equivalent.

5 is a graph in which the current value error distribution of the current cell shown in FIG. 4 is sequentially added up to each current cell (1-0 to 1-63).

FIG. 6 is a block diagram showing a configuration of a conventional D / A conversion device.

[Explanation of symbols]

1 1st current cell group 1-A logical relation circuit 1-B logical sum circuit 1-0 to 1-63 current cell 2,3 memory circuit 2'X decoder 3'Y decoder 4-18A, B, 30-32 Latch circuit 49 to 27 Digital input terminal 28 Power supply terminal 29 Analog output terminal 33 to 35, 1-C constant current source 42 Load resistance 43 to 45, 1-D switch circuit 46 Y latch circuit group 47 X latch circuit group 48 Second Latch circuit 49 Switch circuit group 56 Second current cell group 57 Statistical integral linearity error distribution 58 Certain one sample integral linearity error distribution (before optimizing selection order of current cells) 59 Certain sample Integral linearity error distribution (after optimizing the selection order of current cells) 60 Statistical ideal integral linearity error straight line 61 One sample ideal integral linearity error straight line 10 ~106,100-A, 100-B~107-
A, 107-BY Y decoder output signal 108 to 115 X decoder output signal 116 Ground (GND) 117 Data input / output bus 118 Storage circuit control signal

Claims (8)

[Claims] 1. An n-bit (n is a positive integer) digital input terminal, an analog output terminal, and an upper-order m bits (m is a positive integer) of the n-bit digital input terminals are input and an arbitrary number is input. , A first latch circuit group having all outputs of the memory circuit as inputs, and a first current cell group having all outputs of the first latch circuit group as control signal inputs And a second (n−m) -bit data input terminal of the n-bit digital input terminal
Latch circuit group, and a second current cell group connected to the power supply terminal and the analog output terminal via a switch circuit group that uses the outputs of all the second latch circuit groups as control signal inputs. A D / A conversion device characterized by the following. 2. The D / A conversion device according to claim 1, wherein the integers n and m have a relationship of n ≧ m and m ≧ 2. 3. The m-bit input is divided into upper Y bits and lower X bits (X and Y are natural numbers), and
D / according to claim 2, characterized in that m = X + Y.
A converter. 4. The memory circuit comprises a first memory circuit having the X-bit as an address input and a second memory circuit having the Y-bit as an address input. 3. The D / A conversion device described in 3. 5. The first latch circuit group includes an X-latch circuit group that receives all outputs of the first memory circuit, and a Y-latch circuit that receives all outputs of the second circuit. The D / A conversion device according to claim 4, wherein the D / A conversion device comprises a group. 6. The first current cell group is composed of current cells having (2 ^m ) or (2 ^m-1 ) current values I (real number), and these current cells are the Y-cells. 6. The D / A converter according to claim 5, wherein the output of the latch circuit group is used as a row selection control signal and the output of the X-latch circuit group is used as a column selection control signal in a matrix. 7. The two-input logical product, wherein the current cell has an arbitrary output of the Y-latch circuit group as one input and another input as an arbitrary output of the X-latch circuit group,
A two-input logical sum that uses the output of the two-input logical product as one input and the other input as an arbitrary output of the Y latch circuit group, and a switch circuit that uses the output of the two-input logical sum as a control signal input The current value I, one of which is connected to the power supply terminal and the analog output terminal and the other of which is connected to GND through
A constant current source having a (real number) and a D / A conversion device. 8. The second current cell group comprises a current value (1 /
2) ・ I, (1/4) ・ I (1/8) ・ I, ・ ・ ・ (1
/ 2 ^nm ) · I (n−m) constant current sources, each of which has one end connected to GND and the other end connected to the switch circuit group. The D / A conversion device according to claim 1, 2, 3, 4, 5, 6 or 7.