JPH07106451A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a two layer gate structure having high flatness and charge retaining characteristics. CONSTITUTION:A P<+> impurity diffusion region 5 is formed in stripe in an N well 2 made in a P type semiconductor substrate 1. A trench coated with an oxide 8 is made therein and polisilicon 10 is deposited in the trench. A polycrystalline or single crystal silicon semiconductor layer 12 is provided thereon with source region 14 and drain region 16 being formed therein through an insulation film 11. A metallization 20 of Al, for example, is further formed thereon through an interlayer insulation film 17, e.g. BPSG. A diffusion region 5 and the polysilicon 10 serve as a control gate and a floating gate, respectively. Since the transistor region is formed flat, the wiring region is also formed flat. Furthermore, infiltration of contaminants can be prevented effectively because the gate is embedded in the semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

The present invention is excellent in charge retention property,
The present invention relates to a non-volatile semiconductor memory device having a two-layer gate structure in which almost no steps are recognized and wiring is highly reliable.

[0002]

2. Description of the Related Art A conventional rewritable nonvolatile semiconductor memory device includes an EPROM for erasing stored contents by ultraviolet rays.
(Erasable Programmable Read Only Memory) and electrically erasable EEPROM (Electorically Erasable Pro)
grammable Read Only Memory). EEPROM
Various cell transistors have been proposed, but one of them is an EPROM which is superior in terms of integration degree.
There is a cell transistor of the same simple two-layer polysilicon structure as the above. This cell transistor having a two-layer polysilicon structure has a two-layer polysilicon gate composed of a floating gate for holding charges on a semiconductor substrate and a control gate that functions as a gate electrode. EP
The difference between the ROM cell and the EEPROM cell is that the EPRO
Since M is erased by irradiating it with ultraviolet rays, for example, 0.
In case of 6 μm design rule, the gate oxide film is 16
The thickness of the gate oxide film is about 10 nm, but the EEPROM has a gate oxide film thinner than that of the EPROM because it electrically erases.
It is about nm. The present invention is such a 2
A new cell structure is proposed in order to solve the problems of the non-volatile memory cell transistor having the layer polysilicon structure.

Next, a conventional non-volatile memory cell having a two-layer polysilicon structure will be described with reference to FIGS. 36 to 43. FIG. 36 shows a two-layer polysilicon type EEPROM.
2 is a cross-sectional view showing the structure of the completed memory cell in which a first gate insulating film 104, a floating gate 114, a second gate insulating film 107 and a control gate 115 are sequentially formed on a p-type silicon wafer 101. It is formed by stacking. An insulating film 111 of silicon oxide is formed on the silicon wafer including the control gate 115.
Are formed. In the p-type silicon wafer 101, an n-type source region 112 and an n-type drain region 113 are formed between the stacked bodies. FIG. 37 (a) is a plan view of a silicon wafer in which this EEPROM is formed, and FIG. 36 is a sectional view taken along the line AA '. 37 (b), 38 (a), and 38 (b) are cross-sectional views taken along lines BB ', CC', and DD 'of FIG. 37 (a), respectively. Memory cell transistors are repeatedly formed on the silicon wafer 101. FIG. 37
In (a), the insulating film 111 is omitted. Source area 1
Since 12 is formed commonly to each memory cell, it is formed in a stripe shape on the surface region of the silicon wafer 101.
Each source region 112 is formed on a silicon wafer, and is sandwiched by gate stacks that are also strip-shaped. The gate stack includes a floating gate 114 formed on the first gate insulating film 104 and a second gate formed on the floating gate 114.
The control gate 115 is formed via the gate insulating film 107. Floating gate 114
Are divided into memory cells, but the control gates 115 are connected in a strip shape. The drain region 113 is centered on the gate stack and is the source region 1
12, facing the floating gate 114
In the same manner as above, each memory cell is separated.

Next, referring to FIGS. 37 to 43, this E
The manufacturing process of the EPROM will be described. First, the element region 1 is formed on the p-type silicon 101 by the LOCOS (selective oxidation) method.
02 and the field oxide film 103 are formed in a strip shape (see FIG. 3).
9). Next, a silicon oxide film is grown to a thickness of about 12 nm as the first gate insulating film 104, and the first polycrystalline silicon 105 is deposited thereon by CVD or the like. This will later become the floating gate 114. Next, patterning is performed using a photoresist, and division 106 of the floating gate in the word line direction is performed by etching (FIG. 40). Next, an interlayer insulating film to be the second gate insulating film 107 is formed, and the second polycrystalline silicon 10 is formed thereon.
8 is deposited by CVD or the like. This polycrystalline silicon 1
08 will later become a control gate. Further, the photoresist 109 is patterned to form a two-layer gate, and the second polycrystalline silicon 108, the insulating film 107, and the first polycrystalline silicon 105 are sequentially etched (FIGS. 41 and 42). As a result, as shown in FIG. 43, the control gate 115 and the floating gate 11 perpendicular to the forming direction of the field oxide film 103 are formed.
4 is formed. Then, the photoresist 109 is removed, and the photoresist 110 is patterned again so as to have a boundary within the width of the strip-shaped control gate. Then, the oxide film is selectively etched to form a source line pattern. This is the SAS (Self-Aligned S
ource) technology (Fig. 43).

Next, the photoresist 110 is removed,
After forming the silicon oxide film 111 on the entire surface, a photoresist (not shown) for ion-implanting into the source region 112 is applied and patterned, and, for example, As is ion-implanted and thermally diffused to form the source diffusion region 112. Form. Further, the drain region 113 is formed by the same method (FIGS. 37 and 38). After that, an insulating film 110 is formed on the entire surface of the semiconductor substrate 101 including the gate stacked body by a well-known technique. Further, although not shown, a contact is opened in this insulating film 101 and an electrode is wired. Since the memory cell thus formed has a two-layer polysilicon gate on the semiconductor substrate, a step difference of about several hundred nm is generated between the surface of the semiconductor substrate and the uppermost portion of the memory cell. The gate pitch on the side sandwiching the diffusion region 112 is the minimum pitch. Therefore, it is not easy to flatten a pattern having this severe aspect with an interlayer insulating film, and poor flatness causes some reliability and performance problems.

One of the problems is that it is difficult to maintain the data stored in the cell transistor, that is, the charge retention characteristic in a good condition. In the cell transistor having the above structure, "1" and "0" are distinguished between the state where electrons are injected into the floating gate and the state where electrons are discharged, and data is stored. Here, if positive mobile ions and the like come near the floating gate into which electrons have been injected through the interlayer insulating film, electrons will escape from the footing gate, and this mobile ion will be apparently attracted. The amount of electrons in the floating gate changes and the data changes. In order to prevent such behavior, it is a major problem to prevent impurities from entering the interlayer insulating film. Therefore, the inter-layer insulating film of the non-volatile device is required to have good quality so as to prevent impurities from entering. However, in this cell structure having poor flatness, not only the quality of the interlayer insulating film but also the good coverage are required, and the selection of the interlayer insulating film is limited accordingly.

In the aluminum (Al) wiring formed on the interlayer insulating film, this step causes a focus blur of the photoresist between A1 running on the gate laminated body and A1 running on the semiconductor substrate, and reliability of the wiring. Reduce sex. For non-volatile memory, multi-layer wiring technology has become an essential technology because high performance such as high speed is required. When introducing this multi-layer wiring technology, this poor flatness becomes a greater problem. Further, since the elements are separated by the field oxide film in the cell transistor, the source region 11 is formed as described in FIGS.
Although the SAS technique is used for forming 2, the structure in which the source and gate boundaries of the cell transistor have a step on the semiconductor substrate surface of the source and the channel below the gate when the field oxide film is removed by this method. Therefore, there is a problem in that the gate oxide film thickness in the vicinity of the gate end portion that is oxidized during post-oxidation varies and the cell erase characteristic also varies. Further, since the semiconductor substrate has the diffusion region, the junction capacitance of the diffusion region causes a voltage drop, which is a serious problem.

[0008]

In such a conventional cell transistor having a two-layer polysilicon structure, the floating gate 114 for holding charges is covered with the insulating films 107 and 111. Is not sufficient, impurities enter from the insulating film covering the floating gate, and the charge retention characteristic deteriorates. In order to improve the charge retention characteristics, it is necessary to optimize the insulating film, but poor flatness limits the selection of the insulating film. Further, in the aluminum wiring formed on the insulating film, the step causes the photoresist to be defocused, which reduces the reliability of the wiring. Further, if the multi-layer wiring technology is introduced, the decrease in reliability becomes more remarkable. In this conventional structure, in order to form the source region, the field oxide film for element isolation is formed by the SAS technique. However, in this method, the gate oxide film thickness varies and the threshold value after data erasure varies. Occurs. Also, since the semiconductor substrate has a diffusion region, its junction capacitance is large and causes a voltage drop. The present invention has been made under such circumstances, and provides a non-volatile semiconductor memory device in which the floating gate has excellent charge retention characteristics, and a step is hardly recognized, and wiring is highly reliable.

[0009]

According to the present invention, at least a part of a two-layer gate stacked body is formed in a silicon single crystal semiconductor substrate, and polycrystalline silicon or a polycrystalline silicon is formed on the semiconductor substrate above the gate stacked body. It is characterized in that a single crystal silicon semiconductor layer is formed and a source region, a drain region, and a channel region between the source / drain regions are formed therein. That is, the nonvolatile semiconductor memory device of the present invention comprises: a semiconductor substrate having a groove formed on its main surface; and a first insulating film formed on the main surface of the semiconductor substrate and covering at least the bottom of the groove. An impurity diffusion region that is formed inside the semiconductor substrate and is in contact with the bottom of the groove through the first insulating film, and that is used as a control gate, and is embedded in the groove to form a floating gate. Used as a conductive layer, a second insulating film formed on the semiconductor substrate and covering at least the conductive layer, and a conductive layer formed on the main surface of the semiconductor substrate and separated from the conductive layer by the second insulating film. A source / drain region formed in the semiconductor layer and a semiconductor layer in contact with the source / drain region;
The first feature is that the channel region between the drain regions is formed in a region above the conductive layer.

A semiconductor substrate, an impurity diffusion region formed on the main surface of the semiconductor substrate and used as a control gate, and a first insulating layer formed on the main surface of the semiconductor substrate and covering at least the impurity diffusion region. A membrane,
A conductive layer formed on the impurity diffusion region via the first insulating film and used as a floating gate, and a second conductive layer formed on the main surface of the semiconductor substrate and covering at least the conductive layer. An insulating film; a semiconductor layer formed on the main surface of the semiconductor substrate and in contact with the conductive layer via the second insulating film; and source / drain regions formed in the semiconductor layer, A second feature is that the channel region formed between the source / drain regions is formed in a region above the conductive layer. Further, a semiconductor substrate having a groove formed on its main surface, a first insulating film formed on the main surface of the semiconductor substrate and covering at least the bottom of the groove, and the first insulating film in the groove. First formed on the film and used as a control gate
Of the conductive layer, a second insulating film formed on the main surface of the semiconductor substrate and covering at least the first conductive layer, and the second insulating film in the groove. A second conductive layer used as a gate, a third insulating film formed on the main surface of the semiconductor substrate and covering at least the second conductive layer, and a third conductive film on the main surface of the semiconductor substrate. A semiconductor layer formed and in contact with the conductive layer via the third insulating film, and a source / drain region formed in the semiconductor layer, the channel region between the source / drain regions, The third characteristic is that the conductive layer is formed in a region above the conductive layer.

[0011]

Since the floating gate is covered with the single crystal silicon or the single crystal silicon which is the semiconductor substrate and the polycrystalline silicon film on the single crystal silicon, the penetration of impurities can be greatly controlled. In addition, since the conventional two-layer gate stacked body having a large step is embedded in the single crystal silicon or the single crystal silicon and the polycrystalline silicon on the single crystal silicon, the surface thereof is flat and the insulating film functions as There is no need to consider the performance for maintaining the charge retention characteristics, and there is no limitation on the coverage. As a result, the focus blur of the aluminum wiring is eliminated. Further, since the source region is formed in the polycrystalline silicon film deposited and formed on the semiconductor substrate, it can be formed by patterning with a mask, and it is not necessary to use the SAS technique. Therefore, the variation in the threshold value after the data is erased can be reduced. Since the source / drain regions are formed in the deposited polycrystalline silicon film, the junction capacitance can be reduced.

[0012]

Embodiments of the present invention will be described with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a cell transistor of a semiconductor memory device (EEPROM) in which metal wiring such as aluminum is formed, FIG. 9 is a perspective view of the semiconductor memory device, and FIG. 4 is a modification of FIG. Plan view, FIG. 2 to FIG.
FIG. 4A is a sectional view and a plan view of the manufacturing process of the EEPROM. For example, a p-type silicon substrate is used as the semiconductor substrate 1, and an N well 2 in which cell transistors are formed therein
Are formed by a known technique. The surface of the semiconductor substrate 1 is thermally oxidized to form a dummy oxide film 3 having a thickness of, for example, about 100 nm. Then, a photoresist 4 having a predetermined pattern is formed on the oxide film 3 in a stripe shape. Then, boron (B) is doped to form a p-type diffusion region 5 serving as a control gate in the N well 2. The control gate 5 is formed in a strip shape on the semiconductor substrate 1. A plurality of N wells 2 are repeatedly formed in the semiconductor substrate 1, and a plurality of strip-shaped control gates 5 are formed in each well. That is, the control gates 5 are formed in stripes on the semiconductor substrate 1 according to the stripe pattern of the photoresist 4 (FIG. 2). FIG. 2B is a sectional view taken along the line BB ′ of the plan view of the semiconductor substrate 1 of FIG. 2A in which the photoresist and the oxide film are omitted.

Next, the photoresist 4 is stripped and removed, and a photoresist 6 having another pattern is newly formed on the dummy oxide film 3. Using the photoresist 6 as a mask, the diffusion region 5 of the control gate of the semiconductor substrate 1 is etched by anisotropic etching or the like to form a groove 7 in each diffusion region 5 repeatedly. Later, a floating gate of polycrystalline silicon is formed in this groove. 3B is a sectional view taken along the line BB ′ of the plan view of the semiconductor substrate 1 of FIG. Since the groove 7 is formed inside the control gate 5, the region where the floating gate formed in the groove 7 and the control gate overlap is constant, so that the coupling ratio is constant even if there is some mask misalignment. Can be In addition, FIG. 4 is another example in which the shape of the floating gate is different from that of FIG. Groove 7 of FIG. 3 (a)
Is formed in the control gate 5, and the groove 7 in FIG. 4 is wider than the control gate 5, but no significant difference is observed in the action and effect. Next, the photoresist 6 and the dummy oxide film 3 are peeled off and removed from the semiconductor substrate 1, and an insulating film 8 such as a silicon thermal oxide film and a polycrystalline silicon film 9 are formed on the entire surface of the semiconductor substrate 1 ( FIG. 5A).

Next, the polycrystalline silicon film 9 is etched back so that only the polycrystalline silicon embedded in the groove 7 remains on the semiconductor substrate 1. The polycrystalline silicon in the trench 7 becomes the floating gate 10. The floating gate 10 may be made into n-type by diffusing impurities by a method such as ion implantation or phosphorus diffusion, or a method of depositing a doped poly such as phosphorus may be used. After that, an insulating film 11 such as a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 to completely cover the floating gate 10 (FIG. 5).
(B)). Next, the semiconductor layer 1 made of a polycrystalline silicon film
2 is deposited on the entire surface of the semiconductor substrate 1 by CVD or the like. Since the floating gate 10 is completely covered with the single crystal silicon semiconductor substrate 1, the intrusion of impurities is sufficiently prevented. In addition, since the two-layer gate stacked body is embedded in the single crystal silicon semiconductor substrate, the surface becomes flat, and thereafter the deposition of an insulating film such as an interlayer insulating film and the reliability of metal wiring such as aluminum are improved. Leads to improvement (Fig. 5
(C)).

Next, a photoresist 13 is formed on the semiconductor layer 12 made of a polycrystalline silicon film, and using this as a mask, a region such as As is formed in the region between the floating gates 10 of the semiconductor layer 12 made of the polycrystalline silicon film. Impurities are doped by a method such as ion implantation to form the n-type region 14 (FIG. 6A), and then the impurities are thermally diffused to n.
The mold source region 14 is formed in a strip shape. After forming the n-type region 14, the photoresist 13 is peeled and removed, and another photoresist 15 is formed instead on the semiconductor layer 12 made of a polycrystalline silicon film. Then, for example, an impurity such as As is doped by ion implantation at a position symmetrical to the source region 14 around the region of the semiconductor layer 12 made of a polycrystalline silicon film on the floating gate 10 and then n-doped.
The mold region 16 is formed (FIG. 6B). Then, as shown in FIGS. 7 and 8, the n-type region 16 is thermally diffused to separately form the n-type drain region 16 for each cell.

The PN junction capacitance formed in the semiconductor layer 12 made of a polycrystalline silicon film is smaller than the conventional one, and the voltage drop is small. FIG. 7 is a plan view of a semiconductor substrate on which a semiconductor layer 12 made of a polycrystalline silicon film is formed, and FIGS. 8A and 8B are B- of this plan view.
It is sectional drawing which follows the B'line and CC line. In the plan view, the inside of the semiconductor substrate 1 is not shown, but the floating gates 10 buried in the grooves are separated into cells to form two lines. The controller formed underneath
The lugate 5 is continuously formed in a strip shape. The source region 14 is continuously formed in a strip shape, and the cell portion is wide. The drain region 16 is independent for each cell. Although not shown, the channel region may be doped with impurities in order to set the threshold value after ultraviolet irradiation to a desired value. It is also possible to perform ion implantation of boron or the like into the region 18 between the drain region and the adjacent drain region for electrical element isolation. Photoresist 1
After removing 5, the semiconductor layer 12 made of a polycrystalline silicon film is covered with an interlayer insulating film 17 as shown in FIG. Next, the interlayer insulating film 17 is patterned using a photoresist to form a contact hole exposing the drain region, and then a metal electrode 20 of aluminum or the like is wired and electrically connected to the drain region 16. For the electrodes of the control gate 5, low resistance electrodes can be obtained by making one contact with a plurality of cells. Since the electrode wiring is formed on the flat interlayer insulating film, patterning can be performed without focus deviation.

In the above example, the semiconductor layer 12 made of a polycrystalline silicon film in which the source / drain regions constituting the cell transistor are formed on the semiconductor substrate 1 is deposited on the entire surface of the semiconductor substrate. The semiconductor layer 12 made of a film is used as a source region, a drain region and a source /
It may be formed only in the channel region between the drain regions, and may be formed in a mesh shape on the semiconductor substrate 1. In this case, patterning with a photoresist is required, but the region 18 between adjacent drain regions is completely electrically isolated by the insulating film, and boron implantation for electrical isolation is not necessary. . FIG. 9 is a partial perspective view of the plan view of FIG. 7. In this figure, the semiconductor layer 12 made of a polycrystalline silicon film formed on the semiconductor substrate 1 and the source / drain regions formed therein are shown, and the interlayer insulating film and the like on the semiconductor layer 12 made of a silicon film are shown. Absent. The control gate 5 formed in the N well 2 of the semiconductor substrate 1 extends in the Y direction. The source region 14 formed in the semiconductor layer 12 made of a polycrystalline silicon film also extends in the Y direction like the control gate 5. The drain region 16 is formed independently for each cell transistor. Since the drain line to be a bit line is orthogonal to the control gate 5, it is wired in the X direction by a metal wiring such as Al. An impurity having a conductivity type opposite to that of the drain region is implanted into the region 18 between the drain region in the Y direction and the adjacent drain region to electrically isolate the drain and the drain region. Also, if polycrystalline silicon is not formed in this region 18, an insulator will be formed, so that complete electrical isolation is possible.

Next, a second embodiment will be described with reference to FIGS. The process up to the step of forming the control gate 5 on the semiconductor substrate 1 is the same as that shown in FIG. As the semiconductor substrate 1, for example, a p-type silicon substrate is used, and the N well 2 in which the cell transistor is formed is formed by a well-known technique. The surface of this semiconductor substrate 1 is thermally oxidized to form an oxide film 3. After that, oxide film 3
A photoresist 4 having a predetermined pattern is formed on the p-type and is doped with B to form a control gate p.
A type diffusion region 5 is formed in the N well 2. The control gate 5 is formed in a strip shape on the semiconductor substrate 1. A plurality of N wells 2 are repeatedly formed in the semiconductor substrate 1, and a plurality of strip-shaped control gates 5 are formed in each well. That is, the control gates 5 are formed in stripes on the semiconductor substrate 1 according to the stripe pattern of the photoresist 4 (FIG. 2). After that, the photoresist 4 and the dummy oxide film 3 are peeled off and removed, and a new silicon oxide film 26 is grown in a subsequent step (2 in FIG. 11A).
8), a thicker film or a film having a similar thickness is formed.
An island-shaped oxide film 26 is formed in the area for forming the gate (FIG. 10). FIG. 10B is a sectional view taken along the line BB ′ of FIG.

Next, after removing the photoresist 27, the silicon single crystal film 2 is formed on the exposed surface of the semiconductor substrate 1.
8 is deposited by epitaxial growth to a height lower than that of the oxide film 26 or to the same height (FIG. 10C). Since a single crystal does not normally grow on the oxide film 26, the island-shaped oxide film 26 is arranged on the silicon single crystal film 28. After that, the oxide film 26 is removed by etching to form the groove 29. Next, the surface of the silicon film 28 is covered with the insulating film 30, and the polycrystalline silicon film 31 is formed thereon (FIG. 11B). The polycrystalline silicon film 31 is etched back and left only in the openings 29 of the silicon film 28, and this is used as the floating gate 10. The floating gate 10 is made n-type by a method such as ion implantation, phosphorus diffusion, or doped poly such as phosphorus. After that, the insulating film 32 is formed in the same manner as in the first embodiment to cover the floating gate 10 (FIG. 11).
(C)). Next, the semiconductor layer 12 made of a polycrystalline silicon film is formed on the insulating film 32, and the polycrystalline silicon film is doped with impurities to form the n-type source / drain regions 14 and 1.
6 is formed (FIGS. 12 and 13). FIG. 12 is a plan view of the semiconductor substrate, and FIGS. 13 (a) and 13 (b) are sectional views taken along the line BB 'and the line CC'. After that, although not shown, an interlayer insulating film is formed on the polycrystalline silicon film 12, a contact hole is formed in this insulating film, and further electrode wiring is performed.

Next, a third embodiment will be described with reference to FIGS. 14 to 19. FIG. 14B is a sectional view taken along the line BB ′ of the plan view shown in FIG. A p-type silicon substrate is used, in which cell transistors are formed N
Well 2 is formed by a well-known technique. The surface of the semiconductor substrate 1 is thermally oxidized to form, for example, a dummy oxide film 3 having a thickness of about 100 nm. Then, a photoresist 4 having a predetermined pattern is formed on the oxide film 3 and the oxide film 3 is patterned. Then, the surface of the semiconductor substrate 1 is exposed in a stripe shape (FIG. 14). Then, using the photoresist 4 as a mask, the main surface of the semiconductor substrate 1 is etched by anisotropic etching or the like to repeatedly form a plurality of strip-shaped grooves 35 for each N well 2 (FIG. 15A). . Figure 15
FIG. 14A is a sectional view taken along the line BB ′ of FIG. After forming the groove 35, an insulating film 36 is formed on the surface of the semiconductor substrate 1 by, for example, thermal oxidation. Next, the entire surface of the semiconductor substrate 1 is covered with polycrystalline silicon, and the polycrystalline silicon film 37 is formed in a band shape in the groove 35 by etching back, and this is used as the control gate 5. After that, an insulating film 38 such as silicon oxide is formed on the control gate 5 (FIG. 15B).

After that, polycrystalline silicon 39 is deposited again on the semiconductor substrate 1 (FIG. 16A), and etching back is performed to form the polycrystalline silicon film 39 in the groove 35 in a state of being arranged on the insulating film 38. (FIG. 16B). Next, a photoresist 40 is applied on the semiconductor substrate 1 and patterned to form a pattern having stripes in a direction orthogonal to the strip of the polycrystalline silicon film 37 forming the control gate 5. Then, using the photoresist 40 as a mask, the polycrystalline silicon film 39 buried in the groove is divided into cells, and the floating gate 10 is formed.
To form. The polycrystalline silicon film 39 is used as the control gate 5 in a strip shape. The control gate 5 and the floating gate 10 are made into n-type by doping impurities by a method such as ion implantation, phosphorus diffusion or doped poly. In this embodiment, the control gate 5, the insulating film 38, and the floating gate 10 are sequentially deposited in the same groove, so that the coupling ratio of the memory cell becomes constant. After being removed by etching,
Grooves 41 are formed (FIGS. 17 and 18). FIG. 17
17A is a plan view of the semiconductor substrate, FIG. 17B is a sectional view taken along the line DD ′ of this plan view, and FIG. 18B is a sectional view taken along the line CC ′ of this plan view. It is a figure and FIG.
FIG. 4 is a sectional view taken along the line BB ′ of this plan view. The photoresist 40 is formed on the surface of the semiconductor substrate 1 from above the semiconductor substrate 1.
Then, an insulating film 42 such as a silicon oxide film is newly formed on the surface of the semiconductor substrate 1 and is etched back to form the insulating film 4 in the groove 41 between the floating gates 10.
3 is embedded (FIG. 19).

Through the above steps, a flat semiconductor substrate surface is formed. Although not shown, the following steps are the same as those in the first and second embodiments described above. That is, after covering the floating gate 10 with an insulating film, a polycrystalline silicon film as a semiconductor layer is deposited on the entire surface of the semiconductor substrate 1 by CVD or the like. Then, a source / drain region and a channel region therebetween are formed in this semiconductor layer. Since the floating gate 10 is covered with this polycrystalline silicon film, the intrusion of impurities is sufficiently prevented. Further, since the two-layer gate laminated body is embedded in the single crystal silicon semiconductor substrate 1, the surface becomes flat and the deposition of an insulating film such as an interlayer insulating film thereafter and the reliability of metal wiring such as aluminum are reliable. It leads to improvement of sex.

Next, a fourth embodiment will be described with reference to FIGS. 20 (a) is a plan view of a semiconductor substrate having cell transistors formed thereon, and FIG.
FIG. 4 is a sectional view taken along the line BB ′ of this plan view. The X direction in the drawing is the pit line direction, and the Y direction is the word line direction. Also in this embodiment, similarly to the first embodiment, first, the N well 2 is formed on the semiconductor substrate 1, and the cell transistor is formed in the N well 2 region. Photoresist 4
5 is applied and formed on the semiconductor substrate 1, and the floating gate formation region is patterned (FIG. 20). next,
Grooves 44 are formed by etching. Polycrystalline silicon is embedded in the groove 44 in a later step to form a floating gate. Next, with the photoresist 45 being patterned, impurities such as boron are implanted to form the impurity diffusion region 5 which will later become the control gate (FIG. 21). Through the above steps, the control gate and the floating gate are self-aligned. Therefore, misalignment is eliminated and the coupling ratio between the control gate and the floating gate becomes constant. FIG. 22
A perspective view of the semiconductor substrate at this stage is shown in FIG. Since the impurity diffusion region 5 needs to be connected in a band shape in the Y direction, that is, the word line direction, nitrogen annealing is performed after the impurity diffusion region 5 is formed, or a gate oxide film is formed in a later process or a source / drain region is formed. A thermal process for activation of ion implantation is used to connect the impurity diffusion regions 5 in the Y direction together. At this time, the adjacent X-direction impurity diffusion regions 5
Optimizes the distance between the impurity diffusion region and the impurity diffusion region (distance between grooves) so that they do not contact each other.

Further, as shown in FIG. 24B, if the impurity diffusion region 5 is ion-implanted in the Y direction (word line direction) at an implantation angle of, for example, 7 degrees, the impurity diffusion region 5 and the impurity diffusion region 5 are diffused. The distance D of the region 5 can be made small, and it becomes easy to connect the regions 5 in the subsequent heating process. After that, as shown in FIG.
6 is formed, and then the whole surface is covered with polycrystalline silicon 47. The polycrystalline silicon 47 is doped with impurities as in the first to third embodiments. In this embodiment, phosphorus is doped to form n-type polycrystalline silicon 47. After that, as shown in FIG. 23B, the polysilicon 44 is buried in the groove 44 by etching back to form the floating gate 10. After that, as shown in FIG. 24A, an insulating film 48 and polycrystalline silicon 49 to be a semiconductor layer forming source / drain regions and channel regions are deposited. The substrate surface is flattened by the above steps, and the subsequent steps are the same as those in the above-mentioned embodiment, and the same effect can be obtained. Also, the same can be applied to the variation in the devoted region of silicon for forming the channel in this embodiment.

Next, a fifth embodiment will be described with reference to FIGS. FIG. 25A is a plan view of a semiconductor substrate on which cell transistors are formed, where the X direction is the bit line direction and the Y direction is the word line direction. FIG. 25B is a sectional view taken along the line BB ′ of this plan view.
26 to 29 are plan views and cross-sectional views of the manufacturing process for explaining this portion. First, the N well 2 is formed on the semiconductor substrate 1, and the cell transistor is formed in the N well 2 region. The semiconductor substrate is oxidized, and the oxide film 3 is formed to be thicker than or equal to the thickness of the epi layer (55 in FIG. 26 (b)) grown in the subsequent step, and patterned to form the photoresist 53. It is formed by coating in the floating gate formation region (FIG. 25). Next, etching is performed to leave the oxide film 3 in a predetermined pattern of the photoresist 53 (FIG. 26A). Then photoresist 5
3 is peeled off, and a single crystal silicon single crystal film 55 is selectively deposited on the exposed portion of the silicon semiconductor substrate 1 (FIG. 26).
(B)). This can be achieved, for example, by epitaxial growth. When phosphine (PH ₃ ) or arsine (AsH ₃ ) is used as a doping gas during this epitaxial growth, P or As can be doped and an N type silicon single crystal film can be formed. The silicon single crystal film 55 is grown to a height lower than or equal to the height of the oxide film 3. After that, the oxide film 3 can be thinned to 10 nm by etching to form the island-shaped groove 54. After that, the patterned photoresist 56 covers the portions other than the strip-shaped portion including the groove 54 (FIG. 27).

Thereafter, a p-type impurity such as boron is implanted to form an impurity diffusion region 57 (FIG. 28 (a)). Figure 2
28 is a sectional view taken along the line AA ′ of FIG.
A sectional view taken along the line is FIG. The impurity diffusion region 57 is formed in a strip shape in the N well in the substrate and in the N type doped silicon single crystal film 55. Next, polycrystalline silicon 59 is deposited (FIG. 29) and then etched back to fill the trench with polycrystalline silicon. The buried island-shaped polysilicon becomes the floating gate 10, and the impurity diffusion region becomes the control gate 5 (see FIG. 23). The subsequent steps are the same as those in the second embodiment, and the floating gate 10 and the insulating film 3 are formed as shown in FIG.
After being covered with 2, the semiconductor layer 12 is formed, and further subsequent steps are performed.

The photoresist 5 described with reference to FIG.
By making the width of the strip 6 thicker or thinner than the groove 54, the contact area between the impurity diffusion region and the groove can be made constant even if there is some misalignment of the photoresist, and the cup of the floating gate and the control gate can be made uniform. The ring ratio can be kept constant. The polysilicon embedded as the floating gate is doped with impurities in the same manner as in the first to fourth embodiments. The subsequent steps are the same as those in Examples 1 to 4, and the same effect is obtained. Further, regarding the variation in the deposition region of silicon for forming the channel, the same thing can be considered in the fourth embodiment.

Next, the operation of the cell transistor of the nonvolatile semiconductor memory device of the present invention will be described. 1. For the case where the source / drain region is n-type. First, a description will be given with reference to FIG. The figure is a schematic cross-sectional view of a cell transistor. In this example, the control gate (word line) is of p-type. This cell transistor is basically an n-type transistor, and a floating gate formed below the transistor via an insulating film is an n-type and a p-type transistor formed below the floating gate via an insulating film. The control gate formed of the diffusion region in the N well of the semiconductor substrate is p-type. The above cell structure is the same as that of the first embodiment, but is also the same as that of the second and third embodiments.

Threshold voltage (Vth) of cell transistor
Is negative in both the written state and the erased state. Therefore, the read potential is the threshold voltage (Vth) in the written state.
And the intermediate potential of the threshold voltage in the erased state. In the case of writing, a negative potential is applied to the word line (Vg) connected to the control gate and a positive potential is applied to the bit line (Vd) connected to the drain region, and the source line (Vs) formed by the source region is opened ( open). The potential (Vwell) of the N well is set to 0V. Select a cell in which the word line and the bit line are orthogonal and select the flow
Electrons are extracted from the gate to the drain region by a tunnel current. When erasing, the channel region is set to the ground potential (Vs = Vd = 0V) and the N well (Vwell) is set.
Then, a positive high potential is applied to the control gate (Vg) to inject electrons from the channel region. For erasing, batch erasing or block erasing in well units is performed. In addition,
At the time of reading, if a positive potential (Vwell) is applied to the N well, the reading potential can be set to 0V.

Next, a case where the control gate is of n type will be described with reference to FIG. The cell transistor is
An n-type transistor is used and a p-type semiconductor substrate is used.
The threshold voltage (Vth) of this cell transistor is positive both in the written state and the erased state. The read potential is an intermediate potential between the threshold voltage in the written state (Vth and the threshold voltage in the erased state. In the case of writing, the word line (Vg) connected to the control gate is positive potential, the bit line A positive potential is also applied to (Vd) and the source line (Vs) is set to 0 V. A cell in which the word line and the bit line are orthogonal to each other is selected and electrons are extracted from the drain region to the floating gate. When biased in this way, some of the electrons accelerated in the pinch-off region near the drain become hot electrons, which are trapped by the n-type floating gate.When erasing, the source line (Vs) is set to a positive potential and word The line (Vg) is set to 0 V and the bit line (Vd) is opened, and then electrons are extracted to the sources collectively in the unit sharing the source region. It is removed by.

Next, with reference to FIG. 32, description will be made on a case where the control gate is of n type and a P well is formed on the semiconductor substrate. An n-type transistor is used as the cell transistor, and an n-type semiconductor substrate is used. In FIG. 31, only a positive potential can be applied to the word line (Vg), but a negative potential can be applied by inserting the P well in the semiconductor substrate. That is, the write operation is the same as in FIG. 31, but when erasing, the source line (Vs) is set to a positive potential, the word line (Vg) is set to a negative potential, and the bit line (Vd) is opened. Then, by setting the potential (Vwell) of the P well to a negative potential, electrons are extracted to the source in a unit sharing the source region, and erased at once. However, the absolute value of the potential of the P well must be larger than the absolute value of the potential of the word line (| Vwe
ll |> | Vg |). It is possible to erase in word line units,
It is not necessary to apply a high voltage to the source region.

2. When the source / drain region is p-type. In the cell transistor of FIG. 33, the control gate connected to the word line has an n-type. This cell transistor is based on a p-type transistor, and the floating gate formed below the transistor via an insulating film is n-type, and the p-type transistor formed below the floating gate via an insulating film. P of semiconductor substrate
The control gate composed of the diffusion region in the well is n-type. The P well is formed in the N well in the semiconductor substrate. That is, a double well is formed in the semiconductor substrate.

The threshold voltage (V
th) is positive both in the written state and the erased state. Therefore, the read potential is the threshold voltage (V
th) and the threshold voltage in the erased state. In the write operation, a positive potential is applied to the word line (Vg) connected to the control gate, a negative potential is applied to the bit line (Vd) connected to the drain region, and a source line (Vs) formed by the source region is formed. ) Is open (o
Pen) and the potential of the N well (VNwell) is
Leave at 0V. A cell in which a word line and a bit line are orthogonal to each other is selected, and electrons are injected from the drain region to the floating gate by a tunnel current. When erasing, the source / drain regions are grounded (Vs = Vd = 0).
V), and a negative potential is applied to the P well (VPwell) and the control gate (Vg) to extract electrons from the source / drain regions. VNwell is also set to 0V. For erasing, batch erasing or block erasing in well units is performed. When reading, a positive potential (V
well) is applied, the read potential can be set to 0V. In the erasing method, since a negative potential is applied to the control gate, it is necessary to put the cell region in the double well and electrically separate it from the peripheral portion.

Next, the case where the control gate connected to the word line is of p-type will be described with reference to FIG. This cell transistor is based on a p-type transistor, and the floating gate formed below the transistor via an insulating film is p-type, and a p-type semiconductor formed below the floating gate via an insulating film. The control gate composed of the diffusion region in the substrate is p-type. The threshold voltage (Vth) of this cell transistor is
Both the written state and the erased state are negative. Therefore, the read potential is an intermediate potential between the threshold voltage in the written state (Vth and the threshold voltage in the erased state. In the case of the writing operation, the word line (V) connected to the control gate.
g) and a bit line (Vd) connected to the drain region, a negative potential is applied to the source line (V
s) is set to 0V. A cell in which a word line and a bit line are orthogonal to each other is selected, and holes are injected from the drain region to the floating gate. That is, when biased in this way, some of the holes accelerated in the pinch-off region near the drain become hot holes, which are trapped by the floating gate. When erasing, the source line (Vs) is set to a negative potential, the word line (Vg) is set to 0V, and the bit line (Vd) is opened. Then, electrons are extracted to the source in a unit of sharing the source region, and erased collectively.

Next, with reference to FIG. 35, the case where the control gate is of p type and the N well is formed in the semiconductor substrate will be described. A p-type transistor is used as the cell transistor, and a p-type semiconductor substrate is used. In FIG. 31, only a negative potential can be applied to the word line (Vg), but N
A positive potential can be applied by putting the well in the semiconductor substrate. That is, the write operation is the same as in FIG. 34, but when erasing, the source line (Vs) is set to a negative potential, the word line (Vg) is set to a positive potential, and the bit line (Vd) is opened. Then, by setting the potential (Vwell) of the N well to a positive potential, electrons are extracted to the source in a unit of sharing the source region and erased collectively. However, the absolute value of the potential of the N well must be larger than the absolute value of the potential of the word line (| Vwell |
> | Vg |). It is possible to erase in word line units, and it is not necessary to apply a high voltage to the source region. As described above, in the present invention, either an n-type substrate or a p-type substrate can be used as the semiconductor substrate, and when the well is not used as the semiconductor substrate,
A cell transistor having a direct control gate is formed.

Since the source region is formed in the deposited semiconductor layer of polycrystalline or single crystal silicon, it can be formed by patterning using a mask, and it is not necessary to use the SAS technique. Therefore, the threshold value (Vt
The variation in h) is also small. Further, the source / drain regions can have a small junction capacitance when formed in the deposited polycrystalline silicon. The material of the control gate used in this embodiment is not limited to polycrystalline silicon, but may be silicide, refractory metal such as W, Mo, or Ti, silicide of these refractory metals, or a laminated body of polycrystalline silicon and silicide. is there.

[0037]

According to the present invention, since the floating gate is covered with the single crystal silicon by the above structure, for example, impurities from the BPSG film used as an interlayer insulating film can be prevented from entering the floating gate. It can be greatly restricted. Also, in the past, two-layer gates with large steps (floating gate / control gate)
Since it is embedded in the semiconductor substrate, the surface is flat, and as the function of the interlayer insulating film, it is not necessary to consider the characteristics for maintaining the charge retention characteristics, and the coverage is not limited. Focus blur in patterning of metal wiring is also eliminated.

[Brief description of drawings]

FIG. 1 is a sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view of a manufacturing process of the first embodiment.

FIG. 3 is a plan view and a sectional view of the manufacturing process of the first embodiment.

FIG. 4 is a plan view of the semiconductor substrate of the first embodiment.

FIG. 5 is a sectional view of a manufacturing process of the first embodiment.

FIG. 6 is a sectional view of a manufacturing process of the first embodiment.

FIG. 7 is a plan view of the manufacturing process of the first embodiment.

FIG. 8 is a sectional view of a manufacturing process of the first embodiment.

FIG. 9 is a plan view and a sectional view of the manufacturing process of the first embodiment.

FIG. 10 is a plan view and a sectional view of the manufacturing process of the second embodiment.

FIG. 11 is a sectional view of a manufacturing process of the second embodiment.

FIG. 12 is a plan view of the manufacturing process of the second embodiment.

FIG. 13 is a sectional view of a manufacturing process of the second embodiment.

FIG. 14 is a plan view and a sectional view of the manufacturing process of the third embodiment.

FIG. 15 is a sectional view of a manufacturing process of the third embodiment.

FIG. 16 is a sectional view of a manufacturing process of the third embodiment.

FIG. 17 is a plan view and a sectional view of the manufacturing process of the third embodiment.

FIG. 18 is a plan view and a sectional view of the manufacturing process of the third embodiment.

FIG. 19 is a plan view and a sectional view of the manufacturing process of the third embodiment.

FIG. 20 is a plan view and a sectional view of the manufacturing process of the fourth embodiment.

FIG. 21 is a sectional view of a manufacturing process of the fourth embodiment.

FIG. 22 is a perspective view of a semiconductor substrate according to a fourth embodiment.

FIG. 23 is a sectional view of a manufacturing process of the fourth embodiment.

FIG. 24 is a sectional view of a manufacturing process according to the fourth embodiment.

FIG. 25 is a plan view and a sectional view of the manufacturing process of the fifth embodiment.

FIG. 26 is a sectional view of a manufacturing process of the fifth embodiment.

FIG. 27 is a plan view of the manufacturing process of the fifth embodiment.

FIG. 28 is a sectional view of a manufacturing process of the fifth embodiment.

FIG. 29 is a sectional view of a manufacturing process according to the fifth embodiment.

FIG. 30 is an explanatory diagram of the operating principle of the present invention.

FIG. 31 is an explanatory diagram of an operating principle of the present invention.

FIG. 32 is an explanatory diagram of the operating principle of the present invention.

FIG. 33 is an explanatory diagram of the operating principle of the present invention.

FIG. 34 is an explanatory view of the operating principle of the present invention.

FIG. 35 is an explanatory diagram of the operating principle of the present invention.

FIG. 36 is a sectional view of a conventional nonvolatile semiconductor memory device.

37A and 37B are a plan view and a cross-sectional view of a conventional nonvolatile semiconductor memory device.

FIG. 38 is a sectional view of a conventional nonvolatile semiconductor memory device.

FIG. 39 is a plan view and a cross-sectional view of a manufacturing process of a conventional nonvolatile semiconductor memory device.

FIG. 40 is a plan view and a cross-sectional view of a manufacturing process of a conventional nonvolatile semiconductor memory device.

FIG. 41 is a plan view and a cross-sectional view of a manufacturing process of a conventional nonvolatile semiconductor memory device.

FIG. 42 is a cross-sectional view of manufacturing steps of a conventional nonvolatile semiconductor memory device.

FIG. 43 is a plan view and a cross-sectional view of a manufacturing process of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1 semiconductor substrate 2 N well 3 dummy oxide film 4, 6, 13, 15, 27, 34, 40, 45, 53
Photoresist 5 Control gate (impurity diffusion region) 7, 29, 35, 41, 44 Groove 8, 11, 26, 30, 32, 36, 38, 42, 4
3, 46, 48 Insulating film 9, 31, 37, 39, 47 Polycrystalline silicon film 10 Floating gate 12, 49 Semiconductor layer 14 Impurity diffusion region (source region) 16 Impurity diffusion region (drain region) 17 Interlayer insulating film 18 Semiconductor Region between the drain / drain regions of the layer 20 metal wiring 28 semiconductor epitaxial growth layer

Front page continuation (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/115 (72) Inventor Eiji Kamiya 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki City, Kanagawa Prefecture Toshiba Corporation In-house (72) Inventor Kazumi Amemiya, 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa, Ltd. Toshiba Research Institute Co., Ltd. (72) Inventor Tomoko Yamane, 25, Kawasaki-ku, Kawasaki-ku, Kanagawa, Japan 1 Toshiba Microelectronics Co., Ltd. In the company

Claims (3)

[Claims] 1. A semiconductor substrate having a groove formed on a main surface, a first insulating film formed on the main surface of the semiconductor substrate and covering at least a bottom portion of the groove, and formed inside the semiconductor substrate. An impurity diffusion region that is in contact with the bottom of the groove through the first insulating film and that is used as a control gate; and a conductive layer that is embedded in the groove and is used as a floating gate, A second insulating film formed on the semiconductor substrate and covering at least the conductive layer is in contact with the conductive layer formed on the main surface of the semiconductor substrate via the second insulating film. A semiconductor layer and a source / drain region formed in the semiconductor layer, wherein a channel region between the source / drain regions is formed in a region above the conductive layer. Nonvolatile semiconductor memory device. 2. A semiconductor substrate, an impurity diffusion region formed on the main surface of the semiconductor substrate and used as a control gate, and a first insulation formed on the main surface of the semiconductor substrate and covering at least the impurity diffusion region. A film, a conductive layer formed on the impurity diffusion region through the first insulating film and used as a floating gate, and formed on the main surface of the semiconductor substrate to cover at least the conductive layer. A second insulating film, a semiconductor layer formed on the main surface of the semiconductor substrate and in contact with the conductive layer via the second insulating film, and source / drain regions formed in the semiconductor layer And a channel region formed between the source / drain regions, the channel region being formed in a region above the conductive layer. 3. A semiconductor substrate having a groove formed on a main surface thereof, a first insulating film formed on the main surface of the semiconductor substrate and covering at least a bottom portion of the groove, and the first insulating film in the groove. A first conductive layer formed on the first insulating film and used as a control gate, and formed on the main surface of the semiconductor substrate, and at least the first conductive layer.
A second insulating film covering the conductive layer of the second insulating film, and the second insulating film in the groove.
A second conductive layer used as a gate, and at least the second conductive layer formed on the main surface of the semiconductor substrate.
A third insulating film covering the conductive layer, a semiconductor layer formed on the main surface of the semiconductor substrate, and in contact with the conductive layer via the third insulating film; A source / drain region formed, wherein a channel region between the source / drain regions is formed in a region above the conductive layer.