JPH07101414B2 - Parallel computer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer constituting a neural circuit retina type circuit.

2. Description of the Related Art Recently, parallel computers have been actively used for the purpose of performing multiple calculations. This parallel computer is known, for example, as shown in FIG. A conventional parallel computer will be described below with reference to FIG. FIG. 2 is a block diagram showing a configuration when a conventional parallel computer is flexibly applied. In FIG. 2, 1 is a memory that stores n learning data, 10 is a selector that selects any one of the n learning data stored in the memory, 11 is a switch with 1 input and m output, 12, 13 , 14 has internal parameters that can be modified from the outside, m neural circuit retina type circuits composed of one or more computers, 15 is an m-input 1-output switch, 9 is the input data It is a distributor that distributes to individual neural circuits and retinal circuits.

The operation of the parallel computer configured as described above will be described below. Here, m learning data are sequentially input to X1, ..., Xm, m neural circuits and retinal circuit are sequentially input to N.
1, ..., Nm. First, the learning data X1 is selected by the selector 10 from the memory 1 that stores m learning data,
The signal is output to N1 of the m neural circuit retina circuits by the switch 11. Neural circuit Retinal circuit N1 based on learning data X1
Learns, finds the internal parameter correction amount, and outputs the internal parameter correction amount to the switch 15. Switch 15
Outputs the internal parameter correction amount to each neural circuit retina type circuit 12, 13, 14 through the distributor 9. The neural circuit retina type circuits 12, 13 and 14 modify internal parameters based on the internal parameter modification amount. The above processing is performed on the learning data X2, ...
, Xm and neural circuit retinal circuit N2, ..., Nm are made to correspond in order. In this way, n stored in the memory 1
By repeating the operation of selecting m data from the data by the selector 10 and modifying the internal parameters of each neural circuit retinal circuit 12, 13, 14, the learning progresses and the internal parameters are sequentially modified. Go.

However, in the above configuration, when any one neural circuit retinal circuit is processing the learning data, the other (m-1) neural circuit retinal circuits are Since it is in the rest state, there is a problem that a plurality of neural circuit retina type circuits, that is, a plurality of computers forming a neural network cannot be effectively used. As described above, in the conventional neural circuit retinal circuit, the sequential processing for correcting the internal parameters for each given learning data is basic, and the learning is repeated by the number of data for learning many data. There is also a problem that learning speed is slow because it is necessary.

In view of the above problems, the present invention provides a plurality of neural circuit retinal circuits,
That is, the present invention provides a parallel computer having a configuration capable of effectively using a plurality of computers constituting a neural network.

Means for Solving the Problem The present invention selects m (m is a positive integer of 2 or more and n or less) learning data from n (n is an integer of 2 or more) learning data, and the remaining (n -M) means for leaving the learning data, and m neural network schematic circuits having internal parameters that can be modified by an internal parameter modification amount from the outside and configured by one or more computers, Means for distributing the m learning data to the m neural circuit retina circuits, means for collecting internal parameter correction amounts from the m neural circuit retina circuits, and the collected m internal parts Means for obtaining the average internal parameter correction amount by obtaining the average of the parameter correction amounts and means for distributing the average internal parameter correction amount to the m neural circuit retina circuits as the internal parameter correction amount are provided. It

Operation According to the present invention, according to the above configuration, first, m pieces of learning data are selected from n pieces of learning data, the m pieces of learning data are output to the m pieces of neural circuit retinal circuits, and then the respective neural circuits are output. In the retinal circuit, the internal parameter correction amount is obtained based on the learning data. Since the processing for obtaining the internal parameter correction amount is simultaneously performed in parallel in m neural circuit retina circuits, it is possible to obtain m internal parameter correction amounts.
The internal parameter correction amount output from each neural circuit retinal circuit is collected, and the average internal parameter correction amount is obtained by averaging them. Next, the average internal parameter correction amount is output to each neural circuit retinal circuit, and the internal parameter is corrected in each neural circuit retinal circuit based on the average internal parameter correction amount. As described above, since a plurality of internal parameter correction amounts can be simultaneously obtained by using a plurality of neural circuit retina type circuits, a plurality of neural circuit retina type circuits, that is, a plurality of neural circuit retina type circuits constituting The computer can be used efficiently.

Example One example of the present invention will be described below.

FIG. 1 is a block diagram showing the configuration of a parallel computer according to an embodiment of the present invention. In FIG. 1, 21 is a memory for storing n learning data, 22 is a selector for selecting m learning data from the n learning data stored in the memory,
23 is a distributor that outputs m learning data to m neural circuit retinal circuits, 24, 25 and 26 are neural circuit retinal circuits composed of one or more computers, and 27 is m neural circuits. Circuit retina type collector that collects the internal parameter modification amount output from the circuit, 28 is an averaging machine that calculates the average parameter modification amount from m internal parameter modification amounts, and 29 is the average parameter modification amount m neural circuit retinal formula It is a distributor that outputs to the circuit.

The operation of the parallel computer configured as described above will be described below.

First, from the n pieces of learning data stored in the memory 21, the selector 22 selects arbitrary m pieces of learning data.
At this time, the remaining (n−m) pieces of data are stored in the memory 21 as they are. The selected m learning data are output one by one to the m neural circuit retinal circuits by the distributor 29, and the internal parameter correction amount is obtained based on the learning data in the m neural circuit retinal circuits. Then, the m internal parameter correction amounts output from the m neural circuit retinal circuits 24, 25, 26 are collected by the collector 27. The collected m number of internal parameter correction amounts are averaged by the averaging machine 28 to obtain an average internal parameter correction amount. The average internal parameter correction amount is distributed by the distribution machine 29 to m neural circuit retina circuits 24, 25, Output to 26, each neural circuit retinal circuit
At 24, 25, and 26, the internal parameters are corrected based on the average internal parameter correction amount. By repeating the above processing, learning of each neural circuit retinal circuit 24, 25, 26 proceeds. In this case, how to select m learning data from n learning data by the selector 22 is not particularly specified. For example, in order to use all n learning data once, it may be selected regularly or in order. . When m is arbitrarily selected from n while repeating learning, there may be no problem in terms of accuracy of learning even if some data that are not selected remain.

EFFECTS OF THE INVENTION According to the present invention, a plurality of neural circuits are selected by selecting m learning data from n learning data and calculating m learning data at the same time by m neural circuit retina circuits. The calculation can be performed simultaneously by a plurality of computers forming the retinal circuit, which improves the efficiency of the calculation.

The present invention thus enables learning of neural circuit retinal circuits to proceed in parallel with a plurality of neural circuit retinal circuits,
Since learning with multiple learning data proceeds at the same time,
The learning speed is remarkably improved and its effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a parallel computer in one embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional parallel computer. 21 …… Memory, 22 …… Selector, 23 …… Distributor, 24,25,26
...... Neural circuit Retinal circuit, 27 …… Collector, 28 …… Average machine, 29 …… Distributor.

(72) Inventor Mie Saito 3-10-1 Higashisanda, Tama-ku, Kawasaki-shi, Kanagawa Matsushita Giken Co., Ltd. No. 10 No. 1 Matsushita Giken Co., Ltd. (56) Reference JP-A-1-237754 (JP, A)

Claims (1)

[Claims] 1. The learning data of m (m is a positive integer of 2 or more and n or less) is selected from n (n is an integer of 2 or more) learning data and the remaining (n−m) learning data is selected. The data is a means for leaving it alone, the internal parameters that can be modified by an external internal parameter modification amount, and the m neural circuit retina circuits that are composed of one or more computers, and the m learning data. To the m neural network retinal circuits, a means for collecting internal parameter modification amounts output from the m neural circuit retinal circuits, and an average of the m internal parameter modification amounts. A parallel computer comprising means for obtaining an average internal parameter correction amount by taking the above, and means for distributing the average internal parameter correction amount as the internal parameter correction amount to the m neural circuit retina circuits.