JPH0698310A - Picture coding/decoding device - Google Patents

Abstract

PURPOSE:To improve the efficiency by allocating a code to a degenerative picture element pattern obtained through reduction conversion. CONSTITUTION:An average value calculation circuit 103 calculates an in-block average value of an input picture signal of one frame, a compression processing circuit 104 applies compression processing of a difference PCM and the result is sent via a multiplexer 112. An average value from the circuit 103 is inputted also to a frame memory 105. The content of the memory 105 is referenced to be converted by a reduction conversion pattern generating circuit 106, and all conversion picture element patterns are generated and written in a pattern memory 107. The conversion picture element pattern stored therein is classified by a pattern classification circuit 108. That is, since similar patterns are degenerated into one pattern, the number of picture element patterns is considerably less. The pattern is written in a memory 110 via a sequencing circuit 109, a picture element pattern of a minimum error is selected by an optimum pattern selection circuit 111 and outputted via the multiplexer 112. Thus, the coding efficiency of a moving picture signal is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding device for still image signals or moving image signals and an image decoding device for decoding an image signal encoded by the encoding device, and more particularly to an image decoding device. The present invention relates to an image encoding / decoding device that utilizes the partial self-similarity of.

[0002]

2. Description of the Related Art Image in a system for transmitting or storing a still image signal such as a color facsimile or an electronic still camera system, and a system for transmitting or storing a moving image signal such as a TV telephone, a TV conference, a digital VTR, a video disc. There is a demand for an image encoding device that compresses a signal with high efficiency and encodes it, and an image decoding device that decodes an image signal encoded by the encoding device.

There are various types of image encoding apparatuses, and one recently proposed is an encoding method utilizing partial self-similarity of natural images. Partial self-similarity means that when a pixel pattern of a part X of an image is focused as shown in FIG. 5, a pixel pattern Y similar to this, that is, a pixel pattern having a similar pattern and a different scale is present in the same image. It is a property that exists. By performing encoding using this partial self-similarity, efficient compression becomes possible. For details of this encoding method, see, for example, the Image Coding Symposium (PCSJ91) 6-11.
It is described in "Image coding using fractal".

An outline of this encoding method will be described with reference to FIGS. 6 and 7. FIG. 6 shows an image to be encoded, and FIG. 7 shows an encoding algorithm. First, a plurality of (K × L) blocks Bkl (k = 1, 2, ..., L =) are encoded images.
1,2, ...), and the average pixel value γkl for each block
Is obtained, and a value obtained by subtracting the average value from the pixel value of each pixel is set as a search target pixel pattern (S1).

On the other hand, a larger block Dkl (hereinafter referred to as a large block) within the same image to be encoded is selected (S2). At this time, vectors αkl and βkl are obtained as information on the position and block size of the large block Dkl with respect to the block Bkl. Next, this large block Dkl
Image is sub-sampled so that it has the same number of pixels as the block Bkl, and spatially reduced (S3). Further, an average value of the reduced image is obtained, and this average value is subtracted from the pixel value of each pixel ( S4). Next, conversion of the pixel array such as rotation and horizontal inversion (S5), reduction in the pixel amplitude direction,
By sequentially performing pixel value conversion (S6) such as addition and subtraction,
Create a converted pixel pattern. In S5, one parameter εkl is selected from eight combinations of 90 ° rotation and left / right inversion.

Then, by calculating the squared error between this converted pixel pattern and the target pixel pattern obtained in S1, the similarity between the two patterns is investigated (S7), and this squared error is minimized. , S6, the reduction ratio (amplitude scaling) δkl is determined. When the absolute value of δkl is 1 or more, the process returns to S5, and when the survey of all eight εkl is completed, the process returns to S2.

Further, the above squared error is compared with a predetermined threshold value Z, and if it is equal to or larger than the threshold value, the process returns to S5, and if all eight εkl have been investigated, the process returns to S2. If the squared error becomes smaller than the threshold value Z, each parameter α at that time
The values of kl, βkl, γkl, δkl, εkl are sent as encoded output. If the squared error does not become smaller than the threshold value Z for all combinations of αkl, βkl, εkl, the parameter with the smallest error is determined as the encoded output. Actually, each code is quantized and then variable-length coded and output.

[0008]

In the above-mentioned conventional coding method, for each block of the input image signal,
Five parameters αkl, βkl, γkl, δkl, εkl are transmitted as encoded output. This encoding operation compares the input vector with the set of output vectors prepared as a codebook and transmits the code word of the output vector with the smallest error with respect to the input vector. Apply to the encoding method, assign codewords to all that can appear as converted pixel patterns (corresponding to output vectors) obtained by reduction conversion with each parameter, and assign them to blocks of input image signals (corresponding to input vectors) It is considered to be equivalent to transmitting the code representing the converted pixel pattern with the smallest error.

However, the converted pixel pattern obtained by reducing and converting the above parameter set is not actually evenly distributed in the space of the pixel pattern, and similar converted pixel patterns are concentrated. It is in a situation to appear. In the conventional coding method in which code words are assigned to all of the converted pixel patterns concentrated in a part as described above, a redundant code configuration is performed, and in this respect, there is room for improvement in coding efficiency. It is believed that there is.

On the other hand, when the above-mentioned conventional coding method is applied to the coding of a moving image signal, (a) each frame is treated as a still image and the above coding method is applied, (b) interframe difference Two methods of applying the above-mentioned coding method to an image or a motion compensation inter-frame difference image can be considered. However, since the method of (a) does not use the correlation between the frames of the image, the coding efficiency cannot be sufficiently improved. The method (b) has a problem that the partial self-similarity of the inter-frame difference image is smaller than that of the original input moving image signal, so that a sufficient effect cannot be obtained.

It is an object of the present invention to provide an image coding / decoding device capable of further improving the coding efficiency in a coding system utilizing partial self-similarity of images.

[0012]

In order to solve the above-mentioned problems, the present invention classifies all converted pixel patterns obtained by reduction conversion according to a predetermined rule to reduce the number of patterns and reduce the degenerate pixel pattern. The main point is to improve coding efficiency by creating and ordering so that the image patterns are evenly distributed in the pixel space and codes are appropriately assigned.

That is, the image coding apparatus according to the present invention comprises a block dividing means for dividing an input image signal input in frame units into a plurality of blocks, and the input image for each block divided by the block dividing means. Average value calculation means for calculating the average value of the pixel values of the signal, storage means for storing the information of the average value calculated by the average value calculation means in frame units, and information of the average value stored in the storage means , A plurality of conversion pixel patterns that are generated by the pattern conversion means, and a plurality of conversion pixel patterns that are generated by the pattern generation means are classified and reduced to a number smaller than the conversion pixel patterns. Pattern classification means for creating a degenerate pixel pattern,
Ordering means for ordering a plurality of degenerate pixel patterns created by the pattern classifying means and giving a pattern number, and the block division of the input image signal among the plurality of degenerate pixel patterns ordered by the ordering means. Pattern selecting means for selecting the degenerate pixel pattern having the smallest error for the blocks divided by the means, the pattern number of the degenerate pixel pattern selected by the pattern selecting means, and the average value calculated by the average value calculating means. And a means for outputting the information as a coded output.

On the other hand, the image decoding device corresponding to this image coding device classifies all the converted pixel patterns obtained by the reduction conversion according to the same rule as the image coding device and performs ordering to classify the image coding device. Decoding is performed by selecting the degenerate pixel pattern corresponding to the pattern number sent from the.

That is, the image decoding apparatus stores the information of the average value in the encoded output transmitted from the image encoding apparatus in frame units, and the information of the average value accumulated in the storing means. , A plurality of conversion pixel patterns that are generated by the pattern conversion means, and a plurality of conversion pixel patterns that are generated by the pattern generation means are classified and reduced to a number smaller than the conversion pixel patterns. A pattern classifying unit for creating a degenerate pixel pattern, an ordering unit for ordering a plurality of degenerate pixel patterns created by the pattern classifying unit and giving a pattern number, and a plurality of degenerate pixels ordered by the ordering unit. Select the degenerate pixel pattern corresponding to the pattern number in the coded output from the patterns and decode it. Characterized in that it comprises a pattern selecting means for obtaining.

In addition, according to the present invention, when combined with motion-compensated inter-frame prediction, which is an effective technique for improving the coding efficiency in moving picture coding, the types of converted pixel patterns are reduced using a motion-compensated inter-frame prediction signal to perform ordering. After that, the outline is to select the one that is closest to the input moving image signal from the plurality of degenerate pixel patterns and transmit the pattern number.

That is, this image coding apparatus divides an input moving image signal input in frame units into a plurality of blocks, a block divided by the block dividing means, and a locally decoded signal of the previous frame. And a motion vector detecting means for detecting a motion vector by comparing with the motion vector detecting means, and a motion compensating means for selecting a locally decoded signal of the previous frame indicated by the motion vector detected by the motion vector detecting means to create a motion compensated interframe prediction signal. The inter-frame prediction means, the pattern creating means for performing a reduction conversion on the locally decoded signal of the previous frame to create a plurality of converted pixel patterns, and the plurality of converted pixel patterns created by the pattern creating means for the motion Reduced to a number smaller than the converted pixel pattern compared to the compensation inter-frame prediction signal Pattern selecting means for selecting a plurality of degenerate pixel patterns, ordering means for ordering a plurality of degenerate pixel patterns selected by this means and giving pattern numbers, and a plurality of ordering means for ordering the plurality of degenerate pixel patterns. Pattern selecting means for selecting a degenerate pixel pattern having the smallest error with respect to a block divided by the block dividing means of the input image signal among degenerate pixel patterns, and a pattern of the degenerate pixel pattern selected by the pattern selecting means And a means for outputting information of the motion vector detected by the motion vector detecting means as an encoded output.

On the other hand, the decoding device corresponding to this image coding device creates a motion-compensated inter-frame prediction signal from the decoded signal of the previous frame based on the motion vector in the coded output transmitted from the image coding device. A motion-compensated inter-frame predicting means, a pattern creating means for creating a plurality of converted pixel patterns by performing reduction conversion on the decoded signal of the previous frame, and a plurality of converted pixel patterns created by the pattern creating means. Pattern selecting means for selecting a plurality of degenerated pixel patterns degenerated to a number smaller than the converted pixel pattern, as compared with the motion compensation inter-frame prediction signal;

The ordering means for ordering a plurality of degenerate pixel patterns selected by this means and giving a pattern number, and the plurality of degenerate pixel patterns ordered by the ordering means, are included in the encoded output. And a pattern selection unit for selecting a degenerate pixel pattern corresponding to the pattern number to obtain a decoded output.

[0020]

As described above, according to the present invention, all the conversion pixel patterns that can appear by classifying the conversion pixel patterns obtained by the reduction conversion and reducing the number to make the degenerate pixel patterns, and assigning codes to these degenerate pixel patterns. The code length of the code assigned to the pixel pattern (the pattern number of the degenerate pixel pattern) can be shortened as compared with the conventional encoding method in which the code is assigned to, and highly efficient encoding / decoding is performed.

Further, even when the motion compensation interframe predictive coding system is combined with the coding system utilizing the self-similarity of images, the conversion pixel pattern is classified by using the motion compensation interframe prediction signal. As a result, it is possible to perform encoding / decoding with high encoding efficiency.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of an image coding apparatus according to the first embodiment of the present invention, and FIG.
3 is a block diagram showing the configuration of an image decoding device corresponding to the image encoding device of FIG.

The image coding apparatus shown in FIG. 1 includes a frame memory 101, a blocking circuit 102, and an average value calculating circuit 1.
03, compression processing circuit 104, frame memory 105, reduction conversion pattern creation circuit 106, first pattern memory 107, pattern classification circuit 108, ordering circuit 10.
9, a second pattern memory 110, an optimum pattern selection circuit 111 and a multiplexer 112.

In FIG. 1, an input image signal input on a frame-by-frame basis is first stored in a frame memory 101 and then divided by a blocking circuit 102 into a plurality of blocks which are units of encoding. At the time of encoding, the average value of pixel values of each block of the image signal of each block divided by the block formation circuit 102 (hereinafter, referred to as intra-block average value) is transmitted one frame ahead. That is, the average value calculation circuit 103 calculates the average value in the block for the input image signal of one frame, and further the compression processing circuit 1
After being subjected to compression processing such as DPCM (differential PCM) by 04, it is transmitted to the transmission line or the recording medium via the multiplexer 112.

The in-block average value calculated by the average value calculation circuit 103 is also input to the frame memory 105 and stored as it is arranged in the frame. After the data of the intra-block average value for one frame is stored in the frame memory 105, the reduction conversion pattern creation circuit 106 performs the reduction conversion with reference to the contents of the frame memory 105 to obtain a conversion pixel pattern. Everything that is possible is created and written to the first pattern memory 107.

Here, the reduction conversion is performed by reducing a part X of an image larger than the encoding target block Y, as shown in FIG.
This is a process of converting into a block having the same size as Y by a conversion including rotation, and its algorithm is as described in FIG. 7. That is, the reduced conversion pattern creation circuit 1
At 06, the encoding algorithm shown in FIG. 7 is executed. However, in this embodiment, the average value γkl in S1 of FIG.
Since the average value calculation circuit 103 performs the calculation of, the reduced conversion pattern generation circuit 106 performs the remaining steps S2 to S7.

In the above-mentioned document, the five parameters (block position αkl, block size βkl, average value γkl, amplitude scaling δkl, rotation εkl) generated as shown in FIG. 7 by this reduction conversion are transmitted. In the method of this embodiment, the average value γkl is calculated by the average value calculation circuit 103 and transmitted in advance as described above, and therefore it is not necessary to send it again. The pattern memory 107 stores all converted pixel patterns defined by the set of these parameters.

The plurality of converted pixel patterns stored in the pattern memory 107 in this way are included in the pattern classification circuit 108.
It is input to and classified into several. That is, comparing all the converted pixel patterns stored in the pattern memory 107, it is often the case that a plurality of similar patterns exist. The pattern classification circuit 108 performs a process of degenerating such a plurality of similar converted pixel patterns into one common pattern. That is, the number of converted pixel patterns actually used by this process is reduced to a number of pixel patterns that is significantly smaller than the original converted pixel patterns stored in the pattern memory 107. The converted pixel pattern after the degeneracy is referred to as a degenerate pixel pattern.

Next, the plurality of degenerate pixel patterns thus obtained are input to the ordering circuit 109, where they are ordered so that the same correspondence is performed on the decoding device side, and then the second degenerate pixel pattern is set. It is written in the pattern memory 110. As an ordering method, for example, the order of magnitude of the (1,1) component of the vector components in the block (when the (1,1) components have the same value, further (1,2)
It is sufficient to adopt a component that can perform the same ordering according to the same rule in the encoding device and the decoding device, such as using components ...

The degenerate pixel pattern written in the pattern memory 110 is input to the optimum pattern selection circuit 111, and is compared with the pixel pattern of the block of the input image signal from the blocking circuit 102 from which the average value is subtracted. As a result, the degenerated pixel pattern with the smallest error is selected for the block of the input image signal. Then, the information of the pattern number of the selected degenerate pixel pattern is output from the optimum pattern selection circuit 111, and is transmitted to the transmission line or the recording medium via the multiplexer 112.

Next, the image decoding apparatus shown in FIG. 2 will be described. This image decoding device includes a demultiplexer 2
01, a frame memory 202, a reduced conversion pattern creation circuit 203, a first pattern memory 204, a pattern classification circuit 205, an ordering circuit 206, a second pattern memory 207, a pattern selection circuit 208, and a frame memory 209.

A signal transmitted from the image coding apparatus of FIG. 1 via a transmission line or a recording medium is input to the demultiplexer 201, and the in-block average value and the pattern number information are separated. The information on the separated average value in the block is stored in the frame memory 202, and one frame image of the average value is formed in the frame memory 202.

The path from the frame memory 202 to the second pattern memory 207, that is, the frame memory 202
-> Reduced conversion pattern creation circuit 203-> first pattern memory 204-> pattern classification circuit 205-> ordering circuit 2
06 → second pattern memory 207 operates as follows: frame memory 105 → reduction conversion pattern creating circuit 106 → first pattern memory 107 in the image coding apparatus of FIG.
→ pattern classification circuit 108 → ordering circuit 109 → second
The operation of the pattern memory 110 is completely the same. As a result, the same degenerate pixel patterns as the contents of the second pattern memory 108 in FIG. 1 are stored in the second pattern memory 207 in exactly the same order.

Then, with reference to the contents of the second pattern memory 207, the pattern selecting circuit 208 performs a process of associating the pattern number sent from the demultiplexer 201 with the degenerate pixel pattern. By adding the average value of the block to this, the pixel pattern of each block is decoded and formed. This pixel pattern is sequentially written in the frame memory 209 and is restored in the frame memory 209 as one frame of image signal data. The above is the flow of the overall processing through the image encoding device in FIG. 1 and the decoding device in FIG.

In the image decoding apparatus of FIG. 2, the pattern selection circuit 208 performs the decoding by replacing the pattern number from the image coding apparatus with the pixel pattern. However, as another decoding method, the pattern is selected. Decoding may be performed by iterative transformation by the method described in the above-mentioned document using parameters corresponding to pixel patterns indicated by numbers. That is, for example, the five parameters αk
After subsampling from the image signal of the large block specified by αkl and βkl among l, βkl, γkl, δkl, and εkl, and performing average value separation, pixel array conversion based on εkl, δ
Pixel value conversion based on kl is sequentially performed, and finally the in-block average value γkl is added to decode the pixel pattern of the block Bkl.

When the first embodiment is applied to the coding / decoding of a moving image signal, the pattern memory is not updated frame by frame, but is periodically updated every plural frames. The same contents of the pattern memory may be used during the period of the plurality of frames. If you do this,
The calculation load required for conversion pixel pattern creation → classification (degeneration) → ordering can be reduced, and the amount of hardware can be reduced.

Various methods of classifying the converted pixel patterns in the pattern classifying circuits 108 and 205 can be considered. For example, a method is conceivable in which all the converted pixel patterns stored in the pattern memory 107 are clustered by a codebook creation algorithm (eg, LBG algorithm) used in vector quantization.

As a sub-optimal method, initial clustering in which each element of a block is roughly scalar-quantized is prepared, and a finite number of patterns are selected in descending order of the number of elements belonging to each cluster. Can also be considered. According to the latter method, clustering can be sequentially performed for each block of the input image signal, and the first pattern memories 107 and 204 can be omitted. In this case, the final pattern output may be the center of gravity of each cluster, for example.

Next, a second embodiment in which the present invention is applied to moving picture coding / decoding will be described. FIG. 3 is a block diagram showing the configuration of the transmission side of the image encoding device in the embodiment, and FIG. 4 is a block diagram showing the configuration of the image decoding device corresponding to the image encoding device of FIG. Unlike the first embodiment, this embodiment performs motion-compensated interframe prediction and is applied only to moving images. Regarding the motion-compensated interframe prediction, for example, "Multidimensional signal processing of TV images" written by Takahiko Fukibuki (Nikkan Kogyo Shimbun, November 5, 1988)
It is described in various documents such as Chapter 6 and Chapter 7 of the Japanese issue).

In FIG. 3, the input moving image signal input in units of frames is first divided into a plurality of blocks by the block forming circuit 301. The divided image signal of each block is branched into two, one of which is the motion vector detection circuit 30.
Entered in 2. The motion vector detection circuit 302 compares the locally decoded signal of the previous frame accumulated in the frame memory 303 with each block of the input image signal, calculates the motion amount that gives the smallest prediction error, and calculates the optimum motion amount. It is detected as a motion vector. The detected motion vector is encoded by the variable length encoding circuit 310 and transmitted to the transmission line or the recording medium via the multiplexer 311.

Further, the detected motion vector is given to the frame memory 303 as a part of the address and used for generating a motion compensation (MC) inter-frame prediction signal. On the other hand, in addition to this, from the locally decoded signal of the previous frame accumulated in the frame memory 303, all conversion pixel patterns are created in the reduction conversion pattern creation circuit 304 by the reduction conversion according to the algorithm shown in FIG.
Pattern memory 305. Note that the reduced conversion pattern creation circuit 304 in this embodiment may also perform the calculation processing of the average value γkl in S1 of FIG. 7, unlike the first embodiment.

When the MC interframe prediction signal generated for each block of the input moving image signal is output from the frame memory 303, the pixel pattern accumulated in the pattern memory 305 in the pattern selection circuit 306 and the MC interframe prediction signal. Are compared, and a plurality of predetermined pixel patterns are selected in order from the one with the smallest error as the degenerate pixel pattern, and these degenerate pixel patterns are ordered by the ordering circuit 307 in order from the one with the smallest error. It is stored in the pattern memory 308. The ordering is necessary for the same reason as in the first embodiment, but in this case, the order of increasing the error from the MC inter-frame prediction signal is set.

Next, the optimum pattern selection circuit 309 compares the block of the input moving image signal with the degenerate pixel pattern stored in the pattern memory 308, and selects the pixel pattern with the smallest error. Then, the information of the pattern number of the degenerated pixel pattern selected from the optimum pattern selection circuit 309 is output and transmitted to the transmission line or the recording medium via the multiplexer 311.

Since the degenerate pixel patterns are ordered in ascending order of error from the MC inter-frame prediction signal, the pattern number information is transmitted by variable length coding in which shorter numbers are assigned shorter codes. Is desirable. The degenerated pixel pattern selected by the optimum pattern selection circuit 309 is also sent to the frame memory 303, and the information of the locally decoded signal is updated.

On the other hand, in the image decoding apparatus shown in FIG. 4, the information of the motion vector and the pattern number is obtained by the demultiplexer 401 from the signal transmitted from the image encoding apparatus of FIG. 3 via the transmission line or the recording medium. To be separated. The motion vector information is used as part of the address in the frame memory 403 to create the MC inter-frame prediction signal as in the image encoding device.

The operation from frame memory 403 → reduced conversion pattern creation circuit 404 → first pattern memory 405 → pattern selection circuit 406 → ordering circuit 407 → second pattern memory 408 is performed by the frame in the image coding apparatus in FIG. The operation is the same as that of the memory 303, the reduced conversion pattern creation circuit 304, the first pattern memory 305, the pattern selection circuit 306, the ordering circuit 307, and the second pattern memory 308. As a result, the same degenerate pixel patterns as the contents of the second pattern memory 308 in FIG. 3 are stored in the second pattern memory 408 in the same order.

Then, in the pattern selection circuit 409, the second
The decoded image signal is formed by referring to the contents of the pattern memory 408 and associating the pattern number sent from the demultiplexer 201 with the degenerate pixel pattern. This decoded image signal is also sent to the frame memory 402 and updated as a new decoded image signal.

Also in the second embodiment, as described in the first embodiment, the update in the pattern memory does not have to be performed for each frame. The amount of wear can also be reduced.

[0050]

As described above, according to the present invention, in the coding system utilizing the partial self-similarity of images,
Converted pixel patterns obtained by reduction conversion are classified by the encoding device and the decoding device according to the same rule to create degenerate pixel patterns in which the number of patterns is significantly reduced, and codes are assigned to these degenerate pixel patterns for transmission. As a result, it is possible to provide an image encoding / decoding device having higher encoding efficiency than ever before.

Further, according to the present invention, when combined with the moving picture coding using the motion-compensated inter-frame prediction, the motion-compensated inter-frame prediction signal is used to classify the converted pixel patterns, and similarly the degenerate pixel pattern is used. By creating and assigning codes, it is possible to further improve the coding efficiency of the moving image signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image coding apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image decoding apparatus according to the embodiment.

FIG. 3 is a block diagram showing the configuration of a moving picture coding apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a moving picture decoding apparatus according to the embodiment.

FIG. 5 is a diagram for explaining partial self-similarity of images.

FIG. 6 is a diagram showing a state of block division of an image to be encoded in an encoding method using partial self-similarity of images.

FIG. 7 is a diagram showing an encoding algorithm of the same encoding method.

[Explanation of symbols]

101 ... Frame memory 102 ... Blocking circuit 103 ... Average value calculating circuit 104 ... Compression processing circuit 105 ... Frame memory 106 ... Reduction conversion pattern creating circuit 107 ... Pattern memory 108 ... Pattern classification circuit 109 ... Ordering circuit 110 ... Pattern memory 111 ... Optimal pattern selection circuit 112 ... Multiplexer 201 ... Demultiplexer 202 ... Frame memory 203 ... Reduction conversion pattern creation circuit 204 ... Pattern memory 205 ... Pattern classification circuit 206 ... Ordering circuit 207 ... Pattern memory 208 ... Pattern selection circuit 209 ... Frame memory 301 ... Blocking circuit 302 ... Motion vector detection circuit 303 ... Frame memory 304 ... Reduction conversion pattern creation circuit 305 ... Pattern memory 306 ... Pattern selection circuit 307 ... Ordering circuit 308 ... Pattern memory 309 ... Optimal pattern selection circuit 310 ... Variable length coding circuit 311 ... Multiplexer 401 ... Demultiplexer 402 ... Variable length decoding circuit 403 ... Frame memory 404 ... Reduced conversion pattern creation circuit 405 ... Pattern memory 406 ... pattern classification circuit 407 ... ordering circuit 408 ... pattern memory 409 ... pattern selection circuit

Claims (4)

[Claims] 1. A block dividing means for dividing an input image signal input in frame units into a plurality of blocks, and an average value of pixel values of the input image signal is calculated for each block divided by the block dividing means. An average value calculation means, a storage means for storing the information of the average value calculated by the average value calculation means in frame units, and a plurality of conversions by reduction conversion with reference to the information of the average value stored in the storage means. A pattern creating means for creating a pixel pattern, and a pattern classifying means for classifying a plurality of converted pixel patterns created by the pattern creating means and creating a plurality of degenerate pixel patterns degenerated to a number smaller than the converted pixel patterns. , The order of assigning pattern numbers to the plurality of degenerate pixel patterns created by the pattern classifying means Attaching means, and pattern selecting means for selecting a degenerate pixel pattern having the smallest error with respect to a block divided by the block dividing means of the input image signal among a plurality of degenerate pixel patterns ordered by the ordering means, An image coding apparatus comprising: a pattern number of the degenerate pixel pattern selected by the pattern selecting means and means for outputting information of the average value calculated by the average value calculating means as an encoded output. 2. An accumulating means for accumulating the information of the average value in the encoded output transmitted from the image encoding device according to claim 1 in frame units, and the information of the average value accumulated in the accumulating means. A pattern creating unit for creating a plurality of converted pixel patterns by referring to reduction conversion, and a plurality of degenerate units that classify the plurality of converted pixel patterns created by the pattern creating unit and reduce the number to a smaller number than the converted pixel patterns. A pattern classifying unit for creating a pixel pattern, an ordering unit for ordering a plurality of degenerate pixel patterns created by the pattern classifying unit and giving a pattern number, and a plurality of degenerate pixel patterns ordered by the ordering unit. Pattern for obtaining a decoded output by selecting a degenerate pixel pattern corresponding to the pattern number in the coded output And an image decoding device. 3. A block division means for dividing an input moving image signal input on a frame-by-frame basis into a plurality of blocks, and a motion vector by comparing the blocks divided by the block division means with a locally decoded signal of the previous frame. A motion vector detecting means for detecting the motion vector, and a motion compensating interframe predicting means for selecting a locally decoded signal of the previous frame indicated by the motion vector detected by the motion vector detecting means to create a motion compensated interframe predicted signal, A pattern creating unit that creates a plurality of converted pixel patterns by performing reduction conversion on the locally decoded signal of the previous frame, and a plurality of converted pixel patterns created by the pattern creating unit as the motion-compensated interframe prediction signal. By comparison, a plurality of degenerated pixel patterns degenerated to a number smaller than the converted pixel pattern Pattern selecting means for selecting, a plurality of degenerate pixel patterns selected by this means, and an ordering means for giving a pattern number to the plurality of degenerate pixel patterns, and the input among the plurality of degenerate pixel patterns ordered by the ordering means. Pattern selecting means for selecting a degenerate pixel pattern having the smallest error with respect to the block divided by the block dividing means of the image signal, pattern number of the degenerate pixel pattern selected by the pattern selecting means, and the motion vector detecting means. And a means for outputting the information of the motion vector detected by the above as a coded output. 4. A motion-compensated inter-frame prediction means for creating a motion-compensated inter-frame predicted signal from a decoded signal of a previous frame based on the motion vector in the coded output transmitted from the image coding apparatus according to claim 3. A pattern creating means for creating a plurality of converted pixel patterns by performing reduction conversion on the decoded signal of the previous frame; and a plurality of converted pixel patterns created by the pattern creating means as the motion-compensated interframe prediction signal. By comparison, pattern selecting means for selecting a plurality of degenerate pixel patterns degenerated to a number smaller than the converted pixel pattern, and a plurality of degenerate pixel patterns selected by this means are sequenced and a pattern number is given. Ordering means, and during the encoding output among a plurality of degenerate pixel patterns ordered by the ordering means And a pattern selection unit that obtains a decoded output by selecting the degenerate pixel pattern corresponding to the pattern number.