JPH0697785A - Complementary signal transition detecting circuit - Google Patents

Abstract

PURPOSE:To surely detect the transition even though a high-speed complementary signal being an input signal is inverted twice during a short period by starting the inversion of the input signal and the charge of a capacitive element at the same time. CONSTITUTION:When the inversion of the input signal is not generated in succession, the inversion of the input signal immediately changes an output O to an L state and a pulse with the width corresponding to the discharge period of capacitors 43 or 53 of delay circuit 4 or 5. The first stages of the circuits 4 and 5 are NAND circuits 41 and 51, to which input signals IB and IA are inputted. In a stable state, a signal to be inputted to the NAND circuit connected to the discharging capacitor is in an H state. On the other hand, a signal to be inputted to the NAND circuit connected to the charged capacitor is in an L state. The input signal is inverted in this state and the output of the circuit 4 starts to change to an H state when the IB changes to the L state. Then, the capacitor 43 starts charging at once.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transition detecting circuit for a semiconductor device, which receives two signals that change complementarily as input signals and generates a predetermined pulse signal in response to changes in the input signals.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have become faster and more sophisticated, and transitions of various signals have been detected and the detected signals have been actively applied. Also in the memory element,
The transition of the address signal is detected to reset the internal circuit, and the operation period is limited. The detection signals generated by these transition detections are basic signals for various operations and require reliable detection sensitivity and high speed.

FIG. 8 shows a conventional circuit for detecting a signal transition.
It is a figure which shows an example. Although detailed explanation is omitted,
Data to generate a complementary signal of the input signal
Issue I _A,I_BEnter as. The circuit of FIG. 8 has a complementary input signal.
Signal has a stable state and the output in the high (H) state
can get. And the input signal I_A,I_BWhen is reversed,
Depending on the state of the first NAND circuit 1 or the second NAND circuit
The output of path 2 is about to change, but the key connected to the output
The output state does not change until the capacitor 6 or 7 is charged.
There will be a delay. After this delay, the output of the third NAND circuit 3
The force changes to the low (L) state. At the same time, the first NAN
The output of D circuit 1 and the second NAND circuit 2 is the one in the H state.
The force also tries to change to the L state, but similarly
The original output state is maintained until the discharge is completed.
Therefore, the output of the third NAND circuit 3 is in the L state during that time,
After the discharge ends, the state returns to the H state. Therefore, a pulse is generated.
That is, the pulse rises after the charging period from the inversion of the input signal.
And the pulse width becomes the length of the discharge period. The following
In the figures, common functional parts are given the same reference numerals.
Will be represented.

The above charging period and discharging period are determined by the drive capacity and the capacitance of the capacitor when the output of the NAND circuit changes from L to H or from H to L. Therefore, normally, the driving capability of the p-channel transistor and the driving capability of the n-channel transistor of the NAND circuit are made large so that the charging period is short and the discharging period is long. However, it is difficult to drastically shorten the charging period because it is necessary to charge the capacitor even during the charging period. This charging period is the response time from the inversion of the input signal to the output of the pulse, which is not suitable for high-speed operation. There's a problem.

Therefore, a conventional complementary signal transition detection circuit with improved high-speed operability is shown in FIG. In the circuit of FIG. 8, since the input of the third NAND circuit is delayed, it is difficult to operate at high speed. Therefore, in the circuit of FIG. 9, the first NAN
First delaying the outputs of the D circuit 1 and the second NAND circuit 2
The delay circuit 4 and the second delay circuit 5 are separately provided, and the first NAND
The outputs of the circuit 1 and the second NAND circuit 2 are input to the third NAND circuit 3 without being delayed. As a result, the transition of the complementary input signal appears in the third NAND circuit 3 quickly. The delay circuits 4 and 5 are composed of two inverters and capacitors connected in series.

FIG. 10 shows a potential change in each part of the circuit of FIG.
FIG. Now input signal I_AIs in H state, I_BIs L-shaped
It is in a state. At this time, the output O is in the H state and the first delay
The capacitor 46 of the extended circuit 4 is charged to H,
The potential is Q_AIt is represented by. Similarly, the capacitor 53 of the delay circuit 5
Is in the L state and its potential is Q _BIt is represented by.

The input signal I _A switches to the L state and I _B
Is switched to the H state, the output of the first NAND circuit 1 tries to change to the L state, and the potential P _A changes from L to H. The output O is the first NAND circuit 1 and the third NAND circuit.
It changes to L after the total delay of the circuits 3. At the same time, the output of the inverter 44 of the first delay circuit 4 also changes from H to L, but its potential Q _A slowly drops because the capacitor 46 is connected. The output potential R _A of the inverter 45 goes into the H state in response to the decrease in the potential Q _A , the output potential P _{B of the} second NAND circuit 2 changes to L, and the output O returns to H. This period is represented by t in the figure. At the same time, the output potential Q _B of the inverter 51 of the second delay circuit 5 changes to the H state and becomes stable. The period from the transition to the stable state is represented by u. In this way, a pulse signal having a width corresponding to the discharge period of the capacitor is generated immediately after the transition of the input signal. Here again, the drive capacity of the inverter is shown to be greater during charging than during discharging.

[0008]

In the transition detection circuit for detecting the transition of the address signal of the memory element and generating the pulse signal, in addition to responding to the signal transition at high speed as described above, For the transition, it is required to generate a pulse for a predetermined period from the transition time. This is because it is necessary for the reset operation and the like in the memory element.

The above requirement is that even if noise or the like is mixed in the address pulse and continuous transitions occur in a short period, a predetermined pulse is generated for each transition.
Depending on the transition pattern, it means that it is necessary to generate a pulse that ends after a predetermined time from the last transition and after a period indicated by t in FIG. The circuit of FIG. 9 becomes stable again after the period indicated by u in FIG. 10 from the transition of the input signal. Therefore, if the transition of the input signal is longer than the period indicated by u, a normal pulse signal is output. However, when continuous input signal transitions occur in a period shorter than u, a problem occurs that a normal pulse signal cannot be obtained because the capacitor that defines the pulse width is not charged to a predetermined value. FIG. 11 is a diagram showing a potential change in each part when the input signals I _{A and} I _B continuously transit in a short period in the circuit of FIG.

FIG. 11 is a diagram showing a case where the input signal transitions before the discharge of the capacitor 46 is completed. In response to the first transition of the input signals I _{A and} I _B , the first NAND
The output potential P _A of the circuit 1 changes to H, the output O changes to L, and the output potential Q _A of the inverter 44 of the first delay circuit 4 also starts to change to L. However, since the input signals I _{A and} I _B make the second transition before the discharge of the capacitor 46 is completed, the output potential P _A changes to L, and conversely
Will start charging. At this time, since the discharge of the capacitor 46 is not completed, the output of the first delay circuit 4 does not change,
The output potential P _B of the second NAND circuit 2 and the second delay circuit 5
Since the state of does not change, the output O is the first NAND circuit 1
The output potential P _A of H returns to H as it returns to L. Therefore, the period from the transition of the input signals I _{A and} I _{B to} the end of the output pulse is v shown in the figure, and has a value that has nothing to do with the discharge period of the capacitor.

As described above, the conventional complementary signal transition detection circuit shown in FIG. 9 has no problem in terms of high-speed operability that a pulse is generated immediately after the transition of the input signal, but in the short period of the input signal. Continuous inversion causes a problem that the length of the transition detection pulse becomes short or the transition detection pulse is not output. The present invention has been made in view of the above problems, and an object of the present invention is to realize a transition detection circuit which can detect a transition at high speed even when a complementary signal as an input signal is inverted twice in a short period.

[0012]

The complementary signal transition detection circuit of the present invention has a first signal to which a signal on the first side of the complementary signal is input.
A NAND circuit, a second NAND circuit to which a signal on the second side of the complementary signal is input, a first NAND circuit and a second NAN
The 3rd N which receives the output of the D circuit and outputs a pulse signal
An AND circuit and a first NAND circuit delay the output and then output as an input signal of the second NAND circuit. A first delay circuit and an output of the second NAND circuit delay and then output as an input signal of the first NAND circuit. It is a complementary signal transition detection circuit including a second delay circuit. In order to achieve the above object, the first delay circuit includes a fourth NAND circuit, a first inverter circuit to which the output of the fourth NAND circuit is input, and a capacitive element connected between the output of the fourth NAND circuit and the ground. And an output of the first NAND circuit and a signal on the second side of the complementary signal are input to the fourth NAND circuit, and an output of the fifth NAND circuit and the output of the fifth NAND circuit are input to the second delay circuit. And a capacitive element connected between the output of the fifth NAND circuit and the ground. The fifth NAND circuit receives the output of the second NAND circuit and the signal on the second side of the complementary signal. Configure to be input.

In the circuit of the present invention, the NAND circuit is
It can be replaced with an R circuit.

[0014]

In the complementary signal transition detection circuit of the present invention, a change in the input signal immediately appears at the output as in the conventional example shown in FIG. 9, and the width of the output pulse is defined by the discharge time of the capacitive element. In the conventional example of FIG. 9, the charging of the capacitive element of the other delay circuit is not performed until after the discharging of the capacitive element of the one delay circuit is completed, and the input signal is inverted before this charging is completed. Normal pulse was not output. However, according to the present invention, the signals on the second side and the first side of the complementary signal are input to the fourth NAND circuit of the first delay circuit and the fifth NAND circuit of the second delay circuit, respectively, and are charged by inversion of the input signal. Since the input signal input to the NAND circuit connected to the capacitive element is inverted and changes to the L state, charging of the capacitive element is started at the same time when the input signal is inverted. When this charging is completed, a normal pulse can be output with respect to the inversion of the input signal, and a normal pulse can be output with respect to the continuous inversion of the input signal.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The circuit configuration of the first embodiment of the present invention is shown in FIG. In the figure, I _{A and} I _B indicate complementary input signals, 1
Is a first NAND circuit to which the input signal I _A is input,
Reference numeral 2 is a second NAND circuit to which the input signal I _B is input. Reference numeral 3 is a third NAND circuit to which the output of the first NAND circuit 1 and the output of the second NAND circuit 2 are input, and an output O is obtained from this. The output potential of the first NAND circuit 1 is P _A and the output potential of the second NAND circuit 2 is P _B. Reference numeral 4 is a first delay circuit, and 5 is a second delay circuit.

The first delay circuit 4 has a fourth NAND circuit 41 to which the output of the first NAND circuit 1 and the input signal I _B are input.
And an inverter 42 for inverting its output, and a fourth NAN
It has a capacitor 43 connected between the output of the D circuit 41 and the ground Vss, and the output of the inverter 42 is input to the second NAND circuit 2. The second delay circuit 5 has
A fifth NAND circuit 51 to which the output of the second NAND circuit 2 and the input signal I _A are input, an inverter 52 that inverts its output, an output of the fifth NAND circuit 51 and the ground Vss
And a capacitor 53 connected between and, and the output of the inverter 52 is input to the first NAND circuit 1.

The potential of the output line of the fourth NAND circuit 41 is set to Q
_A, and the potential of the output line of the fifth NAND circuit 51 is Q _B. Further, the output potentials of the inverters 42 and 52 are R _A and R _B , respectively. The circuit of FIG. 1 has input signals I _A, I _B
There are two types of stable states depending on the state, and in any case, the output O of the third NAND circuit 3 is in the H state.

The operation when the inversion of the input signal does not occur continuously is similar to the operation of FIG. 9 described above, and the inversion of the input signal immediately changes the output O to the L state, and the capacitor of the delay circuit 4 or 5 is changed. A pulse having a width corresponding to the discharge period of 43 or 53 is generated. The circuit of FIG. 1 differs from the conventional example of FIG. 9 in that the first stage of the delay circuits 4 and 5 is a fourth NAND circuit 41.
And the fifth NAND circuit 51, the fourth NAN
The input signal I _B is input to the D circuit 41, and the fifth NAND
The input signal I _A is input to the circuit 51. In steady state, N connected to the capacitor being discharged
The input signal input to the AND circuit is in the H state,
Conversely, the input signal input to the NAND circuit connected to the charged capacitor is in the L state. For example,
When the capacitor 43 of the first delay circuit 4 is discharged,
That is, when Q _A is in the L state, the input signal I _B is in the H state. When the input signal is inverted in this state and I _B changes to the L state, the output of the fourth NAND circuit 4 starts to change to the H state and the capacitor 43 immediately starts charging. Therefore, unlike the circuit of FIG. 9, the charging of the other capacitor is started after the discharging of the other capacitor is completed.

The driving capacity of the fourth NAND circuit 41 and the fifth NAND circuit 51 of the circuit of FIG. 1 is greater when the output changes from L to H than when it changes from H to L, as described later. ing. The discharge period, that is, the width of the output pulse is determined by the driving capacity when changing from H to L and the capacitance of the capacitor, but the capacitor is charged in a shorter time.

FIG. 2 shows an input signal I in the circuit of FIG.
_A, is a graph showing a potential change of each portion in the case of inversion in a short time I _B, will be described an operation when the detail. If the input signal I _A is H and I _B is L in the steady state before the operation, the output potential P _{B of the} second NAND circuit 2 is H and the output of the fifth NAND circuit 51 is L. Therefore, the capacitor 53 is discharged and Q _B is L. The output potential R _B of the inverter 52 is H. Therefore, the first NA
The output potential P _A of the ND circuit 1 is L, and the output of the fourth NAND circuit 41 is H. Therefore, the capacitor 43 is charged and Q _A is H. The output potential _RA of the inverter 42 is L, and the output O (transition detection signal) of the third NAND circuit 3 is H.

When the input signals I _{A and} I _B are inverted at time T ₁ , the output potential P _{A of the} first NAND circuit 1 is immediately inverted to H, and the transition detection signal O becomes H at both P _A and P _B. It changes immediately and detects that there is a transition in the input signal. At the same time, the fourth NAND circuit 41 inputs P _A and I
_Since both _B become H, it tries to output L. However, since it takes time to discharge the capacitance of the capacitor 43, the potential Q _A changes slowly.

On the other hand, the second NAND circuit 2 keeps outputting H because the input signal I _B changes to H but R _A remains L. Further, in the fifth NAND circuit 51, the input signal I _A is L
Therefore, the output changes to H. As described above, since the fifth NAND circuit 51 has a large driving ability when changing from L to H, the capacitor 53 is charged relatively quickly, and Q _B changes to H after w hours. As a result, the output potential R _{B of the} inverter 52 also becomes L relatively early.

At the next time T ₂ , the input signal is inverted again and I
_{When A} becomes H and I _B becomes L, the second NAND circuit 2
Raises the output potential P _B to H regardless of R _A , but P _B is still H and does not change until then. On the other hand, in the first NAND circuit 1, I _A changes to H, but since the capacitor 53 is already charged and R _B is L, the output potential P _A remains H. Therefore, the output O remains L.

The output of the fifth NAND circuit 51 tends to change to L because P _B remains H and I _A becomes H. Since the capacitor 53 has already been charged, discharging is started. This discharge is performed at a relatively slow rate as described above. On the other hand, the fourth NAND circuit 41 tries to change the output to H because I _B becomes L. At this time, the capacitor 43 is partially discharged, but the fourth NAND circuit 4
It becomes H relatively quickly in response to the change of the output of 1 to H.

The signal I input to the fifth NAND circuit 51
_{Since A} and P _B do not change after the time T ₂ , the capacitor 53 continues discharging and the output potential R _B of the inverter 52 changes from L to H. Since I _A is H, the output potential P _A of the first NAND circuit 1 becomes L when R _B becomes H.
, And the output O also becomes H accordingly. The period u from the time T ₂ at this time is determined by the discharge period of the capacitor 53, which means that a normal pulse is generated. The state in which this pulse generation is completed is the steady state.

As described above, in the first embodiment, the input signal I
It is possible to generate a normal detection signal even if _{A and} I _B are continuously inverted. A normal detection signal can be generated if the input signal is inverted after the charging of the capacitor that was actually discharged is completed. In the first embodiment, the charging period of the capacitor is shorter than the discharging period.
This is performed by changing the driving capability of the transistors of the AND circuit 41 and the fifth NAND circuit 51. FIG. 3 shows a configuration example of a NAND circuit, in which 301 and 302 are p-type transistors and 302 and 303 are n-type transistors. If the signal applied to the input terminal A is L, the p-type transistor 301 becomes conductive, and if it is H, the n-type transistor 30.
2 conducts. When the signal applied to the input terminal B is L, the p-type transistor 304 is conductive, and when it is H, the n-type transistor 303 is conductive.

As is apparent from the above description, the capacitor starts charging when the input signals I _{A and} I _B become L, and at that time, the two p-type transistors 30 are connected.
Of p. 1, 304, only the p-type transistor controlled by the input signal conducts and charges. Therefore, if an input signal is applied to the terminal A, the p-type transistor 301
The drive capacity of the determines the charging period. The capacitor begins to discharge when both input terminals go high, n
The type transistors 302 and 303 are both conductive. Therefore, if both driving abilities are the same, since two transistors are connected in series, the driving ability of one n-type transistor determines the discharge period.

Since the discharge period corresponds to the pulse width, the driving ability of the n-type transistors 302 and 303 is determined according to the capacitance of the capacitors. Since it is preferable that the charging period is shorter than the discharging period, the p-type transistor 30
The driving capacity of 1 is set to be larger than that of the n-type transistors 302 and 303. The drivability is changed by changing the gate width of the transistor.

Next, an embodiment in which the complementary signal transition detection circuit shown in FIG. 1 is applied to an SRAM is shown in FIGS. FIG. 4 shows a part for generating a reset clock from an address signal, and FIG. 5 shows a bit line reset part, a bus line reset part, and a sense amplifier part which use the reset clock. The address signal to the SRAM is input to the row decoder and the column decoder, but here, as shown in FIG. 4, a complementary signal of each address signal is generated and then input to the transition detection circuit of FIG. Therefore, there are as many transition detection circuits as there are address signals. Since a negative pulse is output from each of the transition detection circuits to which the input address signal makes a transition, when these are input to the multi-input NAND circuit, a reset pulse is always output when an address value transition occurs. .

In the SRAM, a reset operation is performed in order to speed up the operation. This reset operation is, as shown in FIG. 5, a bit line reset in which each bit line pair is short-circuited by the p-type transistors 501 and 502 and the transistor circuits 503 and 504 and a bus line pair circuit 505 in which each bit line pair is put together. The above-mentioned reset pulse is used for both reset operations. In addition, a sense amplifier 506 for amplifying the signal of the bus line pair
The reset pulse is also used for the operation control of. If the address input signal contains noise, a normal reset operation could not be performed so far, but by using the transition detection circuit of the present invention, a normal reset operation can always be performed.

In the first embodiment of FIG. 1, the transition detection circuit using the NAND circuit is shown, but as shown in FIG.
The transition detection circuit can be realized even if all the NAND circuits of are replaced with NOR circuits. The operation of the circuit of FIG. 6 is easy and understandable from the above description, and a detailed description thereof is omitted. However, unlike the circuit of FIG. 1, the circuit of FIG. 6 obtains a positive output pulse.

FIG. 7 shows a configuration example of the NOR circuit. In this case, it is desirable that the pulse width is defined by the charging period and the discharging period is shorter than the charging period. Therefore, the driving capability of the n-channel transistors 703 and 704 is made larger than that of the p-channel transistors 701 and 702.

[0033]

As described above, according to the present invention,
High-speed and reliable transition detection signal can be obtained, and SR
If it is used for address transition detection such as AM, high-speed and stable operation can be guaranteed even if a signal such as noise is input to the address input signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a potential change in each part of the circuit of FIG.

FIG. 3 is a diagram illustrating a configuration example of a NAND circuit.

FIG. 4 is a diagram showing a part of an embodiment in which the circuit of FIG. 1 is applied to SRAM.

5 is a diagram showing another portion of FIG. 4. FIG.

FIG. 6 is a diagram showing a circuit configuration of a second embodiment.

FIG. 7 is a diagram showing a configuration example of a NOR circuit.

FIG. 8 is a diagram showing an example of a conventional complementary signal transition detection circuit.

FIG. 9 is a diagram showing another conventional example.

10 is a diagram showing a potential change in each part of the circuit of FIG.

FIG. 11 is a diagram showing a potential change of each part when an input signal is continuously inverted in the circuit of FIG. 9.

[Explanation of symbols]

 1 ... 1st NAND circuit 2 ... 2nd NAND circuit 3 ... 3rd NAND circuit 4 ... 1st delay circuit 5 ... 2nd delay circuit 41 ... 4th NAND circuit 42 ... Inverter 43 ... Capacitance element 51 ... 5th NAND circuit 52 ... Inverter 53 ... Capacity element

Claims (4)

[Claims] 1. A complementary signal transition detection circuit for generating a predetermined pulse signal according to a change of an inputted complementary signal, wherein a first NAND circuit (1) to which a signal on the first side of the complementary signal is inputted. A second NAND circuit (2) to which a signal on the second side of the complementary signal is input, and outputs of the first NAND circuit (1) and the second NAND circuit (2) are input to output the pulse signal A third NAND circuit (3), a first delay circuit (4) that delays the output of the first NAND circuit (1) and then outputs the delayed signal as an input signal of the second NAND circuit (2), and the second NAND circuit ( A complementary signal transition detection circuit comprising: a second delay circuit (5) that delays the output of 2) and then outputs it as an input signal of the first NAND circuit (1), wherein the first delay circuit (4) comprises: 4th NAND round Road (41)
And a first inverter circuit (42) to which the output of the fourth NAND circuit (41) is input, and a capacitive element (43) connected between the output of the fourth NAND circuit (41) and the ground (Vss). And a fourth NAND circuit (4
The output of the first NAND circuit (1) and the signal on the second side of the complementary signal are input to 1), and the second delay circuit (5) includes a fifth NAND circuit (51).
A second inverter circuit (52) to which the output of the fifth NAND circuit (51) is input, and a capacitive element (53) connected between the output of the fifth NAND circuit (51) and the ground (Vss). And a fifth NAND circuit (5
A complementary signal transition detection circuit, wherein the output of the second NAND circuit (2) and the signal on the second side of the complementary signal are input to 1). 2. The fourth NAND circuit (41) and the fifth NAND circuit (51) each include a p-channel type transistor driven on a first side and a second side of a complementary signal. The complementary signal transition detection circuit according to claim 1, wherein the driving capability of the type transistor is larger than that of the other transistors. 3. A complementary signal transition detection circuit for generating a predetermined pulse signal according to a change of an input complementary signal, wherein a first NOR circuit (61) receives a signal on the first side of the complementary signal. A second NOR circuit (62) to which a signal on the second side of the complementary signal is input, the first NOR circuit (61) and the second NOR circuit (6)
The third output which receives the output of 2) and outputs the pulse signal
A NOR circuit (63), a first delay circuit (64) that delays the output of the first NOR circuit (61) and then outputs the delayed signal as an input signal of the second NOR circuit (62), and the second NOR circuit (62) ), A second delay circuit (65) for delaying the output of the first NOR circuit (61) and outputting it as an input signal of the first NOR circuit (61), wherein the first delay circuit (64) is 4 NOR circuit (64
1), a first inverter circuit (642) to which the output of the fourth NOR circuit (641) is input, and a capacitive element (connected to the output of the fourth NOR circuit (641) and the ground (Vss). 643), the output of the first NOR circuit (61) and the signal on the second side of the complementary signal are input to the fourth NOR circuit (641), and the second delay circuit (65) includes 5 NOR circuit (65
1), a second inverter circuit (652) to which the output of the fifth NOR circuit (651) is input, and a capacitive element (connected between the output of the fifth NOR circuit (651) and ground (Vss). 653), and the output of the second NOR circuit (62) and the signal on the second side of the complementary signal are input to the fifth NOR circuit (651). 4. The fourth NOR circuit (641) and the fifth NOR circuit (651) each include an n-channel type transistor driven on a first side and a second side of a complementary signal, and the n-channel transistor is provided. The complementary signal transition detection circuit according to claim 2, wherein the driving capability of the type transistor is larger than that of the other transistors.