JPH0697427A - Semiconductor device - Google Patents

Abstract

PURPOSE:To materialize a semiconductor device, which can be driven with a plain control circuit and which performs thyristor operation low in on voltage in on condition and performs IGBT operation short in turn on time at turn off, without complicating the manufacture process and excellently in chip's area efficiency. CONSTITUTION:An n<->-type base region 2 is formed on the topside of a p<+>-type anode region 1, and a p-type gate region 3 and a p-type cathode short region 5 are formed a specified interval apart on the surface of the n<->-type base region 2, and an n-type cathode region 4 is formed on the surface within the aforesaid p-type gate region 3, and further the n<+>-type cathode region 4 and the p-type cathode short region 5 are electrically connected. Moreover, a gate oxide film 6 is formed on the surface of the region between the n<+>-type cathode region 4 and the p-type cathode short region 5 and in its vicinity, and this has a gate electrode 7 on the gate oxide film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a structure combining a thyristor and a transistor.

[0002]

2. Description of the Related Art Power semiconductor devices are used in all fields of power control and play an important role. In particular, in recent years, demands for power saving and high speed have increased along with high breakdown voltage and large current. In order to meet these requirements, semiconductor devices have been developed in which a thyristor with a low on-voltage and a transistor for switching the thyristor at high speed are formed on one chip.

A normal thyristor is a current drive type in which switching is controlled by flowing a current from a gate. On the other hand, a thyristor of a type that has a built-in MOS FET and switches the thyristor by injecting or discharging carriers through the MOS FET at the time of turn-on / turn-off operation is generally called a MOS-type thyristor.

FIG. 3 shows a conventional device which is an example of the above device.
1 is a cross-sectional configuration diagram of an example of a double gate MOS type thyristor.
is there. In the figure, p of the MOS thyristor⁺Type
P that is the Kuta area 11 ⁺On the upper surface of mold silicon substrate
Is n⁺The mold buffer region 12 is formed, and
N on the top^-A mold base region 13 is formed.
And this n^-The thyristor portion 2 is formed on the mold base region 13.
0 and a short portion 30 are formed.

The thyristor portion 20 has an n ^-- type base region 1
3 is a p-type base region 21 formed to a predetermined depth on the surface of No. 3, and an n ⁺ -type emitter region 22 formed shallower than the p-type base region 21 on the surface of the p-type base region 21. , P ⁺ -type base contact regions 23. Further, the short portion 30 has a p-type well region 31 formed in the upper portion in the n ⁻ -type base region 13 and a surface portion in the p-type well region 31 that is shallower than the p-type well region 31 with a predetermined interval. N ⁺ type base short region 32,
It is provided with an n ⁺ type emitter short region 33 and ap ⁺ type contact region 34 formed adjacent to a side surface and a lower surface of the n ⁺ type emitter short region 33.

A silicon oxide film 14 is formed on the surface of the n ⁻ type base region 13 where the above-mentioned regions are formed, except for the contact holes.
N ⁻ type base region 13 and n ⁺ type emitter region 2 on the upper surface
Between the two, the first gate electrode 2 made of polysilicon
4 are formed. A second gate electrode 35 made of polysilicon is formed on the upper surface of the silicon oxide film 14 in a portion located between the n ⁺ type base short region 32 and the n ⁺ type emitter short region 33.

Further, in the thyristor section 20, n
^An emitter electrode 25 made of aluminum or the like is formed on the surface of the ⁺ type emitter region 22 through a contact hole formed in the silicon oxide film 14, and an electrode is similarly formed on the surface of the p ⁺ type base contact region 23. 26 is formed.

Further, in the short portion 30, the surface of both the n ⁺ type emitter short region 33 and the P ⁺ type contact region 34 is similarly exposed through the contact hole formed in the silicon oxide film 14. An electrode 36 made of aluminum or the like and an electrode 37 are further formed on the surface of the n ⁺ type base short region 32. Although the wiring electrode is not shown in the figure, the emitter electrode 25 and the electrode 36, and the electrode 26 and the electrode 37 are connected to each other by wiring such as aluminum. And the thyristor part 2
The electrode 24 of 0 is connected to the gate terminal G1 and the electrode 25 is connected to the emitter terminal. Furthermore, the short section 3
The electrode 35 of 0 is connected to the gate terminal G2, and the electrode 36 is connected to the emitter terminal. A collector electrode 15 made of aluminum or the like is formed on the entire back surface of the p ⁺ -type collector region 11.

In the above thyristor, the thyristor portion 20 has n
⁺Type emitter region 22 as source, n ^-Mold base region 13
As the drain and the p-type base region 21 as the channel region
The n-channel MOS type FET is provided,
⁺Type base short region 32 is the source, n⁺Type emitter
The short region 33 is the drain and the p-type well region 31 is the channel.
It is equipped with an n-channel MOS type FET used as a channel region.
Each MOS type FET has an independent gate
It has a double gate MOS type thyristor structure.

Next, the operation of the double gate MOS type thyristor having the above structure will be described with reference to the time chart of FIG. At the time of turn-off, a positive gate voltage is applied to the first gate G1, and the vicinity of the surface of the p-type base region 21 immediately thereunder is inverted into n-type to form an n-channel. As a result, electrons which are the majority carriers of the n ⁺ type emitter region 22 are injected into the n ⁻ type base region 13 through this channel and accumulated. The accumulated electrons promote the injection of holes from the p ⁺ -type collector region 11 to the n ⁻ -type base region 13, so that the thyristor section 20 is turned on.

On the other hand, at the time of turn-off, first the second game
A positive gate voltage is applied to the gate G2, and the p-type wafer immediately below the gate voltage is applied.
Forming a n-channel by inverting the surface of the region 31
Then n ⁺Mold base short region 32 and n⁺Type emitter
The short region 33 is electrically connected through this channel.
As a result, holes accumulated in the p-type base region 21
Is p⁺From the mold base contact region 23, n⁺Mold base
Formed in the short region 32 and the p-type well region 31
n channels, and n⁺Via the type emitter short region 33
Then it comes to be pulled out by the emitter. This time
In the MOS type thyristor, holes in the p type base region 21 are
By being drawn to the emitter by the above-mentioned path, n⁺Type
Emitter region 22 to n^-Of electrons to the mold base region 13
Injection is reduced and latchup as a thyristor is released
The ON resistance increases. In other words, the second gate G
By applying a positive gate voltage to the
Ilista is an IGBT (Insulated Gate Bipolar Transistor)
or) will behave in the same way.

Next, the MOS operating in the IGBT operation
Type thyristor first gate G1 and second gate G2
The gate voltage applied to is turned off. To this
Than n⁺Type emitter regions 22 and n^-Mold base region 13
N channel near the surface of the p-type base region 21 that has been electrically connected to
Since the channel closes, n⁺Type emitter regions 22 to n ^-
The injection of electrons into the mold base region 13 is stopped. Also,
The holes in the p-type base region 21 are generated in the IGBT operation described above.
Since it is pulled out by the emitter, this timing
And the number of holes as excess carriers becomes very small.
There is. Therefore, until the holes disappear due to recombination, etc.
And the turn-off time is short.

FIG. 5 shows a conventional double gate MOS type circuit.
It is sectional drawing which shows the other structural example of a lister. In the figure
, P⁺P made of type silicon substrate⁺Type collector region 4
The upper surface of 1 has n^-The mold base region 42 is formed
It And this n^-On the surface of the mold base region 42,
An n-type emitter region 43 is selectively formed with a predetermined depth.
The surface of the n-type emitter region 43 has p⁺
Mold regions 44 and p⁺The type region 45 is the n-type emitter region 43.
It is formed shallower than a predetermined distance. Also, n
^-Adjacent n-type formed on the surface of the mold base region 42
The two regions are separated between the emitter regions 43, 43.
The p-type region 46 is a part of the lower side of the n-type emitter region 43.
It is formed to extend to. Furthermore, each n-type emitter
One side of the region 43 and n^-Between the mold base region 42
A p-type base region 47 is formed in the sandwiched region.
The p-type base region 47 is the n-type emitter region 43.
Connected to the bottom surface of the p-type region 46 and the side surface of the p-type region 46.
It

P-type base region 47 and p-type base region 4
A gate oxide film 48 is formed on the surface between 7 and the p ⁺ type region 45 and in the vicinity thereof, and a first gate electrode 49 made of polysilicon or the like is formed on the upper surface thereof. Further, on the surface and in the vicinity of the n-type emitter region 43 between the surface p ⁺ -type region 44 and the p-type region 46 of the p-type region 46 is formed with a gate oxide film 48 in the same manner, the polysilicon on the upper surface A second gate electrode 50 made of, for example, is provided. Furthermore, the upper surfaces and part of the side surfaces of the first and second gate electrodes 49 and 50 and the upper surface of the gate oxide film 48 are covered with an insulating film 51. Then, the p ⁺ type region 4 is formed through the contact hole formed in the gate oxide film 48 and the insulating film 51 which are formed in layers.
4, the surface of the p ⁺ -type region 45 and those regions 44, 45
An emitter electrode 52 made of aluminum or the like is formed on the surface of the n-type emitter region 43 located between them. The emitter electrode 52 includes the first and second gate electrodes 49,
The gate oxide film 48 and the insulating film 51 are electrically separated from the gate electrode 50. In addition, the p ⁺ type collector region 41
A collector electrode 53 made of aluminum or the like is formed on the entire back surface of the.

The operation of the double gate MOS thyristor shown in FIG. 5 is basically shown in FIG. 3 except that the gate voltage applied to the second gate G2 at the time of turn-off is a negative gate voltage. It is similar to the double gate MOS type thyristor.

As described above, the double-gate MOS type thyristor shown in FIGS. 3 and 5 operates as a thyristor during on-operation, so that the on-voltage becomes lower than that of the MOS-type FET, and during turn-off, the thyristor operation is performed once. Since it is turned off after shifting to the IGBT operation, a substantial turn-off time is shortened.

[0017]

However, in the conventional composite element of the thyristor and the MOS type FET shown in FIG. 3, it is necessary to form the short section 30 having the MOS type FET together with the body of the thyristor section 20. However, there was a problem that the area efficiency of the device became poor. In contrast,
In the example shown in FIG. 5, the area efficiency is improved, but there is a problem that the manufacturing process is complicated and the cost is increased.

Further, such a composite element is conventionally shown in FIG.
As shown in FIG. 5, it has a double gate structure that requires two gate electrodes for control, and there is a problem that the control circuit becomes complicated.

The present invention solves the above problems,
The purpose is to realize a semiconductor device which can be driven by a simple control circuit, has a low on-voltage, and good switching characteristics, without making the manufacturing process complicated and with area efficiency.

[0020]

The semiconductor device of the present invention comprises:
A second semiconductor region of the second conductivity type is formed on the upper surface of the first semiconductor region of the first conductivity type, and a third semiconductor region of the first conductivity type is spaced apart from the surface of the second semiconductor region by a predetermined distance. A semiconductor region and a fifth semiconductor region; and a fourth semiconductor region of the second conductivity type on the surface in the third semiconductor region, wherein the fourth semiconductor region and the fifth semiconductor region are It is electrically connected.

An insulating film is formed on the surface of the region between the fourth semiconductor region and the fifth semiconductor region and in the vicinity thereof, and a control electrode is provided on the insulating film.

[0022]

In the turn-on operation of the semiconductor device of the present invention, a channel is formed near the surface of the third semiconductor region by applying a control voltage, and the fourth semiconductor region to the second semiconductor region are formed through the channel. Supply electrons (or holes) to. The electrons (or holes) supplied to the second semiconductor region promote the inflow of holes (or electrons) from the first semiconductor region to the second semiconductor region, and enter the thyristor operation.

On the other hand, the turn-off operation is performed in the vicinity of the surface of the second semiconductor region located between the third semiconductor region and the fifth semiconductor region by applying a control voltage having the opposite sign to that at the time of turn-on. Forming a channel. At this time,
Since the carriers excessively accumulated in the second semiconductor region during the on-operation are discharged through the formed channel, the turn-off time is shortened.

Here, the above-mentioned fifth semiconductor region is the third
Since it is formed simultaneously with the step of forming the semiconductor region of
The process does not become complicated, and the area efficiency is slightly deteriorated because it can be formed only by single diffusion.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment M of the present invention.
It is a cross-sectional block diagram of an OS type thyristor.

In the figure, on the upper surface of the first semiconductor region of the first conductivity type, for example, p ⁺ type, for example, the anode region 1,
A second semiconductor region of the second conductivity type, for example, n ⁻ type, such as the base region 2, is formed by epitaxial growth or the like. Then, p is formed on the surface of the n ⁻ type base region 2.
A third semiconductor region of the type, for example, the gate region 3 and a fifth semiconductor region of the p type, for example, the cathode short region 5 are selectively formed at a predetermined interval. The p-type gate region 3 and the P-type cathode short region 5 are formed in the same step by ion implantation or thermal diffusion. Further, on the surface portion in the p-type gate region 3, an n ⁺ -type fourth semiconductor region, for example, a cathode region 4 is formed shallower than the p-type gate region 3 and selectively.

The p-type gate region 3 located between the n ⁺ -type cathode region 4 and the p-type castor short-circuit region 5,
A gate oxide film 6 is formed on the surface of the n ⁻ type base region 2 and its vicinity, and a gate electrode 7 made of polysilicon is formed on the upper surface thereof. And
A cathode electrode 9 made of aluminum or the like is formed so as to be electrically connected to the surfaces of the n ⁺ type cathode region 4 and the p type cathode short region 5. Incidentally, this cathode electrode 9
The gate electrode 7 and the gate electrode 7 are electrically separated by the insulating film 8. An anode electrode 10 made of aluminum or the like is formed on the entire back surface of the p ⁺ type anode region 1.

Next, the operation of the MOS type thyristor having the above structure will be described. To turn on the MOS thyristor of this embodiment, first, a positive gate voltage is applied to the gate electrode 7. This gate voltage inverts the vicinity of the surface of the p-type gate region 3 located immediately below the gate electrode 7 to form an n-channel. In other words, the n channel M having the n ⁺ type cathode region 4 as the source and the n ⁻ type base region 2 as the drain
This means that the OS type FET is turned on, and electrons are supplied from the n ⁺ type cathode region 4 to the n ⁻ type base region 2 through the n channel thereof.

The electrons supplied to the n ^- type base region 2 are
It is attracted to the vicinity of the p ⁺ -type anode region 1 and p
Since the potential barrier of the n-junction is lowered, the flow of holes from the p ⁺ type anode region 1 to the n ⁻ type base region 2 is promoted. Then, when the holes reach the p-type gate region 3, the n ⁺ -type cathode region 4 changes to n.
The supply of electrons to the ⁻ type base region 2 is promoted, and the operation of the thyristor state with a low on-voltage starts.

On the other hand, when the MOS thyristor of this embodiment is turned off, a negative gate voltage is applied to the gate electrode 7. Due to this negative gate voltage, the n channel formed near the surface of the p-type gate region 3 is closed, and at the same time, the n ⁻ -type base region 2 immediately below the gate electrode 7, that is, the p-type gate region 3 is formed. And the p − type cathode short region 5 located between the n ⁻ type base region 2 and the surface are inverted, and a p channel is formed. In other words, p
Type gate region 3 as source, p-type cathode short region 5
The p-channel MOS type FET that has drained is turned on.

As a result, the p-type gate region 3 is electrically connected to the cathode electrode 9 via the p-channel and the p-type cathode short region 5, and the p ⁺ -type anode regions 1 to n are formed.
^The holes that have flowed into the p-type gate region 3 via the ⁻ type base region 2 are extracted to the cathode electrode 9 via the above-described path. That is, the MOS type thyristor shown in FIG. 1 has an IGBT (Insulated Gate Bipolar Transistor) immediately after a negative gate voltage is applied to the gate electrode 7.
) Operate. In this IGBT operation, holes as excess carriers supplied to the p-type gate region 3 are reduced in a short time, and latch-up of the thyristor operation is released, so that the n ⁺ -type cathode region 4 to the n ⁻ -type base region are released. The flow of electrons into the area 2 is stopped.

Further, excess carriers (holes) accumulated in the n ⁻ type base region 2 when the MOS type thyristor is in the on state are directly extracted from the p type cathode short region 5 and at the same time, the p type gate is formed. From the region 3 as well, the above p
Pulled through the channel. Therefore, excess carriers in the n ⁻ type base region 2 disappear in a short time, and
The turn-off time of the OS type thyristor is shorter than that of the conventional thyristor.

Further, the MOS thyristor of this embodiment is
Since the single gate electrode that controls the switching is used, the control circuit can be simplified. Furthermore, since the p-type cathode short region 5 is formed in the same process as the p-type gate region 3, the number of processes does not increase, and
Since the p-type cathode short-circuit region 5 can be formed in a much smaller region than the short-circuit portion 30 of the conventional example shown in FIG. 3, the area efficiency of the chip is improved.

FIG. 2 is a MOS type thyristor in which the conductivity type of the MOS type thyristor of FIG. 1 is inverted. In the figure, ap ⁻ type base region 62 is formed on the upper surface of the n ⁺ type anode region 61. Then, an n-type gate region 63 and an n-type cathode short region 65 are formed on the surface of the p ⁻ type base region 62 at a predetermined interval in the same step. A p ⁺ -type cathode region 64, which is shallower than the n-type gate region 63, is selectively formed on the surface of the n-type gate region 63.

Further, the gate oxide film 66 and the gate electrode 6
7, insulating film 68, cathode electrode 69 and anode electrode 7
Although 0 is formed, the configuration and the like are the same as in the example shown in FIG.

The operation of the MOS type thyristor of FIG. 2 is the same as that of the MOS type thyristor of FIG. 1, although the sign of the gate voltage applied at turn-on and turn-off is reversed.

[0037]

As described above, according to the present invention,
In the ON state, a thyristor operation having a low ON voltage is performed, and at the time of turn-off, the operation is temporarily switched to the IGBT operation and then turned off, so that the turn-off time is short.
Since the S-type thyristor can be realized with a single gate, its control circuit can be simplified. Further, in forming the above-mentioned MOS thyristor, the process does not become complicated, and the deterioration of the area efficiency can be suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of a MOS thyristor which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a MOS type thyristor in which the conductivity type of the MOS type thyristor of FIG. 1 is inverted.

FIG. 3 is a cross-sectional view showing a configuration example of a conventional double gate MOS type thyristor.

FIG. 4 is a time chart explaining the operation of the conventional double gate MOS type thyristor shown in FIG.

FIG. 5 is a cross-sectional view showing another example of the configuration of a conventional double gate MOS type thyristor.

[Explanation of symbols]

1 p ⁺ type anode region 2 n ⁻ type base region 3 p type gate region 4 n ⁺ type cathode region 5 p type cathode short region 6 gate oxide film 7 gate electrode 8 insulating film 9 cathode electrode 10 anode electrode

Claims (1)

[Claims] 1. A second semiconductor region of a second conductivity type on an upper surface of a first semiconductor region of a first conductivity type, and a first conductivity region on a surface of the second semiconductor region at a predetermined distance. A third semiconductor region and a fifth semiconductor region of the second conductivity type, and a fourth semiconductor region of the second conductivity type on the surface in the third semiconductor region,
The fourth semiconductor region and the fifth semiconductor region are electrically connected, and an insulating film is formed on the surface of the region between the fourth semiconductor region and the fifth semiconductor region and in the vicinity thereof. A semiconductor device having a control electrode on the insulating film.