JPH0696592A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a writing time and to accelerate erasing at a high speed by applying a high voltage to a control gate of a memory cell, and simultaneously writing it by a tunnel current flowing from a channel region to a floating gate. CONSTITUTION:A predetermined drain voltage VD, a control gate voltage Vcc are applied to a row decoder RD and a cell(C) selected by a column gate CG. Then, hot electrons are generated in a high electric field near a drain, and simultaneously written by a tunnel current to be injected in a floating gate. In this case, an electric field is generated from a channel(Ch) to a gate (FG) near a source S. In the case of erasing, when all the bits are simultaneously written and the voltages VCC, VD are set to predetermined values, a tunnel current from the vicinity of the source is injected in the gate FG. Then, a drain current is reduced as compared with the case of ordinarily writing, and simultaneous writing is performed without wire disconnection due to an overcurrent. Thus, a writing time is shortened, and erasing can be accelerated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device.

[0002]

2. Description of the Related Art A flash E ² P is shown in FIGS.
The plane pattern and cross section of the memory cell used for ROM are shown. Usually, writing to the memory cell of the flash E ² PROM is performed by injecting electrons into the floating gate FG by hot electron injection, and erasing is performed by the source S.
A high voltage is applied to the FN tunnel current to extract electrons from the floating gate FG.

The above normal writing mechanism will be described in detail with reference to FIG.

Regarding the potential of the floating gate FG, the coupling ratio between the floating gate FG and the control gate CG is C _FC = 0.5, and the V _FG potential at the time of erasing is V _FC.
When _FG (I) = about 1.5 v, the _{V FG = V CG · C FC} + V FG (I) = 12 × 0.5 + 1.5 = 7.5v. Further, the pentode operation creates a pinch-off point PP, and a high electric field is generated near the drain D. Hot electrons are generated in that region, and electrons are injected into the floating gate FG. Especially when writing is performed in the breakdown region, the drain current is large.

The drain current during the above-mentioned normal writing is shown in FIG.
Of I _d1 . In FIG. 3, 1 indicates a breakdown region, 2 indicates cell characteristics, and 3 indicates write load transistor characteristics.

When a memory device is configured with the memory cell having the above structure, electrons may be excessively extracted during erasing, and the threshold _{Vth of the} memory cell may become negative. When the data of another written cell connected to the same data line as the cell having the negative threshold value is read, the overerased cell is effectively in the selected state, causing a malfunction. Therefore, it is necessary to avoid putting the memory cell in the over-erased state.

In order to prevent this, conventionally, erasing has been performed as follows. That is, in order to prevent excessive erasing of cells that have already been erased at the time of erasing, all bits (all memory cells) are first written, then all bits are erased, and the erase level of all memory cells is erased. Is made uniform.

[0008]

Consider, for example, a case where all bits are written in advance at the time of erasing in a 1 M-bit product (128 k × 8 bit configuration). If it takes about 100 μs to write 1 byte, it takes about 14 seconds to write all bits. Subsequent erasure of all bits is performed in about 1 second. Therefore, most of the erasing operation is the writing time, and there is no advantage of erasing all bits at once at a high speed. When such an algorithm is used, when the integration degree increases, the ratio of the write time to the total erase time increases, and the advantage of batch erase disappears.

However, in the current writing mechanism,
All bits cannot be written at once. The reason for this is that when the collective writing is performed, an excessively large write current flows, which leads to destruction such as fusing of the wiring.

The present invention has been made in view of the above,
The purpose thereof is to shorten the writing time in the entire time required for the erase operation in the flash E ² PROM to enable the erase speed to be high.

[0011]

A first nonvolatile semiconductor memory device according to the present invention has a memory cell array in which a plurality of nonvolatile memory cells each having a floating gate, a control gate, a source and a drain are arranged in an array. In a non-volatile semiconductor memory device capable of performing normal writing and reading to the selected memory cell and batch erasing of the plurality of memory cells, it is possible to control the plurality of memory cells prior to the batch erasing. It is configured to have a collective write voltage output means for applying a high voltage to a gate to cause collective write in each memory cell by a tunnel current flowing from a channel region between the source and the drain to a floating gate. To be done.

A second nonvolatile semiconductor memory device according to the present invention has a plurality of memory cell blocks, and each block has a plurality of nonvolatile memory cells having a floating gate, a control gate, a source and a drain. In each of the blocks, in a nonvolatile semiconductor memory device capable of normal writing and reading to the selected memory cell and batch erasing of a plurality of the memory cells in each of the blocks,
Prior to the batch erasing for each block, a high voltage is applied to the control gates of the plurality of memory cells in the selected arbitrary block of the plurality of blocks to apply the high voltage to each of the blocks of the arbitrary block. The memory cell is configured as having a collective write voltage output means for performing collective write by a tunnel current flowing from the channel region between the source and the drain to the floating gate.

A third non-volatile semiconductor memory device according to the present invention is the first or second non-volatile semiconductor memory device, wherein a normal write voltage is applied to a control gate of the memory cell during the normal write. The built-in voltage output means is provided separately from the collective write voltage output means.

A fourth non-volatile semiconductor memory device of the present invention is the first or second non-volatile semiconductor memory device according to the first or second non-volatile semiconductor memory device, in which a normal write voltage is applied to a control gate of the memory cell during the normal write. The voltage output means is provided integrally with the collective write voltage output means to constitute a composite write voltage output means for switching and outputting the normal write voltage and the collective write voltage.

A fifth non-volatile semiconductor memory device of the present invention is the third or fourth non-volatile semiconductor memory device, wherein the normal write voltage output means is a hot electron generated near the drain of the memory cell. Is configured to output the normal write voltage having the voltage value injected into the floating gate.

[0016]

In batch writing performed prior to batch erasing, the batch writing voltage from the batch writing voltage output means is applied to the control gate of each memory cell.
As a result, in each memory cell, a tunnel current flows from the channel region to the floating gate, and writing is performed. Because the current value of the tunnel current is small, even if you write to multiple memory cells at once,
The total current value required for the writing can be suppressed to a small value.

[0017]

EXAMPLE A first example of the present invention is shown in FIG. Figure 1
In the write / read switching circuit WR,
A first collective write circuit WH1 and a second collective write circuit WH2 are provided. Further, transfer gates WT11 to WT1m and WT21 to WT2m are provided on the opposite side of the word line WL _{i from} the row decoder RD side. The SW booster circuit BS is connected to the row decoder RD. In reading, one memory cell C is selected by the row decoder RD and the column gate CG. Based on the current value of the selected cell C, the sense amplifier SA determines whether the data is "0" or "1". The read data is output through the I / O buffer (not output).

Next, the write mode will be described.
Here, for example, normal writing in 1-byte units in the case of an 8-bit configuration will be described.

The cell C selected by the row decoder LD and the column gate CG has a drain voltage V _D = 6v,
Source voltage V _S = 0 v, control gate voltage V _CG =
12v is applied. Hot electrons are generated due to the high electric field near the drain. The electrons are injected into the floating gate and writing is performed. At this time, a drain current of about several mA flows due to the avalanche effect.

Next, the erase mode will be described. Source voltage V _S = 12 v, drain voltage V _D = control gate voltage V _CG = 0 v. As a result, an electric field is applied to the gate oxide film (about 100 angstroms) between the floating gate and the source, and the electrons stored in the floating gate are extracted by the FN tunnel current.

At the time of this erasing, it is necessary to set the cells of all bits to the written state in advance. This writing is
Do it differently than in normal mode. The reason for this is that if multiple bits are simultaneously written in the normal mode, an excessive current may flow and the wiring or the like may be destroyed. This writing is different from the writing in byte unit in the normal mode, and all bits are written collectively. That is, control gate voltage V _CG = 18v, drain voltage V _D = 2
v and the source voltage V _S = 0v. As a result, electrons are injected into the floating gate by the tunnel current from the vicinity of the source. As a result, the drain current is much smaller than in normal writing. As a result, there is no destruction such as breakage of Al wiring due to overcurrent. Therefore, it becomes possible to write all the bits at the same time.

The batch write mechanism in the above embodiment of the present invention will be described with reference to FIG.

The voltage of the floating gate FG is shown in FIG.
As in the case of 1, if the coupling ratio C _FC = 0.5, then V _FG = 18 × 0.5 + 1.5 = 10.5v. A channel ch is formed by the operation of the triode. In the vicinity of the source S, an electric field of about 10 MV / cm (when the gate oxide film is about 100 angstrom) is generated from the channel ch toward the floating gate FG. Electrons are injected from the channel ch into the floating gate FG by a tunnel current.
This is the operation in the triode region with a drain voltage of 2v.
As can be seen, the drain current I _d2 is small.

An example of the algorithm of the erase operation described above will be described with reference to the flowchart of FIG.

In FIG. 4, block A is a part for performing a write operation to all bits once to make the erase characteristics uniform, and block B is a part for performing erase and verify operations. That is, first, writing is performed in byte units (S1). Next, write verify is performed (S2). If the program is NG, the process returns to step S1. This additional program will be conducted up to 25 times. Write verify OK in step S2
In case of, it moves to step S3. If all addresses have not been programmed, the procedure returns to step S1, and if they have been programmed, the procedure moves to step S4. In step 4, all bits are erased at once with an erase pulse of 10 msec. In the case of erase verify NG in step S5, the process returns to step S4. If there is a cell that cannot be erased, additional erase is performed. Perform additional deletion up to 3000 times. If the erase verify is OK in step S5, the erase operation is ended.

FIG. 5 shows a specific example of FIG.

The write / read switching circuit WR is
V _PP (= 12v) is applied to the line WRL connected to the gates of the transfer gates WT11 to WT1m at the time of normal writing in byte units, and at the time other than normal writing (at the time of reading / erasing / in batch writing mode) V
_This is a circuit that gives _CC (= 5v).

At the time of normal writing, <P _rog > = 15v,
NP _rog = 0v, and the V _PP potential becomes the transistor 10
It is applied to the line WRL via 1, 102. <P _rog > = 0v and NP _rog = 5v except during normal writing, and V _CC is applied to the line WRL via the transistor 103.

First and second batch write circuits WH1, WH
Reference numeral 2 is a circuit that operates only when writing all bits at once and applies a high voltage (about 18 V) to all word lines. The second batch write circuit is a circuit that creates a word line potential at the time of batch write, and generates WHL2 = about 18v. WH2 (= about 18v) is turned on / off by WHL1
Transfer gates WT21 to WT2m turned off
Is applied to all word lines WL via. WHL1 is the first
Made with a batch writing circuit. The first collective write circuit WH1 applies a boosted potential (about 23v) to the transfer gates TW1 to TWm gates so that the potential generated in the second collective write circuit WH2 can be applied to all the word lines WL without a potential drop. It is a circuit to do.

At the time of batch writing, an oscillation waveform is given as OSC, PBE = “H” (= 5v), NPBE =
It becomes "L" (= 0v).

In the first collective write circuit WH1, the transistors 201, 202 and 203 allow [0v-V _CC
(5v)] amplitude signal, [0v-V _PP (12v)]
Convert to a signal of amplitude. The capacitor 204 and the transistors 206 and 207 generate a potential boosted from V _PP . The transistors 205 and 210 function as switches that are turned on / off at the time of batch writing and turned on / off at the time of batch writing. In the figure, 208, 20
Reference numeral 9 is a transistor for relaxing high potential. First
The batch write circuit WH1 is 2V _PP -2V _THI (= about 2
An electric potential of 4-1 = 23 v) is generated. Except at the time of batch writing, it is connected to the ground GND by the transistor 210 and becomes 0v.

The operation of the transistors 301 to 310 of the second collective write circuit WH2 is the same as that of the first collective write circuit WH.
Same as 1. Transistors 312, 313, 314
Is a voltage limiter circuit, and WHL2 is set to V _PP + 2V
It is set to _THE (= about 12 + 6v = 18v) (V
_THE is an E-type transistor V _TH ). Except during batch writing, the transistor 310 causes the transistor 30
The gates of 5, 312 and 311 are set to 0v (GND level). By supplying V _CC from the transistor 315, WHL2 becomes V _CC (= 5 v).

RS _{1 to} RS _r are signals in the preceding stage of the buffer of the row decoder LD. Depending on the address selected, the selected row is "L" (= 0v) and the unselected row is "H" (= V _CC
= 5v). C _{11 to} C _mn are memory cells, which are connected to word lines and bit lines.

At the time of reading, WRL = 5v, WHL1 = 0
v, WHL2 = 5v. Transfer gate WT1
1 to WT1m are turned on, and transfer gates WT21 to WT21 to
WT2m is turned off, and only the word line selected by the row decoder LD becomes SW (= 5v).

At the time of normal writing, WRL = 12v, WH
L1 = 0v and WHL2 = 5v. As when reading
The transfer gates WT11 to WT1m are turned on, and the transfer gates WT21 to WT2m are turned off. However, the gates of the transfer gates WT11 to WT1m are as high as V _PP level, and the selected word line is SW.
(= 12v) is transmitted.

At the time of batch writing, WR1 = 0v, WHL
1 = 23v and WHL2 = 18v. The transfer gates WT11 to WT1m are in the ON state, and WHL2 = 18v is applied to all the word lines. The transfer gates WT11 to WT1m are D type transistors,
When the word line becomes _{│V THD} │ or more, it is cut off and separated from the row decoder LD.

At the time of erasing, WRL = 5v, WHL1 = 0
v, WHL2 = 5v. RS _{1 to} RS _r are all V _CC
(= 5v), and all word lines are set to ground GND.

Even during standby, WRL = 5v, WHL1
= 0v and WHL2 = 5v. RS _{1 to} RS _r are V _CC
(= 5v), and all word lines are deselected.

In each mode, the row decoder RD
Signal RS _i for driving (A), word line potentials SW, WR
L, WH1, WH2, PBE, showed the potential of the P _rog in Table 1.

^{Table 1} RS _i WL _i SW WRL WHL1 WHL2 PBE <Prog> _Read selected cell 0 5 5 5 0 5 0 0 Unselected cell 5 0 5 5 0 5 0 0 Write Selected cell 0 12 12 12 0 5 0 15 (Normal) Non-selected cell 12 0 12 12 0 5 0 15 Batch erase 5 0 5 5 0 5 0 0 Batch writing 0 18 5 5 23 18 5 0 (Unit: v) The potential of the output SW (A) of the SW booster circuit BS (A) is shown in Table 2.

Table 2 Normal write Batch write Read batch erase SW (B) 12 18 5 5 SW (A) 12 5 5 5 ( ^{batch write circuit or al word line boosting)} (unit: v) FIG. 6 shows a second embodiment of the present invention. This embodiment is a memory device in which the memory cell array MCA is divided into several blocks B1 to Bl, and each of the blocks B1 to Bl can be independently rewritten.

Since erasing and writing for each block and batch writing for each block are performed, the batch write voltage WHL is used.
2 is transferred to the word line WL. Since the transfer gates connected to each block are driven independently of the gates of other blocks, the first batch write circuit WH1 is divided into 1 blocks corresponding to the blocks B1 to Bl of the memory cell array, and 1 batch write is performed. Circuits WH11 to WH11, and output terminals of the circuits WH11 to WH11 are transfer gates WT of blocks B1 to Bl of the memory cell array.
211 to WT21l and WT2m1 to WT2ml.

The fourth embodiment of the present invention shown in FIG. 7 is
The word line potential at the time of normal writing, reading, and batch writing is created by the same circuit [row decoder RD (B)]. With this circuit configuration, the first and second collective write circuits WH1 and WH2 may be omitted. In addition, this circuit is a batch write circuit,
The structure is the same as that of the conventional type without a write / read circuit and without using a transfer gate for a word line.
This embodiment is an embodiment in which the SW booster circuit BS (B) and the row decoder RD (B) are provided with countermeasures in terms of circuit and process so that batch writing can be performed. SW booster circuit B
Specific examples of the S (B) and the row decoder RD (B) are shown in FIGS. The circuit configuration of the row decoder RD (B) is the same as that of the row decoder RD (A). However, as described later, the oxide film is made thick in order to prevent the oxide film from being destroyed even when 18 V is applied. Output SW
(B) is shown in Table 2.

In FIG. 8, the output SW (B) is added to the source or the like of the P-ch transistor of the final stage buffer of the row decoder RD (B) of FIG. In this circuit, V _CG = 18v is required at the time of batch writing. At this time, the junction breakdown voltage and the gate oxide film breakdown voltage of the buffer portion of the row decoder RD (B) become a problem. In order to improve the breakdown voltage, the junction part of each transistor has a high breakdown voltage structure. That is, the gate oxide film of a transistor to which a high voltage is applied, which is surrounded by a broken line circle in FIG. 9, is made thicker than other transistors.

As a result, even in the memory device having the structure of the conventional example shown in FIG. 7, by setting each voltage to the normal write voltage or the batch write voltage, it is possible to write with different mechanisms.

In FIG. 9, RDM is a row decoder main unit, and RA _i , RB _i , RC _i , RD _i.
Is a signal from the predecoder determined based on the row address.

According to the embodiment of the present invention, the writing to all the bits before erasing can be performed simultaneously for all the bits, so that the erasing time can be greatly shortened. For example, the erasing time, which took 15 seconds with a 1 M cell, can be reduced to about 1 second. As a result, data can be rewritten at high speed, and an added value is added to the advantage of the E ² PROM that can be electrically rewritten.

[0048]

According to the present invention, a plurality of memory cells can be collectively written without causing an overcurrent to flow, thereby reducing the total time required for collective erasing while preventing the occurrence of an overerased state. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory view of a batch writing mechanism.

FIG. 3 is a graph showing a write current.

FIG. 4 is a flowchart for erasing a two-layer cell.

5 is a specific example of FIG.

FIG. 6 is a circuit diagram of a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a third embodiment.

FIG. 8 is a specific example of a part of FIG. 7.

9 is a specific example of a part of FIG. 7. FIG.

FIG. 10 is a plan view of a two-layer cell.

11 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 12 is an explanatory diagram of a normal writing mechanism.

[Explanation of symbols]

C (C _{11 to} C _mn ) memory cell RD (A), RD (B) row decoder BS (A), BS (B) SW booster circuit WH1, WH2 first and second batch write circuit

Claims (5)

[Claims] 1. A plurality of nonvolatile memory cells each having a floating gate, a control gate, a source and a drain are arranged in an array to form a memory cell array, and normal writing and reading to and from the selected memory cell, In a non-volatile semiconductor memory device capable of batch erasing of a plurality of the memory cells, prior to the batch erasing, a high voltage is applied to the control gates of the plurality of the memory cells so that the source of each of the memory cells is the source. A non-volatile semiconductor memory device, comprising: batch write voltage output means for performing batch write by a tunnel current flowing from a channel region between the drain and the drain to a floating gate. 2. A plurality of memory cell blocks are provided, and each of the blocks has a plurality of nonvolatile memory cells having a floating gate, a control gate, a source and a drain arranged in an array. In a non-volatile semiconductor memory device capable of performing normal writing and reading for the selected memory cell and batch erasing for a plurality of memory cells in each block, prior to the batch erasing for each block, the plurality of blocks A high voltage is applied to the control gates of the plurality of memory cells in the selected arbitrary block of the memory cells, and the floating gate is applied from the channel region between the source and the drain in each of the memory cells of the arbitrary block. Batch writing by tunnel current flowing through A non-volatile semiconductor memory device having collective write voltage output means for performing the operation. 3. The normal write voltage output means for applying a normal write voltage to the control gate of the memory cell during the normal write, is provided separately from the collective write voltage output means. 2. The nonvolatile semiconductor memory device according to item 2. 4. A normal write voltage output means for applying a normal write voltage to a control gate of the memory cell at the time of the normal write is provided integrally with the collective write voltage output means to provide the normal write voltage and the normal write voltage. 3. The non-volatile semiconductor memory device according to claim 1, which is a composite write voltage output means for switching and outputting the collective write voltage. 5. The normal write voltage output means is configured to output the normal write voltage having a voltage value at which hot electrons generated near the drain of the memory cell are injected into a floating gate. The nonvolatile semiconductor memory device according to claim 3 or 4.