JPH069428B2 - Digital bus protection relay - Google Patents

Digital bus protection relay

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Publication number
JPH069428B2
JPH069428B2 JP7875786A JP7875786A JPH069428B2 JP H069428 B2 JPH069428 B2 JP H069428B2 JP 7875786 A JP7875786 A JP 7875786A JP 7875786 A JP7875786 A JP 7875786A JP H069428 B2 JPH069428 B2 JP H069428B2
Authority
JP
Japan
Prior art keywords
relay
amount
bus
current
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7875786A
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Japanese (ja)
Other versions
JPS62236327A (en
Inventor
伸夫 江田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7875786A priority Critical patent/JPH069428B2/en
Publication of JPS62236327A publication Critical patent/JPS62236327A/en
Publication of JPH069428B2 publication Critical patent/JPH069428B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電力系統の二重母線を保護するデジタル形地
絡母線保護継電装置に関するものである。
Description: TECHNICAL FIELD The present invention relates to a digital ground fault bus protection relay device for protecting a double bus of a power system.

〔従来の技術〕[Conventional technology]

第3図は例えば特公昭43−2986号公報に示された
従来の分割保護方式と称される二重母線保護装置の原理
構成図であり、図において(1-1)(1-2)は母線、(1-3)は
母線連絡線(以下母連と称す)、(101),(201)…(1n)(2
n)は断路器、(3-1)…(3-n)(3-A)(3B)はCT、(4)はギヤ
ツプ付入力トランス、(101×)(201×),(1n×)
(2n×)は各々断路器(101)(201),(1n)(2
n)が閉成時に接点ONする補助リレー接点、(26)は入
力装置、(27)は整流回路、(28-1)(28−2)は母線保
護リレーである。
FIG. 3 is a principle block diagram of a double busbar protection device called a conventional split protection system disclosed in, for example, Japanese Patent Publication No. 43-2986, in which (1-1) (1-2) are Busbars, (1-3) are busbar connecting lines (hereinafter referred to as busbars), (101), (201)… (1n) (2
n) is a disconnecting switch, (3-1) ... (3-n) (3-A) (3B) is CT, (4) is an input transformer with a gear cup, (101 ×) (201 ×), (1n ×)
(2n ×) are disconnecting switches (101) (201), (1n) (2)
n) is an auxiliary relay contact that turns on when closed, (26) is an input device, (27) is a rectifier circuit, and (28-1) and (28-2) are busbar protection relays.

次に動作について説明する。母線1(1-1)又は母線2(1-
2)に接続される各回線に設置されたCT(3-1)〜(3-n)及
び母線(1−3)に設置さたCT(3-A),(3-B)の二次電
流は各々入力装置(26)に内蔵されたギヤツプ付入力トラ
ンス(4)で電圧変換される。ギヤツプ付入力トランス(4)
には2次コイルと3次コイルを有し、2次コイル出力電
圧は動作量、3次コイル出力電圧は整流回路(27)を介し
て抑制量であり、これら出力は、断路器(101),(201)…
(1n),(2n)の動作状態に応じて開閉する接点(101×),
(201×)…(1n×),(2n×)により、母線1(1-1)を保護す
る母線保護リレー(以下分割リレーAと称す)(28-1)又
は母線2(1-2)を保護する母線保護リレー(以下分割リ
レーBと称す)に選択される。すなわち、分割リレーA
(28-1)の動作量VDAは母線1(1-1)に接続される全回線
のCT2次電流のベクトル和に比例し、抑制量|VRA
は母線1(1-1)に接続される全回線のCT2次電流中最
大の電流に比例したものとなる。同様に分割リレーB(2
8-2)の動作量VDBは母線2(1-2)に接続される全回線の
CT2次電流のベクトル和に比例し、抑制量|VRB|は
母線2(1-2)に接続された全回線のCT2次電流中最大
の電流に比例したものとなる。分割リレーA(28-1)及び
分割リレーB(28-2)は比率差動原理により動作するもの
であり、|VDA|−η|VRA|K又は|VDB|−η|
RB|cmK(但しη,Kは定数)の条件で動作する
ものである。
Next, the operation will be described. Bus 1 (1-1) or Bus 2 (1-
Secondary of CT (3-1) to (3-n) installed on each line connected to 2) and CT (3-A), (3-B) installed on busbar (1-3) Each current is converted into a voltage by the input transformer (4) with a gear incorporated in the input device (26). Input transformer with gearup (4)
Has a secondary coil and a tertiary coil, the output voltage of the secondary coil is the operation amount, and the output voltage of the tertiary coil is the suppression amount via the rectifier circuit (27). These outputs are the disconnector (101). , (201)…
Contact (101x) that opens and closes according to the operating status of (1n) and (2n),
(201 ×)… (1n ×), (2n ×) protects the busbar 1 (1-1) busbar protection relay (hereinafter referred to as split relay A) (28-1) or busbar 2 (1-2) Is selected as a bus protection relay (hereinafter, referred to as a split relay B) that protects the. That is, the split relay A
The operation amount V DA of (28-1) is proportional to the vector sum of the CT secondary currents of all lines connected to the bus 1 (1-1), and the suppression amount | V RA |
Is proportional to the maximum current of the CT secondary currents of all lines connected to the bus 1 (1-1). Similarly, split relay B (2
The operation amount V DB of 8-2) is proportional to the vector sum of the CT secondary currents of all lines connected to the bus 2 (1-2), and the suppression amount | VRB | is connected to the bus 2 (1-2). It is proportional to the maximum current of the CT secondary currents of all the lines that have been processed. The split relay A (28-1) and the split relay B (28-2) operate according to the ratio differential principle, and are | V DA | −η | V RA | K or | V DB | −η |
It operates under the condition of V RB | cmK (where η and K are constants).

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従来の母線保護継電装置は以上のように構成されている
ので、第4図に示すような母線運用時に送電線の零相循
環電流Iothが母線連絡に集中する為内部一線地絡事故が
発生しても母線連絡を通過する各回線の零相循環電流和
ΣIothが不要抑制として効果し分割リレーが不動作又は
検出感度低下となるなどの問題点があった。
Since the conventional busbar protection relay device is configured as described above, an internal one-line ground fault occurs because the zero-phase circulating current Ioth of the transmission line concentrates on the busbar connection when the busbar is operated as shown in FIG. However, there was a problem that the zero-phase circulating current sum ΣIoth of each line passing through the bus connection was effective as unnecessary suppression, and the split relay did not operate or the detection sensitivity was lowered.

この発明は上記のような問題点を解消するためになされ
たもので、零相循環電流の影響をまったく受けない分割
リレー方式を得ることを目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a split relay system that is not affected by the zero-phase circulating current at all.

〔問題点を解決するための手段〕[Means for solving problems]

この発明によれば、母線の内外部事故を判別する一括リ
レーと、各母線単位の分割差動を動作量とし母線一括差
動量に比例した量を抑制量とする分割リレーとを備え、
一括リレー出力と分割リレー出力の論理積により各母線
のトリツプ出力を発生するようにしたものである。
According to the present invention, a collective relay for determining an internal / external accident on the bus bar, and a split relay having an operation amount of a differential differential for each bus bar and an amount proportional to the batch differential amount of the bus as a suppression amount are provided,
The trip output of each bus bar is generated by the logical product of the batch relay output and the split relay output.

〔作用〕 この発明による分割リレーは抑制量として母線一括差動
量に比例した量を使用した比率差動リレーとした為、母
線内部1線地絡事故時に母連を通過する零相循環電流に
よる不要抑制が生じることなく、確実に事故母線を選択
することができる。又外部事故に対しては母線一括差動
量を動作量とし、各回線電流の絶対値に基づいた演算量
を抑制量とする一括リレーにより誤動作を防止すること
ができるものである。
[Operation] Since the split relay according to the present invention is a ratio differential relay that uses an amount proportional to the bus bar differential amount as the suppression amount, it is caused by the zero-phase circulating current passing through the bus station in the case of an internal one-line bus fault. Accident busbars can be reliably selected without unnecessary suppression. Further, for an external accident, a malfunction can be prevented by a collective relay in which the bus-line batch differential amount is the operation amount and the operation amount based on the absolute value of each line current is the suppression amount.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において(4-1)〜(4-n)(4−A)(4−B)はギヤツ
プ付入力トランス、(5)はデジタルリレー、(6)はフイル
ター、(7)はサンプルホールド器(以下S/Hと称
す)、(8)はマルチプレクサー(以下MP×と称す)、
(9)はアナログ/デジタル変換器(以下A/Dと称す)(1
0)はデジタル入力回路(以下DIと称す)、(11)はデジ
タル出力回路(以下DOと称す)、(12)はメモリー、(1
3)はマイクロプロセッサ(以下CPUと称す)である。
CT(3-1)〜(3-n),(3-A)(3B)の2次電流はギャップ付
入力トランス(4-1)〜(4-n)(4-A)(4-B)で電圧変換し、デ
ジタルリレー(5)に導入する。
An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, (4-1) to (4-n) (4-A) and (4-B) are input transformers with gears, (5) is a digital relay, (6) is a filter, and (7) is a sample and hold device ( Hereinafter referred to as S / H), (8) is a multiplexer (hereinafter referred to as MP ×),
(9) is an analog / digital converter (hereinafter referred to as A / D) (1
0) is a digital input circuit (hereinafter referred to as DI), (11) is a digital output circuit (hereinafter referred to as DO), (12) is a memory, (1
3) is a microprocessor (hereinafter referred to as CPU).
The secondary current of CT (3-1) to (3-n), (3-A) (3B) is the input transformer with gap (4-1) to (4-n) (4-A) (4-B ) To convert the voltage and introduce it into the digital relay (5).

一方断路器(101)(201)…(1n)(2n)の開閉状態はそれの補
助リレー接点(101×)(201×)…(1n×)(2n×)を介
してデジタルリレー(5)に導入されている。
On the other hand, the open / close state of the disconnector (101) (201) ... (1n) (2n) is the digital relay (5) via the auxiliary relay contact (101x) (201x) ... (1nx) (2nx). Has been introduced to.

尚ギヤツプ付入力トランス(4-1)〜(4n)には各々2次コ
イルと3次コイルを有し、2次コイルは分割用出力とし
て、そのまゝデジタルリレー(5)に導入し、3次コイル
は、全回線分をペクトル合成した一括用出力としてデジ
タルリレー(5)に導入するもので、第3図に示す従来例
では一括用出力を有していない。
The input transformers with gears (4-1) to (4n) each have a secondary coil and a tertiary coil, and the secondary coil is used as a split output and is introduced to the digital relay (5) as it is. The next coil is to be introduced into the digital relay (5) as a batch output in which all lines are combined by a vector, and the conventional example shown in FIG. 3 does not have the batch output.

ギャップ付入力トランス(4-1)(4-n)(4-A)(4-B)の各2次
出力及び一括用出力は各々フイルター(6)を介し、S/
H(7)で同一時刻,一定間隔のアナログ量瞬時値をサン
プリングする。MP×(8)は各S/H(7)の出力を順次切
替え、A/D(9)にてアナログ量をデジタル量に変換の
上メモリー(12)に記憶させる。一方断路器の開閉状態は
DI(10)より取り込みメモリー(12)に状態を記憶させ、
CPU(13)で電流デジタル量の選択演算、リレー演算等
を行ないDO(11)で動作出力を外部に出すものである。
The secondary output of the input transformer with gaps (4-1) (4-n) (4-A) (4-B) and the output for batch are respectively passed through the filter (6) and S /
H (7) samples the analog value instantaneous value at the same time and at constant intervals. The MP × (8) sequentially switches the output of each S / H (7), converts the analog amount into a digital amount by the A / D (9), and stores it in the memory (12). On the other hand, the open / closed state of the disconnector is taken from DI (10) and stored in the memory (12).
The CPU (13) performs selection calculation of the digital current amount, relay calculation, etc., and the DO (11) outputs the operation output to the outside.

以上の構成から成るデジタル形地絡母線保護継電装置に
おいて演算原理を第2図に示す。
FIG. 2 shows the operation principle of the digital ground fault bus protection relay device having the above-mentioned configuration.

第2図において入力I〜Iは各々第1図のCT(3-
1)〜(3n)の2次電流瞬時値に比例したデジタル量、入力
,Iは第1図のCT(3-A),(3-B)の2次電流瞬時
値に比例したデジタル量、入力Iは第1図の入力トラ
ンス(4-1)〜(4-N)の3次コイルベクトル合成値、すなわ
ち母線1(1-1)及び母線2(1-2)に接続された全回線のC
T2次電流を一括した差動電流(以下一括差動電流と称
す)の瞬時値に比例したデジタル量、入力101×,201×
〜(1n×)(2n×)は第1図の断路器(101)(201)〜(1n)(2n)
の開閉状態を表わすデジタル量であり、電流入力はA/D
(9)、断路器開閉状態信号はDI(10)より各々メモリー
(12)に一時記憶されている。以上の入力データを使用し
て、メモリー(12)に永久保持されたプログラムに従って
CPU(13)で演算処理するものである。選択ブロツク(1
4)は断路器開閉状態に応じて電流入力データを選択する
ものであり、例えば第1図のCT(3-1)の回線が断路器
(101)閉、(201)開の状態であれば電流データIは母線
(1-1)用分割リレー87A(第3図に示す従来の87A(28-1)
に相当)演算を行う入力として選択され、断路器(101)
開(201)閉の状態であれば電流データIは母線2(1-2)
用分割リレー87B(第3図に示す従来の87B(28-2)に相
当)演算を行なう入力として選択される。同様に電流デ
ータIを選択した結果の分割リレー87A用電流デ
ータ群InAをブロツク(15-1)に示し分割リレー87B用電
流データ群InBをブロツク(15-2)に示す。
Input I 1 ~I n each of the first view CT in FIG. 2 (3-
Digital quantities proportional to the secondary current instantaneous values of 1) to (3n), inputs I A and I B are proportional to the secondary current instantaneous values of CT (3-A) and (3-B) in FIG. The digital value and input I D are connected to the composite value of the tertiary coil vector of the input transformers (4-1) to (4-N) in FIG. 1, that is, the bus bar 1 (1-1) and the bus bar 2 (1-2). C of all lines
Digital value proportional to the instantaneous value of the differential current that collectively includes the T secondary current (hereinafter referred to as the collective differential current), input 101 ×, 201 ×
〜 (1n ×) (2n ×) is the disconnector (101) (201) 〜 (1n) (2n)
It is a digital value that indicates the open / closed state of the
(9), disconnection switch open / close status signal is memorized from DI (10)
It is temporarily stored in (12). Using the above input data, the CPU (13) performs arithmetic processing according to a program permanently retained in the memory (12). Selection block (1
4) is for selecting the current input data according to the switching state of the disconnector. For example, the line of CT (3-1) in Fig. 1 is the disconnector.
If (101) closed and (201) open, the current data I 1 is the bus
(1-1) split relay 87A (conventional 87A (28-1) shown in Fig. 3
Corresponding to ()) is selected as the input to perform the operation, and the disconnector (101)
If it is in the open (201) closed state, the current data I 1 is the bus 2 (1-2)
Split relay 87B (corresponding to the conventional 87B (28-2) shown in FIG. 3) is selected as an input for calculation. Similarly shown divided relay 87B for current data group I nB indicates division relay 87A for current data group I nA of the result of selecting the current data I 2 ~ n to block (15-1) to block (15-2).

尚母連(1-3)は母線選択をする必要がないため電流デー
タIはブロック(15-1),Iはブロツク(15-2)にその
まま導入している。演算ブロツク(16-1),(16-2)は分割
リレー用差動量IDA,IDBを得る為のもので母線1(1-
1)に接続さ れた全回線CT2次電流のベクトル和に比例した分割リ
レー87A用差動量 はブロツク(15-1)の電流データ群InAをすべて加算演算
して得られ、同様に分割リレー87B用差動量 はブロック(15-2)の電流データ群InBをすべて加算演算
して得られる。
Naohaharen (1-3) Current data I A block do not have to take the bus selection (15-1), I B is introduced directly to block (15-2). The arithmetic blocks (16-1) and (16-2) are for obtaining the differential amounts I DA and I DB for the split relay, and the bus bar 1 (1-
Differential amount for split relay 87A proportional to the vector sum of CT secondary current of all circuits connected to 1) Is obtained by adding all the current data group I nA of the block (15-1), and similarly the differential amount for the split relay 87B. Is obtained by adding all the current data groups I nB of the block (15-2).

演算ブロツク(17-1)は母線1(1-1)の事故を検出する分
割リレー87−Aの動作判別演算であり演算ブロツク(17-
2)は母線2(1-2)の事故を検出する分割リレー87Bの動作
判別演算である。演算ブロツク(17-1),(17-2)に示す原
理式は、本発明の目的である零相循環電流の影響を受け
ない分割リレーを得る手段を示しており、通常の比率差
動リレーと相違する点は、抑制量のとり方にある。すな
わち、通常の比率差動リレーでは前記従来の実施例に示
すように、各回線電流絶対値の内最大値又はスカラー和
に比例した量を抑制としているが、本発明では一括差動
量に比例した量を抑制量としている。このように一括差
動量に比例した量を抑制量とすれば、多回線並架送電線
に発生する零相循環電流の影響がまったくないことは明
らかであり、前記第4図で説明したような問題点は解消
される。尚、一括差動量は母線外部事故時には零とな
り、抑制効果がなくなるが、この対策として後述の一括
リレーを設けるようにする。本発明の分割リレーは複母
線構成における母線内部事故時に、どの母線事故かを確
実に選択することを目的としており、例えば第1図の母
線(1-1)の事故であれば分割リレー87A(17−1)の分
割差動量IDAと一括差動量Iが同一値となる為、定数
η,Kを適当に設定しておけば|IDA|−η|I
>Kが成立し、分割リレー87A(17−1)は動作す
る。一方分割リレー87B(17−2)の分割差動量IDB
は零又はCT誤差分であるのに対し、抑制量は一括差動
量Iに比例したものとなり、充分な抑制効果を生じ分
割リレー87B(17−2)は動作しない。
The calculation block (17-1) is an operation discrimination calculation of the split relay 87-A that detects an accident on the bus 1 (1-1).
2) is an operation discrimination calculation of the split relay 87B for detecting an accident on the bus 2 (1-2). The principle formulas shown in the arithmetic blocks (17-1) and (17-2) show the means for obtaining a split relay that is not affected by the zero-phase circulating current, which is the object of the present invention. The difference between and is in the amount of suppression. That is, in the normal ratio differential relay, as shown in the above-described conventional embodiment, the amount proportional to the maximum value or the scalar sum of the absolute values of each line current is suppressed, but in the present invention, it is proportional to the collective differential amount. The amount is defined as the suppression amount. If the amount proportional to the collective differential amount is used as the suppression amount as described above, it is apparent that there is no influence of the zero-phase circulating current generated in the multi-line parallel transmission line, as described in FIG. 4 above. Problems are solved. It should be noted that the batch differential amount becomes zero in the event of an external accident on the bus, and the suppression effect is lost. However, as a countermeasure against this, a batch relay described later is provided. The purpose of the split relay of the present invention is to reliably select which busbar accident occurs in a busbar internal accident in a double busbar configuration. 17-1) The divided differential amount I DA and the batch differential amount I D have the same value, so if the constants η 1 and K are set appropriately, | I DA | −η 1 | I D |
> K is established, and the split relay 87A (17-1) operates. On the other hand, the split differential amount I DB of split relay 87B (17-2)
Is zero or the amount of CT error, the suppression amount is proportional to the batch differential amount I D , and a sufficient suppression effect is produced and the split relay 87B (17-2) does not operate.

次に演算ブロツク(18)は母連(1-3)を通過する電流
,Iを除く各回線の電流絶対値を導出する演算ブ
ロツク、演算ブロツク(19)は抑制量を得る演算ブロツク
であり、第2図の例では最大値抑制方式と称されるもの
で各回線電流中最大値に比例した量Iを抑制として導
出するものである。演算ブロック(20)は一括リレーの判
別原理式を演算するブロツクであり、一括差動量|I
|と前記抑制量Iとで比率差動リレー演算を行なう。
(21-1),(21-2)は論理積演算であり、一括リレー(20)と
分割リレー(17-1)又は(17-2)とのAND条件を作り最終
の動作判定とするものである。
Next, the operation block (18) is an operation block for deriving the absolute current value of each line except the currents I A and I B passing through the mother station (1-3), and the operation block (19) is an operation block for obtaining the suppression amount. In the example of FIG. 2, this is called the maximum value suppression method, and the amount I R proportional to the maximum value in each line current is derived as the suppression. The calculation block (20) is a block for calculating the discriminant principle formula of the collective relay, and the collective differential amount | ID
The ratio differential relay calculation is performed using | and the suppression amount I R.
(21-1) and (21-2) are logical product operations, and make an AND condition between the collective relay (20) and the split relay (17-1) or (17-2) to make the final operation judgment. Is.

尚一括リレー用抑制量には母連(1-3)の電流I,I
を導入しなくても良い為、第4図に示すような母連を通
過する零相循環電流和ΣIothの影響を受けることはな
い。
In addition, the currents I A and I B of the mother stations (1-3) are included in the suppression amount for collective relay
Since it does not need to be introduced, it is not affected by the zero-phase circulating current sum ΣIoth passing through the mother station as shown in FIG.

なお、上記実施例では一括リレーと分割リレー用のCT
2次電流及び構成ハードウェアーを共用しているが、こ
れを完全分離した一括+分割二重保護方式における一括
リレー用差動量を第2図の演算(17-1)(17-2)に利用して
もよく第2図の抑制演算(19)を加算演算としてスカラー
和抑制方式としても良い。
It should be noted that in the above embodiment, the CT for the collective relay and the split relay
The secondary current and the constituent hardware are shared, but the differential amount for the collective relay in the collective + split double protection system in which this is completely separated is shown in the calculation (17-1) (17-2) in Fig. 2. Alternatively, the scalar sum suppression method may be used as the addition operation of the suppression operation (19) in FIG.

〔発明の効果〕〔The invention's effect〕

以上のように、この発明によれば、複母線全体を保護す
る一括リレーで母線内外部事故を判別し、一括差動量に
比例した量を抑制量とする各母線単位に設けた分割リレ
ーのAND条件とするよう構成したので、母連を通過す
る零相循環電流和による分割リレーの不動作又は感度低
下等の問題が解消され又デジタルリレー構成とすればす
べてソフトウェアーで処理できる為、コストアップとな
ることなく高信頼度な装置が得られる効果がある。
As described above, according to the present invention, a collective relay that protects the entire compound bus is used to determine an internal / external bus fault, and a split relay that is provided for each bus unit whose suppression amount is an amount proportional to the collective differential amount. Since it is configured to be an AND condition, problems such as the inoperability of the split relay due to the sum of zero-phase circulating currents passing through the mother station or the decrease in sensitivity can be solved. There is an effect that a highly reliable device can be obtained without being up.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例によるデジタル形地絡母線保
護継電装置の構成図、第2図は同じく演算ブロック図、
第3図は従来の分割保護方式を示す構成図、第4図は従
来方式の問題点を説明するための補足図である。 なお図中同一符号は同一又は相当部分を示す。
FIG. 1 is a block diagram of a digital ground fault bus protection relay device according to an embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing a conventional split protection system, and FIG. 4 is a supplementary diagram for explaining problems of the conventional system. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】二重母線に接続された各回線及び母線間連
絡線に設置された変流器の2次電流を各々同一時刻、同
一間隔でサンプリングし、デジタル量に変換して得る第
1の電流データと、前記各回線の変流器2次電流に比例
したアナログ量をベクトル合成した後、前記サンプリン
グと同一時刻、同一間隔でサンプリングしデジタル量に
変換して得る第2の電流データと、前記各回線を母線選
択する断路器開閉状態を各々デジタル量に変換して得る
開閉状態データとを入力するデジタル形母線保護継電装
置において、前記第1の電流データを前記開閉状態デー
タに応じて各母線単位に選択した結果を加算演算して得
る各母線単位の分割差動量を動作量とし、前記第2の電
流データに所定の定数を乗算して得る量を抑制量とした
比率差動リレーを各母線単位の分割リレーとし、前記第
2の電流データを動作量とし、前記第1の電流データ群
の内母線連絡線の電流データを除く全回線電流の各々を
絶対値演算し、その各絶対値電流中最大値又は各絶対値
電流の加算値に所定の定数を乗算して得る量を抑制量と
した比率差動リレーを母線一括の一括リレーとし、前記
母線単位毎の分割リレー出力と一括リレー出力との論理
積により各母線のトリツプ出力を発生するようにしたこ
とを特徴とするデジタル形母線保護継電装置。
1. A first current obtained by sampling secondary currents of current transformers installed in each line connected to a double bus and an inter-bus connecting line at the same time and at the same interval and converting them into digital quantities. Current data and second analog data obtained by vector-synthesizing analog quantities proportional to the secondary currents of the current transformers of the respective lines and then sampling at the same time and at the same intervals as the sampling and converting into digital quantities. A digital busbar protection relay device for inputting switching state data obtained by converting the switching state of the disconnecting switch that selects each of the lines into a digital amount, and the first current data according to the switching state data. Ratio difference in which the divided differential amount of each busbar unit obtained by adding and computing the results selected for each busbar unit is used as the operation amount, and the amount obtained by multiplying the second current data by a predetermined constant is the suppression amount. Dynamic relay A split relay is used for each bus, the second current data is used as an operation amount, and all the line currents except the current data of the inner bus connecting line of the first current data group are subjected to absolute value calculation and their absolute values are calculated. A ratio differential relay in which the amount obtained by multiplying the maximum value in the current value or the added value of each absolute value current by a predetermined constant is the suppression amount is a collective relay of the bus bar collectively, and the split relay output and the collective relay for each bus bar unit A digital bus protection relay device characterized in that a trip output of each bus is generated by a logical product with the output.
JP7875786A 1986-04-04 1986-04-04 Digital bus protection relay Expired - Lifetime JPH069428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7875786A JPH069428B2 (en) 1986-04-04 1986-04-04 Digital bus protection relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7875786A JPH069428B2 (en) 1986-04-04 1986-04-04 Digital bus protection relay

Publications (2)

Publication Number Publication Date
JPS62236327A JPS62236327A (en) 1987-10-16
JPH069428B2 true JPH069428B2 (en) 1994-02-02

Family

ID=13670769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7875786A Expired - Lifetime JPH069428B2 (en) 1986-04-04 1986-04-04 Digital bus protection relay

Country Status (1)

Country Link
JP (1) JPH069428B2 (en)

Also Published As

Publication number Publication date
JPS62236327A (en) 1987-10-16

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