JPH0693675B2 - Independent synchronous network buffer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used for data transmission means between independent synchronous networks.
In particular, it relates to the centering means of the data signal buffer provided at the connection point.

〔Overview〕

According to the present invention, the centering means of the buffer device provided at the connection point between the independent synchronous networks performs the centering forcibly and periodically at a designated time, thereby performing the centering regardless of the status of the transmission line. Compared to the example, it is possible to prevent the occurrence of a data error associated with centering.

[Conventional technology]

In data transmission between independent synchronous networks, a buffer circuit is prepared at the connection point to absorb the phase difference between the mutual timings. Normally, this buffer circuit is provided with a centering circuit that restores the maximum margin when the buffer margin is reduced. Conventionally, it was general to detect a decrease in margin and automatically perform centering.

[Problems to be solved by the invention]

With such a conventional centering means, the centering is automatically executed when the buffer margin is reduced, so that the user need not be aware of it. When the transmission line is overcrowded or during the transmission of important data, centering is performed, and there is a drawback that an error occurs in the data.

The present invention eliminates such drawbacks, and an object of the present invention is to provide an independent synchronous inter-network buffer device capable of suppressing the occurrence of a data error by appropriately selecting the time at which centering is executed. .

[Means for solving problems]

The present invention is characterized in that, in an independent synchronous inter-network buffer device in which centering is performed, centering is performed for each calendar time when the setting can be changed.

[Action]

Specify the centering time using the calendar timer whose settings can be changed. Centering is performed forcibly and periodically at this designated time. This designated time is determined according to the usage status of the transmission path. For example, during a time zone when the transmission path is overcrowded, centering is avoided to prevent the occurrence of a data error. When the phase difference is large, the cycle is set short and the buffer is effectively used.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The figure is a block diagram showing the configuration of this embodiment.

In this embodiment, as shown in the figure, between one network and another network in which data is synchronously transmitted by a clock having a phase difference with respect to a clock phase for synchronously transmitting data in this one network. When the one network is in the phase state of either the lead phase or the lag phase with respect to the other network, the data corresponding to this phase difference is temporarily stored and the lead phase is inserted. Or a buffer circuit 1 which is a storage means for giving data corresponding to this phase difference to the other network when either of the delay phases is in the other phase state
CPU4 which is a centering means for changing the address of the data string stored in the buffer circuit 1 so that the substantially center of the data string coincides with the substantially central address of the address assigned to the storage area of the buffer circuit, It is provided with a comparator circuit 2, which is a starting means for starting the centering means at each calendar time when the setting can be changed, a calendar timer 3, a serial interface 5, and a terminal 6.

First, the user sets the centering time data g from the terminal 6. The CPU 4 reads this centering time data g through the serial interface 5 and sets it in the comparator circuit 2. The comparator circuit 2 compares the calendar time data f output from the calendar timer 3 with the centering time data g, and outputs a centering request signal e to the buffer circuit 1 when they match. Buffer circuit 1
Receives the centering request signal e and performs centering.

For example, if the delay of the data up to 70msec in data transmission 64k bit / sec is allowed, buffer size, (delayed data) × (transmission rate) = 64,000 (kbit / sec) × 70 × 10 - ³ (sec) = 4,480 (bit). If you perform centering once a day,
The phase difference of the transmission timing of the other side, The degree is within the allowable range.

Further, when the phase difference between the transmission timings of both sides is large, the centering cycle can be shortened.

〔The invention's effect〕

As described above, according to the present invention, since centering can be selectively performed while avoiding a time when data transmission is overcrowded, it is possible to prevent a data error from occurring.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1 ... Buffer circuit, 2 ... Comparator circuit, 3 ...
Calendar timer, 4 ... CPU, 5 ... Serial interface, 6 ... Terminal, 7 ... CPU internal bus, a ... Received data, b ... Read data, c ... Write clock, d ... Read clock, e ... Centering request signal, f ... Calendar time data, g ... Centering time data.

Claims (1)

[Claims] 1. A network is inserted in a path between one network and another network in which data is synchronously transmitted by a clock having a phase difference with respect to a clock phase for synchronously transmitting data in the one network. , When one of the ropes is in a phase state of either the lead phase or the lag phase with respect to the other rope, temporarily stores data corresponding to this phase difference, and either the lead phase or the lag phase is stored. In the other phase state, by changing the address of the storage means that gives data corresponding to this phase difference to the other rope, and the address of the data row stored in this buffer circuit In the independent inter-synchronous network buffer device, which has a centering means for matching the address substantially in the center of the address assigned to the storage area of the buffer circuit, the above-mentioned central Plesiochronous networks buffer apparatus characterized by comprising an activation means for activating the grayed means.