JPH0690587A - Phase-locked controller - Google Patents

Abstract

PURPOSE:To output a phase signal closer to a real value even in the case that there is a disturbance in the inputted phase signal. CONSTITUTION:An angle compensating signal domega is sought by grading the difference between a sampled and held input phase signal theta and an output phase signal sampled and held in the same cycle. An angle speed signal omegais compensated by adding the angle speed compensating signal domega to the input angle speed signal omega, and the difference between input and output of the phase signal is reflected in the angle speed. An output phase signal thetao smooth and close to a real value is gotten by Integrating the compensated angle speed signal being gotten this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization control device for processing a synchronization phase signal used for controlling a synchronous motor, for example, a phase signal input at a coarse period and a phase signal having a denser period. The present invention relates to a phase synchronization control device for converting to and outputting.

[0002]

2. Description of the Related Art As an example of a device using a phase synchronization control device, FIG. 3 shows an example of the configuration of a drive device for a synchronous motor. Here, the main circuit is composed of a DC power source 30, P in order from the power source side.
It is composed of a WM inverter 31 and a synchronous motor (SM) 33. The phase angle (θ) and the angular velocity (ω) of the synchronous motor 33 are detected by the position detector 34, and the detection output thereof is transmitted via the transmission device 35 every predetermined time (sampling period) Ts to the phase synchronization control device 36 (details are described below). (See below with reference to FIG. 4). The phase synchronization control device 36 is based on the input phase signal θ and is more detailed (shorter period).
The phase signal θo is output to the SIN table 37. S
The IN table 37 is a three-phase (U, V, W) SIN having a value corresponding to each phase point corresponding to the input phase signal θo.
Generate a wave signal. The phase synchronization control device 36 also outputs a velocity signal v corresponding to the angular velocity signal ω and sends it to the velocity control circuit 38. The speed control circuit 38 outputs the current peak value command Im ^* corresponding to the input speed signal v. Based on the current peak value command Im ^* and the SIN wave signal output from the SIN table 37, the multiplier 39 multiplies both by the three-phase current commands Iu ^* , Iv ^* ,
Form Iw ^* and send it to current control circuit 40.
When the phase angle of the U-phase current is θu, the current command for each of the three phases is expressed as follows.

Iu ^* = Im ^* · sin θu (1) Iv ^* = Im ^* · sin (θu-2π / 3) (2) Iw ^* = Im ^* · sin (θu-4π / 3) (3) ) The current control circuit 40 controls the output of the PWM inverter 31 via the PWM control circuit 41 so that the motor current detected by the current detector 32 matches the current commands Iu ^* , Iv ^* , Iw ^* .

Details of the phase synchronization controller 36 will be described with reference to FIG. The phase synchronization control device 36 includes a phase input unit 11, an angular velocity input unit 12, a sample hold circuit 13.
a, a sample hold circuit 13b, an integrator 14, an adder 15, a phase output section 16, and a speed output section 17. The phase signal θ sequentially input to the phase input unit 11 is sampled by the sampling and holding circuit 13a at the sampling cycle T.
The angular velocity signal ω sampled and held at s and input to the angular velocity input unit 12 is the sample and hold circuit 13b.
Therefore, the sample is held at the same sampling period Ts. The angular velocity signal ωi sample-held by the sample-hold circuit 13b is, on the one hand, the integrator 14
Thus, the speed is integrated (integrated) in a shorter cycle dt, and on the other hand, the speed output section 17 outputs the speed signal v. The output signal of the integrator 14 is added to the phase signal θi held in the sample hold circuit 13b by the adder 15 at the cycle dt and output from the phase output unit 16 as the phase signal θo at the cycle dt. The period dt is synchronized with the clock periods of the speed control circuit 38 and the current control circuit 40 shown in FIG.

FIG. 5 is a diagram showing an example of sampling states of the input phase signal and the sampled and held phase signal. T
o is one cycle of the input phase signal θ, Ts is one sampling cycle, and θm is the maximum value of the phase angle within one cycle, for example, 2
π.

FIG. 6 shows a comparison between an input phase signal (on a solid line) and a true phase signal (on a broken line) when a disturbance based on a detection error or the like is included. θi, θi + 1, θi + 2
, ... are the sampled values of the input phase signal by the sampling of the i-th, i + 1-th, i + 2-th, ...
i, ωi + 1, ωi + 2, ... Are sample values of the input angular velocity signal by the sampling of the i-th time, the i + 1-th time, the i + 2-th time ,.

[0007]

In the conventional phase synchronization control device 36 shown in FIG. 4, the phase signal θ and the angular velocity signal ω are used as input signals to output the phase signal θo having a shorter cycle. However, when the input phase signal θ has a disturbance due to a detection error or the like, as can be seen from FIG. 6, the output phase signal θo deviates from the true phase value and is distorted as a result. You will lose control.

Therefore, it is an object of the present invention to provide a phase synchronization control device capable of outputting a phase signal closer to the true value even when there is a disturbance in the input phase signal.

[0009]

In order to achieve the above object, a phase synchronization controller according to the present invention provides an input phase signal sampled and held at a predetermined sampling period and an output phase signal sampled and held at the same sampling period. And an integrator that outputs a corrected phase signal by integrating the angular velocity signal input in relation to the phase signal and corrected by the angular velocity correction signal. , And a phase output unit for outputting the phase signal obtained by the integrator in a cycle shorter than the sampling cycle.

[0010]

In the phase synchronization control device according to the present invention, the angular velocity correction signal is weighted by the difference between the input phase signal θ sampled and held at a predetermined sampling cycle and the output phase signal sampled and held at the same sampling cycle. Find dω. The input angular velocity signal ω is corrected by adding the angular velocity correction signal dω to the input angular velocity signal ω,
The input / output difference of the phase signal is reflected in the angular velocity. By integrating the corrected angular velocity signal thus obtained,
An output phase signal θo that is smooth and close to the true value can be obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings.

FIG. 1 shows an embodiment of a phase synchronization controller according to the present invention. Here, as an example, a case where a phase signal sampled one time before is used and reflected in the angular velocity will be described.

The phase synchronization controller 36 of FIG. 1 comprises a phase input section 11, an angular velocity input section 12, and a sample hold circuit 13.
a, 13b, 13c, phase output unit 16, speed output unit 1
7, a subtractor 21, a compensation calculation unit 22, an adder 23, and an integrator 24. Here, the same reference numerals as those in FIG. 4 indicate circuit portions having the same or similar functions.

In the phase synchronization controller shown in FIG. 4,
The phase signal θ is input to the sample hold circuit 13a via the phase input section 11 and sampled and held therein at the sampling cycle Ts. Sample hold circuit 13a
The phase signal θi sampled and held by the sample and hold circuit 1 at the same sampling period Ts
The subtracter 21 obtains the difference from the previous output phase signal .theta.i-1 sampled and held by 3c as the phase difference signal d.theta. =. Theta.i-.theta.i-1. The compensation calculation unit 22 obtains the average angular velocity for the period Ts by dividing the phase difference signal dθ by the sampling period Ts, performs appropriate weighting by multiplying it by an appropriate gain k, and obtains the angular velocity correction signal dω. On the other hand, the angular velocity signal ωi is obtained as a sample hold value via the angular velocity input unit 12 and the sample hold circuit 13b having the sampling period Ts. This angular velocity signal ωi is corrected by the addition of the angular velocity correction signal dω in the adder 23, and is further integrated (integrated) by the integrator 24 in the period dt shorter than the sampling period Ts to form the phase signal θo. This phase signal θo is, on the one hand, the phase output unit 1
6 to the SIN table 37 (see FIG. 3) and, on the other hand, the sample hold circuit 13c.
Is sampled and held at the sampling cycle Ts by
It is sent to the subtractor 21 as the previous phase signal θi-1. In this way, by correcting the angular velocity signal ωi with the angular velocity correction signal dω obtained based on the difference from the previous phase signal, the angular velocity signal reflecting the input disturbance is obtained, and the angular velocity signal is further calculated by the integrator 24. The phase output unit 16 integrates at the cycle dt and outputs it as the phase signal θo at the cycle dt. The angular velocity signal ωi obtained via the sample hold circuit 13b is output from the velocity output unit 17 in the cycle dt.
Is output as a speed signal v and is sent to the speed control circuit 38 (FIG. 3).

FIG. 2 is a diagram showing a comparison between an input phase signal (solid line) containing a disturbance and a true phase signal (dashed line) in the apparatus of FIG. 1, which is shown corresponding to FIG. .
Also here, θi, θi + 1, θi + 2, ... Show the sampled values of the input phase signal by the sampling of the i-th time, the i + 1-th time, the i + 2-th time, and also ωi, ωi + 1, ωi. +2, ... Show the sampled value of the input angular velocity signal by the sampling of the i-th time, the i + 1-th time, the i + 2-th time ,. It can be seen that the control device of the present invention can output the output phase signal closer to the true value.

As described above, in the phase synchronization control device of the type in which the phase signal and the angular velocity signal are input and the sample and hold are performed at a constant sampling period, even when the input value includes disturbance, By taking the difference between the current input phase value and the previous input phase value and reflecting the difference in the angular velocity, a smooth output phase signal close to the true value can be obtained.

[0017]

According to the present invention, the input angular velocity signal ω is corrected by taking into consideration the influence of the disturbance, so that the input phase signal including the disturbance is sampled and held at a constant sampling time to have a more true value. It can be output as a close output phase signal. Therefore, more accurate motor control can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a drive control device for a synchronous motor according to the present invention.

2 is a diagram showing a comparison between an input phase signal including a disturbance and a true phase signal in the apparatus of FIG.

FIG. 3 is a block diagram showing a configuration example of a drive control device for a general synchronous motor.

FIG. 4 is a block diagram showing an internal configuration of the phase synchronization control device in FIG.

5 is a diagram showing an example of a sampled state of an input phase signal and a sampled and held phase signal in the apparatus of FIG.

6 is a diagram showing a comparison between an input phase signal including a disturbance and a true phase signal in the device of FIG.

[Explanation of symbols]

 11 phase input unit 12 angular velocity input unit 13a, 13b, 13c sample hold circuit 16 phase output unit 17 velocity output unit 21 subtractor 22 compensation calculation unit 23 adder 24 integrator 31 PWM inverter 33 synchronous motor 34 position detector 35 transmission device 36 Phase Synchronous Control Device 37 SIN Table 38 Speed Control Circuit 39 Multiplier 40 Current Control Circuit 41 PWM Control Circuit

Claims (1)

[Claims] 1. A compensation calculation unit for obtaining an angular velocity correction signal by weighting a difference between an input phase signal sampled and held at a predetermined sampling cycle and an output phase signal sampled and held at the same sampling cycle, and the phase signal. And an integrator that outputs a corrected phase signal by integrating the angular velocity signal corrected by the angular velocity correction signal, and a phase signal obtained by this integrator at a cycle shorter than the sampling cycle. A phase synchronization control device comprising a phase output section for outputting.