JPH0690277B2 - Digital pulse compressor - Google Patents
Digital pulse compressorInfo
- Publication number
- JPH0690277B2 JPH0690277B2 JP63186396A JP18639688A JPH0690277B2 JP H0690277 B2 JPH0690277 B2 JP H0690277B2 JP 63186396 A JP63186396 A JP 63186396A JP 18639688 A JP18639688 A JP 18639688A JP H0690277 B2 JPH0690277 B2 JP H0690277B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- digital
- filter coefficient
- pulse compression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パルス圧縮レーダ用に用いられるディジタ
ル・パルス圧縮装置に関するものである。The present invention relates to a digital pulse compression device used for pulse compression radar.
一般に、パルス圧縮レーダは、リニアFM波形やバーカー
・コードによる位相変調波形のように自己相関関数がイ
ンパルスに近い波形をもつパルスを送受信し、受信処理
において受信信号と送信信号波形の相互相関をとること
により受信パルスを時間軸上で圧縮するとともに振幅方
向へ積み上げ、信号対雑音比の改善及び距離分解能の向
上を図るものである。この構成は、M.I.スコルニクレー
ダーハンドブック”マグローヒル インターナショナル
ブックカンパニー20-1〜20-4頁（M.I.Skolnik Radar Ha
ndbook"McGraw-Hill International Book Company pp.2
0-1〜20-4）で示されているようにマッチド・フィルタ
回路で構成され、従来パルス圧縮処理をディジタル回路
で実現する方法としては第３図に示すものがあった。In general, pulse compression radar transmits and receives pulses with a waveform whose autocorrelation function is close to an impulse, such as a linear FM waveform or a phase modulation waveform by Barker code, and cross-correlates the received signal and the transmitted signal waveform in the reception process. Thus, the received pulses are compressed on the time axis and piled up in the amplitude direction to improve the signal-to-noise ratio and distance resolution. This configuration is based on MI Skornik Radar Handbook "Maglow Hill International Book Company" pages 20-1 to 20-4 (MISkolnik Radar Ha
ndbook "McGraw-Hill International Book Company pp.2
0-1 to 20-4), a conventional method for realizing pulse compression processing by a digital circuit is shown in FIG. 3, which is constituted by a matched filter circuit.
第３図においては、１は同期位相検波器、２はA/D変換
器、３は高速フーリエ変換回路（以下、「FFT回路」と
いう）、４は複素乗算器、５はフィルタ係数メモリ、６
は逆フーリエ変換回路（以下、「IFFT」という）であ
る。In FIG. 3, 1 is a synchronous phase detector, 2 is an A / D converter, 3 is a fast Fourier transform circuit (hereinafter referred to as “FFT circuit”), 4 is a complex multiplier, 5 is a filter coefficient memory, 6
Is an inverse Fourier transform circuit (hereinafter referred to as "IFFT").
以下、この従来技術の動作について説明する。The operation of this prior art will be described below.
同期位相検波器１及びA/D変換器２を経た時系列の受信
信号ｘ（ｔ）はFFT回路３によりフーリエ変換され、周
波数スペクトラムＸ（ω）に変換される。一方、フィル
タ係数メモリ５は、予め送信信号の周波数スペクトルの
複素共役値Ｘ＊（ω）を計算して記憶させてあり、複素
乗算器４により受信信号スペクトラムＸ（ω）との積が
とられる。この乗算結果は、IFFT回路６により逆フーリ
エ変換されて再び時系列に戻され、出力ｙ（ｔ）とな
る。The time-series reception signal x (t) that has passed through the synchronous phase detector 1 and the A / D converter 2 is Fourier-transformed by the FFT circuit 3 to be converted into a frequency spectrum X (ω). On the other hand, the filter coefficient memory 5 has previously calculated and stored the complex conjugate value X * (ω) of the frequency spectrum of the transmission signal, and the complex multiplier 4 takes the product with the reception signal spectrum X (ω). . The result of this multiplication is subjected to inverse Fourier transform by the IFFT circuit 6 and returned to the time series again to become the output y (t).
上記の処理によりｙ（ｔ）は式（１）のように表すこと
ができる。By the above processing, y (t) can be expressed as in Expression (1).
式（１）をウィナー ヒンチン（Wiener-Khintchine）
の定理により書き直すと、式（２）となる。 Wiener-Khintchine from equation (1)
When rewritten by the theorem of, it becomes equation (2).
式（２）は受信信号の自己相関関数であるため、ｙ
（ｔ）はインパルス状の波形として出力され、パルス圧
縮動作がなされることになる。 Since equation (2) is the autocorrelation function of the received signal, y
(T) is output as an impulse-shaped waveform, and pulse compression operation is performed.
なお、IF信号入力を同期位相検波器１でCOHOとの位相検
波を行って直交ベクトルI/Qビデオに変換し、A/D変換器
２で変換クロック毎にディジタル信号に変換する動作に
ついては周知のことであり、説明を省略する。Note that the operation of converting the IF signal input into a quadrature vector I / Q video by performing phase detection with COHO with the synchronous phase detector 1 and converting into a digital signal at each conversion clock with the A / D converter 2 is well known. The description is omitted.
さらに、A/D変換器２においては、変換クロックの周期
が実際上は有限の値であることから、変換時の周波数特
性歪みが存在し、別途得られたフィルタ係数との間に不
整合が生じることも周知のことである。Furthermore, in the A / D converter 2, since the conversion clock cycle is actually a finite value, there is frequency characteristic distortion during conversion, and there is a mismatch with the separately obtained filter coefficient. It is also well known that it occurs.
従来のディジタル・パルス圧縮装置は、以上のように構
成されているので、送受信波形毎に、それに対応したフ
ィルタ係数をROM等のフィルタ係数メモリ上に用意して
おく必要があり、汎用性に欠けるとともに送受信波形を
多種使い分けるようなレーダにおいては、フィルタ係数
メモリを多数設けて切換え使用せねばならず、ハード・
ウェア規模の増大を招くという欠点があった。Since the conventional digital pulse compression device is configured as described above, it is necessary to prepare a filter coefficient corresponding to each transmitted / received waveform in a filter coefficient memory such as ROM, which lacks versatility. In addition, in a radar that uses different transmission and reception waveforms, it is necessary to provide a large number of filter coefficient memories and switch between them.
There was a drawback that it caused an increase in wear scale.
また、一般にディジタル・パルス圧縮装置では上述のよ
うにIF信号を同期位相検波器及びA/D変換器によりベク
トルI/Qビデオを経てディジタル信号に変換することが
不可欠であるが、上記従来装置ではこれらの変換誤差を
考慮したフィルタ係数の設定が困難であった。In general, in a digital pulse compression device, it is indispensable to convert an IF signal into a digital signal via a vector I / Q video by a synchronous phase detector and an A / D converter as described above. It was difficult to set the filter coefficient in consideration of these conversion errors.
この発明は、上記のような問題点を解消するためになさ
れたものであり、任意の送受信波形に対し、A/D変換系
の変換誤差を含めた形で適応できて汎用性のある、しか
も若干のハード・ウェア規模の増加で実現することので
きるディジタル・パルス圧縮装置を得ることを目的とす
る。The present invention has been made to solve the above problems, and is versatile and can be applied to any transmission / reception waveform in a form including the conversion error of the A / D conversion system. It is an object of the present invention to obtain a digital pulse compression device which can be realized with a slight increase in the hardware scale.
この発明に係るディジタル・パルス圧縮装置は、先ず初
期設定として送信信号発生回路からの送信信号をパルス
圧縮回路の入力へ供給し、受信処理と同様にA/D変換及
びFFT回路でのフーリエ変換を行い、その周波数スペク
トラム出力をフィルタ係数メモリの方へ切換えて複素共
役をとった後、フィルタ係数メモリへ記憶させ、受信処
理時には、受信信号をパルス圧縮入力へ供給するととも
に、FFT回路出力を複素乗算器側へ切換えて上記フィル
タ係数メモリから読み出したフィルタ係数と乗算し、さ
らにこれをIFFT回路に通してパルス圧縮を行うものであ
る。The digital pulse compression device according to the present invention first supplies the transmission signal from the transmission signal generation circuit to the input of the pulse compression circuit as an initial setting, and performs the A / D conversion and the Fourier transform in the FFT circuit as in the reception process. Then, the frequency spectrum output is switched to the filter coefficient memory to take the complex conjugate and then stored in the filter coefficient memory.When receiving, the received signal is supplied to the pulse compression input and the FFT circuit output is complex-multiplied. It is switched to the device side, multiplied by the filter coefficient read from the filter coefficient memory, and further passed through an IFFT circuit to perform pulse compression.
この発明においては、フィルタ係数用メモリの内容は、
上記のように既存のA/D変換系及びFFT回路を用いて送信
信号から生成されるので、A/D変換系の変換誤差を考慮
した形で、送信信号波形の変化に適応することができ、
しかもかかる汎用性のあるディジタル・パルス圧縮装置
を若干のハード・ウェア規模の増加で得ることができ
る。In the present invention, the contents of the filter coefficient memory are
Since it is generated from the transmission signal using the existing A / D conversion system and FFT circuit as described above, it is possible to adapt to changes in the transmission signal waveform in consideration of the conversion error of the A / D conversion system. ,
Moreover, such a versatile digital pulse compressor can be obtained with a slight increase in the hardware scale.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるディジタル・パルス圧
縮装置を示し、図において、１は同期位相検波器、２は
A/D変換器、３はFFT回路、４は複素乗算器、５はフィル
タ係数メモリ、６はIFFT回路、７は送信信号生成回路、
８は送信信号と受信信号を切換えるアナログ切換器、９
はディジタル切換器、10は複素共役回路である。FIG. 1 shows a digital pulse compressor according to an embodiment of the present invention, in which 1 is a synchronous phase detector and 2 is a synchronous phase detector.
A / D converter, 3 FFT circuit, 4 complex multiplier, 5 filter coefficient memory, 6 IFFT circuit, 7 transmission signal generation circuit,
8 is an analog switch for switching between a transmission signal and a reception signal, 9
Is a digital switch, and 10 is a complex conjugate circuit.
本実施例においては第３図の従来回路に比し、IF切換器
８、ディジタル切換器９、及び複素共役回路10が付加さ
れている。In this embodiment, an IF switch 8, a digital switch 9 and a complex conjugate circuit 10 are added as compared with the conventional circuit shown in FIG.
以下、第１図を用いて、本実施例の作用、動作について
説明する。The operation and operation of this embodiment will be described below with reference to FIG.
初期設定時、アナログ切換器８は、送信信号生成回路７
の出力を通し、IF受信信号入力を遮断するように切換え
られている。又、ディジタル切換器９は複素共役回路10
へ出力が得られるように切換えられており、送信信号は
同期位相検波器１及びA/D変換器２を経て、ディジタル
信号に変換されてFFT回路３でフーリエ変換されて、周
波数スペクトラムＸ（ω）に変換される。このＸ（ω）
はディジタル切換器９を経て、複素共役回路10へ導か
れ、複素共役値Ｘ＊（ω）に変換されてフィルタ係数メ
モリ５に書き込まれる。At the time of initial setting, the analog switch 8 has the transmission signal generation circuit 7
It is switched so that the IF reception signal input is cut off through the output of. The digital switch 9 is a complex conjugate circuit 10
The transmission signal is converted to a digital signal through the synchronous phase detector 1 and the A / D converter 2 and is Fourier-transformed by the FFT circuit 3 to obtain the frequency spectrum X (ω ) Is converted to. This X (ω)
Is guided to the complex conjugate circuit 10 through the digital switch 9, converted into the complex conjugate value X * (ω), and written in the filter coefficient memory 5.
次に、パルス圧縮動作時には、アナログ切換器８はIF受
信信号入力を通し、送信信号を遮断するように切換えら
れ、ディジタル切換器９は複素乗算器４へ出力が得られ
るように切換えられており、IF信号入力は、FFT回路３
までは上記と同様の処理がなされ、ディジタル切換器９
にて、複素乗算器４へＸ（ω）を出力する。一方、フィ
ルタ係数メモリ５は、初期設定により設定されたＸ
＊（ω）を読み出し、複素乗算器４でＸ（ω）・Ｘ
＊（ω）の乗算を行って、IFFT回路６により逆フーリエ
変換されて、時系列上のパルス圧縮出力を得る。Next, during the pulse compression operation, the analog switch 8 is switched so as to pass the IF received signal input and block the transmission signal, and the digital switch 9 is switched so as to obtain an output to the complex multiplier 4. , IF signal input is FFT circuit 3
Up to the above, the same processing as described above is performed, and the digital switch 9
Then, X (ω) is output to the complex multiplier 4. On the other hand, the filter coefficient memory 5 has the X value set by the initial setting.
* (Ω) is read out and X (ω) · X is obtained by the complex multiplier 4.
* (Ω) is multiplied and inverse Fourier transformed by the IFFT circuit 6 to obtain a time-series pulse compression output.
次に、第２図は本発明の第２の実施例として、直交ベク
トルI/Qビデオでの送受信信号の切換えを行った例を示
す。Next, FIG. 2 shows, as a second embodiment of the present invention, an example in which transmission / reception signals are switched in an orthogonal vector I / Q video.
この第２の実施例は第１図の第１の実施例に対し、送信
信号波形を直交ベクトルI/Qビデオの段階で描出し、A/D
変換器２入力で送受信号を切換えるようにした点が相違
する。This second embodiment is different from the first embodiment shown in FIG. 1 in that the transmission signal waveform is drawn at the stage of orthogonal vector I / Q video, and A / D
The difference is that the transmitter / receiver is switched by the input of the converter 2.
本第２の実施例においても、A/D変換器２の変換誤差を
含むフィルタ係数が得られることから、上記第１の実施
例と同様の効果が得られる。Also in the second embodiment, since the filter coefficient including the conversion error of the A / D converter 2 is obtained, the same effect as that of the first embodiment can be obtained.
なお、上記実施例では複素共役回路10をディジタル切換
器９とフィルタ係数メモリ５の間に設けているが、フィ
ルタ係数メモリ５と複素乗算器４との間、又はディジタ
ル切換器９と複素乗算器４との間に設けてもよく、上記
と同様の効果が得られることはいうまでもない。Although the complex conjugate circuit 10 is provided between the digital switch 9 and the filter coefficient memory 5 in the above embodiment, it may be provided between the filter coefficient memory 5 and the complex multiplier 4 or between the digital switch 9 and the complex multiplier 4. It is needless to say that the same effect as described above can be obtained by providing the same between No. 4 and No. 4.
また、複素共役回路10で単に複素共役を行うのみでな
く、上述したレーダーハンドブック”に示されているよ
うなレンジ・サイドローブ抑圧用ウェイティング係数を
乗じてもよく、本質的に上記と同様の効果が得られる。Further, not only the complex conjugation is performed by the complex conjugation circuit 10, but the weighting coefficient for range / sidelobe suppression as shown in the above-mentioned Radar Handbook "may be multiplied, and the effect is essentially the same as the above. Is obtained.
以上のように、この発明によれば、ディジタル・パルス
圧縮装置の一部をなすA/D変換系及びFFT回路を用いてフ
ィルタ係数を得るように構成したので、A/D変換系の変
換誤差を含めた形で任意の送受信波形に適応でき、汎用
性のあるディジタル・パルス圧縮装置を若干のハード・
ウェア規模の増加で実現することができる効果がある。As described above, according to the present invention, since the filter coefficient is obtained using the A / D conversion system and the FFT circuit which are part of the digital pulse compression device, the conversion error of the A / D conversion system It can be applied to any transmission / reception waveform in a form including
There is an effect that can be realized by increasing the scale of wear.
第１図はこの発明の第１の実施例によるディジタル・パ
ルス圧縮装置を示す系統図、第２図はこの発明の第２の
実施例を示す系統図、第３図は従来のディジタル・パル
ス圧縮装置を示す系統図である。 図において、１は同期位相検波器、２はA/D変換器、３
はFFT回路、４は複素乗算器、５はフィルタ係数メモ
リ、６はIFFT回路、７は送信信号生成回路、８はアナロ
グ切換器、９はディジタル切換器、10は複素共役回路で
ある。 なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a system diagram showing a digital pulse compression apparatus according to a first embodiment of the present invention, FIG. 2 is a system diagram showing a second embodiment of the present invention, and FIG. 3 is a conventional digital pulse compression. It is a systematic diagram which shows an apparatus. In the figure, 1 is a synchronous phase detector, 2 is an A / D converter, 3
Is an FFT circuit, 4 is a complex multiplier, 5 is a filter coefficient memory, 6 is an IFFT circuit, 7 is a transmission signal generation circuit, 8 is an analog switch, 9 is a digital switch, and 10 is a complex conjugate circuit. The same reference numerals in the drawings indicate the same or corresponding parts.
Claims (1)
ス圧縮装置において、 中間周波数帯の送信信号と受信信号とを切り換えるアナ
ログ切換器と、 該アナログ切換器からのIF帯の送信信号または受信信号
入力を直交ベクトルI/Qビデオに変換する同期位相検波
器と、 該直交ベクトルI/Qビデオをディジタル信号に変換するA
/D変換器と、 その出力をフーリエ変換するFFT回路と、 その出力を複素共役回路側と複素乗算器側とに切り換え
るディジタル切換器と、 その出力の複素共役をとる複素共役回路と、 その出力を記憶するフィルタ係数メモリと、 上記ディジタル切換器からの出力に上記フィルタ係数メ
モリの出力を複素乗算する複素乗算器と、 その出力を逆フーリエ変換するIFFT回路とを備え、パル
ス圧縮波形を得ることを特徴とするディジタル・パルス
圧縮装置。1. A digital pulse compressor for a pulse radar, wherein an analog switch for switching between a transmission signal and a reception signal in an intermediate frequency band and an IF band transmission signal or a reception signal input from the analog switching device are orthogonal to each other. Synchronous phase detector for converting vector I / Q video and A for converting the quadrature vector I / Q video into digital signal
/ D converter, FFT circuit that performs Fourier transform of its output, digital switch that switches its output between complex conjugate circuit side and complex multiplier side, complex conjugate circuit that takes the complex conjugate of its output, and its output And a filter coefficient memory for storing, a complex multiplier for complexly multiplying the output from the digital switch with the output of the filter coefficient memory, and an IFFT circuit for inverse Fourier transforming the output to obtain a pulse compression waveform. A digital pulse compression device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63186396A JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63186396A JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0236385A JPH0236385A (en) | 1990-02-06 |
| JPH0690277B2 true JPH0690277B2 (en) | 1994-11-14 |
Family
ID=16187669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63186396A Expired - Fee Related JPH0690277B2 (en) | 1988-07-26 | 1988-07-26 | Digital pulse compressor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0690277B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0566268A (en) * | 1991-09-06 | 1993-03-19 | Mitsubishi Electric Corp | Digital pulse compression device |
| JP5429699B2 (en) * | 2007-01-16 | 2014-02-26 | 日本無線株式会社 | Compression coefficient generator |
| JP2008292343A (en) * | 2007-05-25 | 2008-12-04 | Nec Engineering Ltd | Fm-cw radar |
| JP2011191133A (en) * | 2010-03-12 | 2011-09-29 | Toshiba Denpa Products Kk | Pulse compression device of radar reception signal |
| JP6248923B2 (en) | 2012-02-20 | 2017-12-20 | 日本電気株式会社 | Digital filter circuit, digital filter processing method, and digital filter processing program |
-
1988
- 1988-07-26 JP JP63186396A patent/JPH0690277B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0236385A (en) | 1990-02-06 |
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