JPH0690250B2 - AC signal measuring circuit - Google Patents

AC signal measuring circuit

Info

Publication number
JPH0690250B2
JPH0690250B2 JP1710085A JP1710085A JPH0690250B2 JP H0690250 B2 JPH0690250 B2 JP H0690250B2 JP 1710085 A JP1710085 A JP 1710085A JP 1710085 A JP1710085 A JP 1710085A JP H0690250 B2 JPH0690250 B2 JP H0690250B2
Authority
JP
Japan
Prior art keywords
signal
under test
device under
output
crystal oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1710085A
Other languages
Japanese (ja)
Other versions
JPS61176864A (en
Inventor
俊雄 玉村
Original Assignee
横河・ヒユ−レツト・パツカ−ド株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河・ヒユ−レツト・パツカ−ド株式会社 filed Critical 横河・ヒユ−レツト・パツカ−ド株式会社
Priority to JP1710085A priority Critical patent/JPH0690250B2/en
Priority to EP86101126A priority patent/EP0192981B1/en
Priority to DE8686101126T priority patent/DE3667862D1/en
Priority to US06/824,026 priority patent/US4860227A/en
Publication of JPS61176864A publication Critical patent/JPS61176864A/en
Publication of JPH0690250B2 publication Critical patent/JPH0690250B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は交流信号の測定回路、特に該交流信号の振幅,
位相測定回路に係る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a measuring circuit for an AC signal, and in particular, the amplitude of the AC signal
It relates to a phase measuring circuit.

〔従来技術及びその問題点〕[Prior art and its problems]

一般に被測定素子(例えば抵抗器やコンデンまたは増幅
器)に印加し、そしてその通過信号と印加信号との関係
(例えば電圧、電流の大きさおよび移相量)から、前記
被測定素子のインピーダンスまたは回路自体の利得、位
相を測定する場合に単一の交番信号源を用いていたが、
この場合の信号源は極めて複雑であつた。これを解決す
るために第1図に示すように二つのフラクシヨナルN発
振器を用いていた。これについては本出願人が同日に出
願し、そして「交流信号の振幅,位相測定回路」と題し
た明細書に詳述されている。すなわち、図において、1
0、20はフラクシヨナルN発振器、30は水晶発振器、12
は被測定素子(例えば抵抗器)、13、15はサンプラ、1
4、16はアナログ・デジタル変換器、17はマイクロプロ
セツサである。この場合、測定誤差の要因の一つに前記
フラクシヨナルN発振器自体のジツターや位相雑音があ
る。また、高品質の出力信号を得るために水晶発振器を
用いて実現できるが、この場合の入力信号とサンプリン
グ信号の周波数は単一であり、任意所望の分割数をもつ
たサンプリング信号を得ることは不可能であつた。な
お、フラクシヨナルN発振器とはフラクシヨナル(分
数)N技法を用いた位相ロックループで構成されたもの
であり、ここでは電圧制御発振器(VCO)の出力周波数
を、位相検出器に印加される基準周波数の有理数(整数
+少数)倍にすることができる。これは、負帰還ループ
における分周器の分周比Nを等価的に有理数にすること
により達成される。フラクシヨナルN技法に関する詳細
は、米国特許第3,928,813号あるいは特開昭51-60148な
どに開示されている。
Generally, the impedance or circuit of the device to be measured is applied to the device to be measured (for example, resistor, condensor or amplifier), and the relationship between the passing signal and the applied signal (for example, voltage, magnitude of current and amount of phase shift). I used a single alternating signal source to measure its own gain and phase,
The signal source in this case was extremely complicated. In order to solve this, two fractional N oscillators were used as shown in FIG. This is filed by the applicant on the same day and is described in detail in the specification entitled "Amplitude and phase measuring circuit for AC signals". That is, in the figure, 1
0 and 20 are fractional N oscillator, 30 is crystal oscillator, 12
Is the device under test (eg, resistor), 13 and 15 are samplers, 1
Reference numerals 4 and 16 are analog-to-digital converters, and 17 is a microprocessor. In this case, one of the factors of the measurement error is the jitter and phase noise of the fractional N oscillator itself. Also, it can be realized by using a crystal oscillator to obtain a high-quality output signal, but in this case the frequency of the input signal and the sampling signal is single, and it is not possible to obtain a sampling signal with any desired number of divisions. It was impossible. The fractional-N oscillator is composed of a phase-locked loop using the fractional (fractional) N technique. Here, the output frequency of the voltage-controlled oscillator (VCO) is the reference frequency applied to the phase detector. It can be multiplied by a rational number (integer + minority). This is achieved by making the frequency division ratio N of the frequency divider in the negative feedback loop equivalently rational. Details regarding the fractional N technique are disclosed in U.S. Pat. No. 3,928,813 or JP-A-51-60148.

〔発明の目的〕[Object of the Invention]

本発明は上述の欠点を除去するためになされたものであ
る。
The present invention has been made to eliminate the above-mentioned drawbacks.

〔発明の概要〕[Outline of Invention]

本発明の一実施例によれば、電圧制御型水晶発振器の出
力をサンプリング信号として用い、且つその出力周波数
はフラクシヨナルN発振器により任意の所定値に設定す
ることができる。
According to one embodiment of the present invention, the output of the voltage controlled crystal oscillator is used as a sampling signal, and the output frequency can be set to an arbitrary predetermined value by the fractional N oscillator.

〔発明の実施例〕Example of Invention

第2図は本発明の一実施例による測定回路の電気的回路
図である。図において、30は水晶発振器、11はフイルタ
で、該フイルタを通過した交番信号は被測定素子12に導
入される。ここで、被測定素子12の出力信号および入力
信号はそれぞれサンプラ13、15の各一方の入力端に印加
される。他方、前記サンプラ13、15に導入されるサンプ
リング信号は本発明によれば、次の手段で得られる。す
なわち、前記水晶発振器30の出力はフラクシヨナルN発
振器20に導入され、その出力が位相検出器21の一方の入
力端に印加される。ここで、前記位相検出器21およびフ
イルタ22と電圧制御型水晶発振器23とで閉ループを構成
し、そして前記電圧制御型水晶発振器23の出力を前記位
相検出器21の他方の入力端に印加するとともに、該出力
を前述のサンプリング信号とする。
FIG. 2 is an electric circuit diagram of a measuring circuit according to an embodiment of the present invention. In the figure, 30 is a crystal oscillator, 11 is a filter, and the alternating signal that has passed through the filter is introduced into the device under test 12. Here, the output signal and the input signal of the device under test 12 are applied to the respective one input ends of the samplers 13 and 15, respectively. On the other hand, the sampling signals introduced into the samplers 13 and 15 are obtained by the following means according to the present invention. That is, the output of the crystal oscillator 30 is introduced into the fractional-N oscillator 20, and its output is applied to one input end of the phase detector 21. Here, the phase detector 21 and the filter 22 and the voltage control type crystal oscillator 23 constitute a closed loop, and the output of the voltage control type crystal oscillator 23 is applied to the other input end of the phase detector 21. , The output is the sampling signal described above.

ここで、前記被測定素子に印加される信号の周期をT、
サンプリング信号の周期をtとした場合、 t=nT+T/m の関係をもたせる(但しm、nは正の整数で、且つmは
サンプル数である)。上述の信号で、例えば水晶発振器
30の出力周波数を100MHzとした場合、そのサンプリング
信号の周波数を約1MHz近傍とすれば、前記100MHzの一周
期を何分割するかによりその設定周波数が決まる。この
設定周波数は第2図のフラクシヨナルN発振器20で設定
し、これを電圧制御型水晶発振器23の出力にロツクすれ
ばよい。
Here, the period of the signal applied to the device under test is T,
When the period of the sampling signal is t, the relationship of t = nT + T / m is provided (where m and n are positive integers and m is the number of samples). With the above signal, for example a crystal oscillator
When the output frequency of 30 is 100 MHz and the frequency of the sampling signal is set to about 1 MHz, the set frequency is determined by how many times one cycle of 100 MHz is divided. This set frequency may be set by the fractional-N oscillator 20 shown in FIG. 2 and locked by the output of the voltage-controlled crystal oscillator 23.

例えば、上記の分割数mを10とすればそのサンプリング
信号の周波数fsは1/1.001 MHzとなり、これを16桁に換
算すると 999.000999000999kHzとなる。更には分割数を1000にす
ると、その周波数は999.990000099999000……となる。
すなわち、電圧制御型水晶発振器23の出力信号における
周波数の可変範囲は、分割数の増大に従つて狭くなる
が、ジツターや位相雑音の少ない高品質のサンプリング
信号が任意の周波数で得られるので、実用上の効果大で
ある。
For example, when the division number m is 10, the frequency fs of the sampling signal is 1 / 1.001 MHz, which is 999.000999000999 kHz when converted into 16 digits. Furthermore, if the number of divisions is 1000, the frequency will be 999.990000099999000 ....
That is, the variable range of the frequency in the output signal of the voltage-controlled crystal oscillator 23 becomes narrower as the number of divisions increases, but a high-quality sampling signal with less jitter and phase noise can be obtained at any frequency. The effect is great.

【図面の簡単な説明】[Brief description of drawings]

第1図は交流信号の振幅,位相測定回路を説明するため
の原理図、第2図は本発明の一実施例による交流信号の
振幅,位相測定回路の電気的回路図である。 30:水晶発振器、12:被測定素子、13、15:サンプラ、1
4、16:アナログ・デジタル変換器、17:マイクロプロセ
ツサ、20:フラクシヨナルN発振器、21:位相検出器、2
3:電圧制御型水晶発振器、11,22:低域通過フイルタ。
FIG. 1 is a principle diagram for explaining an AC signal amplitude / phase measuring circuit, and FIG. 2 is an electrical circuit diagram of an AC signal amplitude / phase measuring circuit according to an embodiment of the present invention. 30: Crystal oscillator, 12: Device under test, 13, 15: Sampler, 1
4, 16: Analog-to-digital converter, 17: Microprocessor, 20: Fractional N oscillator, 21: Phase detector, 2
3: Voltage control type crystal oscillator, 11, 22: Low pass filter.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】被測定素子に印加される測定信号と該被測
定素子からの出力信号との振幅、位相関係を測定する回
路において、 前記被測定素子に測定信号を印加する水晶発振器と、 前記測定信号の周期をTとしたとき、t=nT+T/m(た
だし、m、nは正の整数で、mは周期Tにおけるサンプ
ル数)なる関係を有する周期tの信号を発生する第2信
号源と、 前記第2信号源の出力信号を基準入力信号としてこれに
位相ロックする電圧制御型水晶発振器を備えた位相ロッ
クループと、 前記被測定素子からの出力信号を前記電圧制御型水晶発
振器からの出力信号によりサンプリングする第1サンプ
リング手段と、 前記被測定素子に印加される測定信号を前記電圧制御型
水晶発振器からの出力信号によりサンプリングする第2
サンプリング手段と、 前記第1サンプリング手段の出力に接続された第1アナ
ログ・デジタル変換器と、 前記第2サンプリング手段の出力に接続された第2アナ
ログ・デジタル変換器と、 前記第1、第2アナログ・デジタル変換器の出力信号に
基づいて、前記被測定素子に印加される測定信号と、該
被測定素子からの出力信号との振幅、位相関係を算出す
るマイクロプロセッサ手段と、 を備えて成る交流信号の測定回路。
1. A circuit for measuring the amplitude and phase relationship between a measurement signal applied to a device under test and an output signal from the device under test, comprising a crystal oscillator for applying the measurement signal to the device under test, A second signal source that generates a signal of period t having a relationship of t = nT + T / m (where m and n are positive integers and m is the number of samples in period T), where T is the period of the measurement signal. A phase-locked loop having a voltage-controlled crystal oscillator for phase-locking the output signal of the second signal source as a reference input signal; and an output signal from the device under test from the voltage-controlled crystal oscillator. A first sampling means for sampling with an output signal; and a second sampling means for sampling a measurement signal applied to the device under test with an output signal from the voltage controlled crystal oscillator.
Sampling means, a first analog-digital converter connected to the output of the first sampling means, a second analog-digital converter connected to the output of the second sampling means, the first and second Microprocessor means for calculating the amplitude and phase relationship between the measurement signal applied to the device under test and the output signal from the device under test based on the output signal of the analog-to-digital converter. AC signal measuring circuit.
JP1710085A 1985-01-31 1985-01-31 AC signal measuring circuit Expired - Lifetime JPH0690250B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1710085A JPH0690250B2 (en) 1985-01-31 1985-01-31 AC signal measuring circuit
EP86101126A EP0192981B1 (en) 1985-01-31 1986-01-29 Circuit for measuring characteristics of a device under test
DE8686101126T DE3667862D1 (en) 1985-01-31 1986-01-29 CIRCUIT FOR MEASURING THE SIZES OF A TESTED ARRANGEMENT.
US06/824,026 US4860227A (en) 1985-01-31 1986-01-30 Circuit for measuring characteristics of a device under test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1710085A JPH0690250B2 (en) 1985-01-31 1985-01-31 AC signal measuring circuit

Publications (2)

Publication Number Publication Date
JPS61176864A JPS61176864A (en) 1986-08-08
JPH0690250B2 true JPH0690250B2 (en) 1994-11-14

Family

ID=11934591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1710085A Expired - Lifetime JPH0690250B2 (en) 1985-01-31 1985-01-31 AC signal measuring circuit

Country Status (1)

Country Link
JP (1) JPH0690250B2 (en)

Also Published As

Publication number Publication date
JPS61176864A (en) 1986-08-08

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