JPH0689926A - Semiconductor chip and method for repairing its defective circuit - Google Patents
Semiconductor chip and method for repairing its defective circuitInfo
- Publication number
- JPH0689926A JPH0689926A JP26549192A JP26549192A JPH0689926A JP H0689926 A JPH0689926 A JP H0689926A JP 26549192 A JP26549192 A JP 26549192A JP 26549192 A JP26549192 A JP 26549192A JP H0689926 A JPH0689926 A JP H0689926A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- normal
- circuits
- area
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、チップ内の不良回路部
分を補修可能とした半導体チップ、及びこの半導体チッ
プの不良回路の補修方法に関し、特に大面積の半導体チ
ップを構成するのに最適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip capable of repairing a defective circuit portion in a chip and a method of repairing a defective circuit of the semiconductor chip, and is particularly suitable for constructing a large-sized semiconductor chip. It is a thing.
【0002】[0002]
【従来の技術】従来から、半導体チップの製造において
は、半導体ウエハ(Si基板)に複数の同一の回路を配
列して形成し、外観検査及び電気的特性検査によって正
常と判定された回路のみをウエハから分割切断し、個々
の半導体チップとして使用している。2. Description of the Related Art Conventionally, in the manufacture of semiconductor chips, a plurality of identical circuits are arrayed and formed on a semiconductor wafer (Si substrate), and only the circuits judged to be normal by an appearance inspection and an electrical characteristic inspection are formed. The wafer is divided and cut and used as individual semiconductor chips.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、この種
の半導体チップにおいては、チップの面積が大きくなる
程、歩留りが急激に低下していく。即ち、チップ面積を
拡大する程、チップ内に不良回路部分の存在する確率が
高くなり、チップ内に一部でも不良回路部分が存在する
と、他の大部分の正常回路が全て無駄になるからであ
る。従って、多機能かつ高密度な回路を有する大面積の
半導体チップを製造することは、特に歩留り低下の点か
ら非常に困難であった。However, in this type of semiconductor chip, the larger the chip area, the more rapidly the yield decreases. That is, the larger the chip area, the higher the probability that a defective circuit portion will exist in the chip, and if there is a defective circuit portion even in a part of the chip, most other normal circuits will be wasted. is there. Therefore, it has been very difficult to manufacture a large-area semiconductor chip having a multi-functional and high-density circuit, especially from the viewpoint of lowering the yield.
【0004】そこで本発明は、チップ内における不良回
路部分の存在が避け得ないことを前提に、その不良回路
を含んだ全体を正常回路として使用することができるよ
うにした半導体チップ及びこの半導体チップの不良回路
補修方法を提供することを目的とする。Therefore, the present invention provides a semiconductor chip which can be used as a normal circuit as a whole including the defective circuit on the assumption that the defective circuit portion is unavoidable in the chip and the semiconductor chip. It is an object of the present invention to provide a defective circuit repairing method.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体チップは、全体の大面積回路が
複数の小面積回路に分割されていると共に、これら複数
の小面積回路とそれぞれ周囲の小面積回路とが電気的に
切り離し可能に接続されているものである。In order to achieve the above object, in a semiconductor chip according to the present invention, an entire large area circuit is divided into a plurality of small area circuits, and each of the plurality of small area circuits is divided into a plurality of small area circuits. It is connected to the surrounding small area circuit so that it can be electrically disconnected.
【0006】また、本発明による半導体チップは、全体
の大面積回路が複数の小面積回路に分割されていると共
に、これら複数の小面積回路とそれぞれ周囲の小面積回
路とが電気的に切り離し可能に接続されている半導体チ
ップであって、前記複数の小面積回路の電気的特性検査
により動作不良と判定された小面積回路が周囲の正常な
小面積回路から電気的に切り離されていると共に、その
不良回路と同機能で正常な小面積回路を有する補修用ブ
ロックが前記不良回路上に搭載され、この補修用ブロッ
クの正常回路が前記周囲の正常回路に電気的に接続され
ているものである。Further, in the semiconductor chip according to the present invention, the entire large area circuit is divided into a plurality of small area circuits, and the plurality of small area circuits can be electrically separated from the surrounding small area circuits. In the semiconductor chip connected to, the small area circuit determined to be malfunctioning by the electrical characteristic inspection of the plurality of small area circuits is electrically separated from the surrounding normal small area circuit, A repair block having the same function as the defective circuit and a normal small-area circuit is mounted on the defective circuit, and the normal circuit of the repair block is electrically connected to the surrounding normal circuit. .
【0007】さらに、本発明による半導体チップの不良
回路補修方法は、全体の大面積回路が複数の小面積回路
に分割されていると共に、これら複数の小面積回路とそ
れぞれ周囲の小面積回路とが電気的に切り離し可能に接
続されている半導体チップの不良回路補修方法であっ
て、前記複数の小面積回路の電気的特性を検査し、この
検査により動作不良と判定された小面積回路を周囲の正
常な小面積回路から電気的に切り離し、その不良回路と
同機能で正常な小面積回路を有する補修用ブロックを前
記不良回路上に搭載し、この補修用ブロックの正常回路
と前記周囲の正常回路とを電気的に接続するものであ
る。Further, in the method for repairing a defective circuit of a semiconductor chip according to the present invention, the whole large area circuit is divided into a plurality of small area circuits, and the plurality of small area circuits and the surrounding small area circuits are respectively formed. A method of repairing a defective circuit of a semiconductor chip that is electrically detachably connected, in which electrical characteristics of the plurality of small area circuits are inspected. It is electrically separated from a normal small area circuit, and a repair block having a normal small area circuit with the same function as the defective circuit is mounted on the defective circuit, and the normal circuit of this repair block and the surrounding normal circuit. Is to electrically connect with.
【0008】[0008]
【作用】上記のように構成された本発明によれば、全体
の大面積回路が複数の小面積回路に分割されているの
で、大面積回路内に不良回路部分が生じた場合でも、そ
の不良回路部分は個々の小面積回路の何れかに存在する
ことになる。個々の小面積回路と周囲の小面積回路とは
電気的に切断可能に接続されているので、電気的特性検
査により動作不良と判定された小面積回路(不良回路)
については、周囲の正常な小面積回路(正常回路)から
電気的に切断することによって、その不良回路が周囲の
正常回路に悪影響を及ぼすことを防止する。そして、不
良回路と同等な正常回路を有する補修用ブロックを不良
回路上に搭載してその正常回路と周囲の正常回路とを導
通させることによって、不良回路が正常回路に置き換え
られる。これにより、他の正常回路を全く無駄にするこ
となく、大面積回路の全体を正常回路として作動させる
ことが可能となる。According to the present invention configured as described above, the entire large area circuit is divided into a plurality of small area circuits. Therefore, even if a defective circuit portion occurs in the large area circuit, the defective circuit portion is defective. The circuit portion will be present in any of the individual small area circuits. Since each small area circuit and the surrounding small area circuits are electrically disconnectable, a small area circuit (defective circuit) determined to be defective by the electrical characteristic inspection
With regard to (2), by electrically disconnecting from the surrounding normal small area circuit (normal circuit), the defective circuit is prevented from adversely affecting the surrounding normal circuit. Then, a repair block having a normal circuit equivalent to the defective circuit is mounted on the defective circuit, and the normal circuit and surrounding normal circuits are electrically connected to replace the defective circuit with the normal circuit. As a result, the entire large area circuit can be operated as a normal circuit without completely wasting other normal circuits.
【0009】[0009]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【0010】まず、図5に示すように、半導体ウエハ
(Si基板)1に複数個の半導体チップ2が形成されて
いる。これらの半導体チップ2がそれぞれ本発明の主題
とする大面積の半導体チップである。そして、個々の半
導体チップ2にそれぞれ形成された全体の回路は一機能
を有する大面積回路3となっているが、この大面積回路
3は機能や素子数等に応じて複数の小面積回路3A〜3
E・・・に分割されている。この例では、半導体チップ
2の上面が複数の同一大の正方形または長方形の領域に
分割されており、各領域にそれぞれ小面積回路3A〜3
E・・・形成されている。First, as shown in FIG. 5, a plurality of semiconductor chips 2 are formed on a semiconductor wafer (Si substrate) 1. Each of these semiconductor chips 2 is a large-area semiconductor chip which is the subject of the present invention. The entire circuit formed on each of the individual semiconductor chips 2 is a large area circuit 3 having one function. The large area circuit 3 has a plurality of small area circuits 3A depending on the function and the number of elements. ~ 3
It is divided into E ... In this example, the upper surface of the semiconductor chip 2 is divided into a plurality of square or rectangular regions of the same size, and the small area circuits 3A to 3 are respectively provided in the regions.
E ... Formed.
【0011】そして、図1〜図4に示すように、各々の
小面積回路3A〜3E・・・の外周近傍には複数の電極
パッド(端子)4が列設され、互いに隣接する小面積回
路3A〜3E・・・の電極パッド4の間が配線5によっ
て導通されている。なお、図5において、半導体チップ
2の外周部に位置する小面積回路の最外周の電極パッド
(端子)6は、この半導体チップ2全体としての外部接
続用となっている。As shown in FIGS. 1 to 4, a plurality of electrode pads (terminals) 4 are arranged in a row in the vicinity of the outer periphery of each of the small area circuits 3A to 3E ... The wirings 5 electrically connect the electrode pads 4 of 3A to 3E. In FIG. 5, the outermost peripheral electrode pads (terminals) 6 of the small area circuit located on the outer peripheral portion of the semiconductor chip 2 are for external connection of the semiconductor chip 2 as a whole.
【0012】小面積回路3A〜3E・・・の電極パッド
4や配線5は、ウエハ段階の回路素子形成工程で形成さ
れるものであり、半導体チップ2の回路素子の形成が完
了した段階では、隣接する小面積回路3A〜3E・・・
どうしが既に導通されている。The electrode pads 4 and the wirings 5 of the small-area circuits 3A to 3E ... Are formed in the circuit element forming process at the wafer stage, and when the circuit elements of the semiconductor chip 2 are completed, Adjacent small area circuits 3A to 3E ...
The two are already connected.
【0013】このように、半導体チップ2の全体の大面
積回路3が複数の小面積回路3A〜3E・・・に分割さ
れているので、大面積回路3内に不良回路部分が生じた
場合でも、その不良回路部分は個々の小面積回路3A〜
3E・・・の何れかに存在することになる。従って、例
えば小面積回路3Aの動作が不良である場合、この小面
積回路3Aの周囲の配線5を切断すれば、この小面積回
路3Aは周囲の小面積回路3B〜3Eから電気的に切り
離されることになる。そして、この小面積回路3Aを補
修すれば、半導体チップ2の大面積回路3が全体として
正常に使用可能となる。As described above, since the whole large area circuit 3 of the semiconductor chip 2 is divided into a plurality of small area circuits 3A to 3E ... Even if a defective circuit portion occurs in the large area circuit 3. , The defective circuit portion is an individual small area circuit 3A-
3E ... Therefore, for example, when the operation of the small area circuit 3A is defective, cutting the wiring 5 around the small area circuit 3A electrically disconnects the small area circuit 3A from the surrounding small area circuits 3B to 3E. It will be. When the small area circuit 3A is repaired, the large area circuit 3 of the semiconductor chip 2 can be normally used as a whole.
【0014】そこで次に、上述のように構成された半導
体チップ2における不良回路の補修方法を具体的に説明
する。Then, a method of repairing a defective circuit in the semiconductor chip 2 constructed as described above will be specifically described.
【0015】まず、図5の半導体チップ2内の各々の小
面積回路3A〜3E・・・を個々に、または半導体チッ
プ2内の全ての小面積回路3A〜3E・・・を一括し
て、電気的特性の検査を行う。なお、この電気的特性検
査には、小面積回路3A〜3E・・・の電極パッド4を
利用することができる。First, each of the small area circuits 3A to 3E ... In the semiconductor chip 2 of FIG. 5 is individually or all of the small area circuits 3A to 3E ... Inspect electrical characteristics. Note that the electrode pads 4 of the small area circuits 3A to 3E ... Can be used for this electrical characteristic inspection.
【0016】次に、上記検査によって、例えば小面積回
路3Aが動作不良と判定された場合、図1及び図2に示
すように、この小面積回路(以下、不良回路という)3
Aと、その周囲の正常動作の小面積回路(以下、正常回
路という)3B〜3Eとの間で、例えばレーザー溶断に
よって配線5を切断する。これによって、不良回路3A
が周囲の正常回路3B〜3Eに電気的な悪影響を及ぼす
ことを防止する。Next, when the small area circuit 3A is judged to be defective in operation by the above inspection, as shown in FIGS. 1 and 2, this small area circuit (hereinafter referred to as defective circuit) 3 is shown.
The wiring 5 is cut, for example, by laser fusing between A and the small-area circuits (hereinafter, referred to as normal circuits) 3B to 3E that are in normal operation and are in the vicinity thereof. As a result, the defective circuit 3A
Prevents the surrounding normal circuits 3B to 3E from being electrically adversely affected.
【0017】そして、不良回路3Aと同等の機能で正常
に動作する置き換えのための正常回路3A′を有する補
修用ブロック7を別に用意し、この補修用ブロック7を
不良回路3A上に例えば絶縁性接着剤8によって固着す
る。なお、この例のように、上面に正常回路3A′を有
する補修用ブロック7を用いる場合、この補修用ブロッ
ク7は、半導体チップ2を前記領域で分割切断すること
によって得ることができる。Then, a repair block 7 having a normal circuit 3A 'for replacement, which operates normally with the same function as the defective circuit 3A, is prepared separately, and the repair block 7 is provided on the defective circuit 3A with, for example, an insulating property. It is fixed by the adhesive 8. When the repair block 7 having the normal circuit 3A 'on the upper surface is used as in this example, the repair block 7 can be obtained by dividing and cutting the semiconductor chip 2 in the region.
【0018】次に、補修用ブロック7の正常回路3A′
に形成された複数の電極パッド(端子)4′と、周囲の
正常回路3B〜3Eの各電極パッド4とを、それぞれボ
ンディングワイヤ9によって接続する。Next, the normal circuit 3A 'of the repair block 7
The plurality of electrode pads (terminals) 4 ′ formed on the above and the respective electrode pads 4 of the normal circuits 3 </ b> B to 3 </ b> E in the periphery are connected by bonding wires 9.
【0019】以上のように、半導体チップ2内に存在す
る不良回路3Aのみを補修用ブロック7の正常回路3
A′に置き換えて補修することによって、他の正常回路
3B〜3E・・・を全く無駄にすることなく、半導体チ
ップ2の大面積回路3の全体を正常回路として作動させ
ることができる。As described above, only the defective circuit 3A existing in the semiconductor chip 2 is repaired by the normal circuit 3 of the repair block 7.
By replacing with A'and repairing, the whole large area circuit 3 of the semiconductor chip 2 can be operated as a normal circuit without wasting the other normal circuits 3B to 3E.
【0020】なお、半導体チップ2内の不良回路3Aを
正常回路3A′に置き換えるのは、ウエハ1から各々の
半導体チップ2を切断する前、または切断した後のいず
れでもよい。また、半導体チップ2内の全ての不良回路
について同様な補修を施すが、半導体チップ2内に不良
回路が多過ぎる場合には、これらの不良回路を補修せず
に半導体チップ2を未使用とする。そして、残った正常
回路を分割切断して前述した補修用ブロック7としてス
トックしておく。The defective circuit 3A in the semiconductor chip 2 may be replaced with the normal circuit 3A 'either before or after cutting each semiconductor chip 2 from the wafer 1. The same repair is applied to all defective circuits in the semiconductor chip 2. However, when there are too many defective circuits in the semiconductor chip 2, these defective circuits are not repaired and the semiconductor chip 2 is unused. . Then, the remaining normal circuit is divided and cut and stocked as the above-mentioned repair block 7.
【0021】次に、図3及び図4によって別の実施例に
おける不良回路の補修方法を説明する。Next, a method of repairing a defective circuit in another embodiment will be described with reference to FIGS.
【0022】この例においては、下面に正常回路3A″
を有する補修用ブロック10を用い、この補修用ブロッ
ク10の正常回路3A″と半導体チップ2の不良回路3
Aとを対向させるようにしたものである。前述と同様に
不良回路3Aと周囲の正常回路3B〜3Eとの間の配線
5を切断し、この不良回路3A上に補修用ブロック10
を載置する。そして、正常回路3A″に形成された複数
の電極パッド(端子)4″と、周囲の正常回路3B〜3
Eの各電極4とを、バンプ11を介して一括接合する。
なお、この場合も絶縁性接着剤8を補助的に使用するの
がよい。In this example, the normal circuit 3A "is provided on the lower surface.
Using the repair block 10 having the following, the normal circuit 3A ″ of this repair block 10 and the defective circuit 3 of the semiconductor chip 2 are used.
A is made to face each other. Similarly to the above, the wiring 5 between the defective circuit 3A and the surrounding normal circuits 3B to 3E is cut, and the repair block 10 is placed on the defective circuit 3A.
To place. Then, a plurality of electrode pads (terminals) 4 ″ formed on the normal circuit 3A ″ and surrounding normal circuits 3B to 3
The respective electrodes 4 of E are collectively bonded via the bumps 11.
In this case as well, it is preferable to use the insulating adhesive 8 as a supplement.
【0023】この例の場合、補修用ブロック10とし
て、正常回路3A″が不良回路3Aと対称的な回路構成
及びパッド配置のものが必要になるが、補修用ブロック
10の機械的な固定とその正常回路3A″の電気的な接
続とを同時に行うことができるので、補修作業の工程並
びに時間を大幅に削減することができる。In the case of this example, the repair block 10 needs to have a circuit configuration and a pad arrangement in which the normal circuit 3A ″ is symmetrical to the defective circuit 3A, and mechanical fixing of the repair block 10 and its arrangement are required. Since the electrical connection of the normal circuit 3A ″ can be performed at the same time, the repair work process and time can be significantly reduced.
【0024】以上、本発明の実施例に付き説明したが、
本発明は上記実施例に限定されることなく、本発明の技
術的思想に基づいて各種の有効な変更並びに応用が可能
である。例えば、実施例では複数の小面積回路をそれぞ
れ同一大の正方形または長方形の領域に形成したが、こ
れらの領域の形状及び大きさは互いに異なっていてもよ
い。The embodiments of the present invention have been described above.
The present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, in the embodiment, a plurality of small area circuits are formed in square or rectangular regions having the same size, but the shapes and sizes of these regions may be different from each other.
【0025】[0025]
【発明の効果】以上説明したように、本発明によれば、
全体の大面積回路が複数の小面積回路に分割され、これ
ら複数の小面積回路と周囲の小面積回路とが電気的に切
り離し可能に接続されているので、不良回路のみを周囲
の正常回路から電気的に切り離して補修用の正常回路に
置き換えることによって、他の正常回路を全く無駄にす
ることなく大面積回路の全体を正常回路として使用する
ことができる。従って、歩留り低下の影響を受けること
なく、多機能かつ高密度な回路を有する大面積の半導体
チップを極めて容易に製造することが可能になり、この
種の半導体チップを使用する機器の小型化を大幅に促進
することができる。As described above, according to the present invention,
The entire large-area circuit is divided into multiple small-area circuits, and these multiple small-area circuits and the surrounding small-area circuits are connected so that they can be electrically disconnected. By electrically disconnecting and replacing with a normal circuit for repair, the whole large area circuit can be used as a normal circuit without wasting other normal circuits. Therefore, it is possible to extremely easily manufacture a large-area semiconductor chip having a multifunctional and high-density circuit without being affected by a decrease in yield, and it is possible to reduce the size of a device using this kind of semiconductor chip. Can be greatly promoted.
【図1】本発明の実施例において半導体チップの不良回
路を補修用ブロックの正常回路によって補修した状態の
要部断面図である。FIG. 1 is a cross-sectional view of essential parts in a state where a defective circuit of a semiconductor chip is repaired by a normal circuit of a repair block in an embodiment of the present invention.
【図2】上記実施例における要部平面図である。FIG. 2 is a plan view of a main part of the above embodiment.
【図3】本発明の別の実施例において半導体チップの不
良回路を補修用ブロックの正常回路によって補修した状
態の要部断面図である。FIG. 3 is a cross-sectional view of essential parts in a state where a defective circuit in a semiconductor chip has been repaired by a normal circuit in a repair block in another embodiment of the present invention.
【図4】上記別の実施例における要部平面図である。FIG. 4 is a plan view of an essential part of the another embodiment.
【図5】本発明の実施例において複数の小面積回路が形
成された半導体チップ及びこの半導体チップが複数個形
成された半導体ウエハの平面図である。FIG. 5 is a plan view of a semiconductor chip having a plurality of small area circuits formed therein and a semiconductor wafer having a plurality of the semiconductor chips formed therein according to an embodiment of the present invention.
1 半導体ウエハ 2 半導体チップ 3 大面積回路 3A〜3E 小面積回路 3A 不良回路 3B〜3E 正常回路 4、6 電極パッド 5 配線 7、10 補修用ブロック 3A′、3A″正常回路 4′、4″ 電極パッド 8 絶縁性接着剤 9 ボンディングワイヤ 11 バンプ 1 Semiconductor Wafer 2 Semiconductor Chip 3 Large Area Circuit 3A to 3E Small Area Circuit 3A Defective Circuit 3B to 3E Normal Circuit 4, 6 Electrode Pad 5 Wiring 7, 10 Repair Block 3A ′, 3A ″ Normal Circuit 4 ′, 4 ″ Electrode Pad 8 Insulating adhesive 9 Bonding wire 11 Bump
Claims (9)
多数の半導体回路素子が集積された半導体チップにおい
て、 全体の大面積回路が複数の小面積回路に分割されている
と共に、これら複数の小面積回路とそれぞれ周囲の小面
積回路とが電気的に切り離し可能に接続されていること
を特徴とする半導体チップ。1. In a semiconductor chip in which a large number of semiconductor circuit elements having a large circuit area with a predetermined degree of integration are integrated, the entire large area circuit is divided into a plurality of small area circuits, and the plurality of small area circuits are divided. A semiconductor chip characterized in that an area circuit and a peripheral small area circuit are electrically detachably connected to each other.
の矩形状領域に形成されていることを特徴とする請求項
1記載の半導体チップ。2. The semiconductor chip according to claim 1, wherein the plurality of small area circuits are formed in rectangular regions of the same size.
端子が形成され、隣接する小面積回路の電極端子間が配
線によって導通されていることを特徴とする請求項1ま
たは2記載の半導体チップ。3. The semiconductor according to claim 1, wherein electrode terminals are formed in the vicinity of the outer periphery of the plurality of small area circuits, and the electrode terminals of the adjacent small area circuits are electrically connected by wiring. Chips.
分割されていると共に、これら複数の小面積回路とそれ
ぞれ周囲の小面積回路とが電気的に切り離し可能に接続
されている半導体チップであって、 前記複数の小面積回路の電気的特性検査により動作不良
と判定された小面積回路が周囲の正常な小面積回路から
電気的に切り離されていると共に、その不良回路と同機
能で正常な小面積回路を有する補修用ブロックが前記不
良回路上に搭載され、この補修用ブロックの正常回路が
前記周囲の正常回路に電気的に接続されていることを特
徴とする半導体チップ。4. A semiconductor chip in which the entire large-area circuit is divided into a plurality of small-area circuits, and the plurality of small-area circuits and their surrounding small-area circuits are electrically detachably connected to each other. The small area circuit determined to be malfunctioning by the electrical characteristic inspection of the plurality of small area circuits is electrically separated from the surrounding normal small area circuit, and has the same function as the defective circuit. A semiconductor chip, wherein a repair block having a normal small-area circuit is mounted on the defective circuit, and the normal circuit of the repair block is electrically connected to the surrounding normal circuit.
有し、その正常回路の電極端子と前記周囲の正常回路の
電極端子とがボンディングワイヤによって接続されてい
ることを特徴とする請求項4記載の半導体チップ。5. The repair block has a normal circuit on its upper surface, and the electrode terminals of the normal circuit and the electrode terminals of the surrounding normal circuit are connected by a bonding wire. The semiconductor chip described.
有し、その正常回路の電極端子と前記周囲の正常回路の
電極端子とが接合されていることを特徴とする請求項4
記載の半導体チップ。6. The repair block has a normal circuit on a lower surface thereof, and an electrode terminal of the normal circuit and an electrode terminal of the surrounding normal circuit are joined to each other.
The semiconductor chip described.
分割されていると共に、これら複数の小面積回路とそれ
ぞれ周囲の小面積回路とが電気的に切り離し可能に接続
されている半導体チップの不良回路補修方法であって、 前記複数の小面積回路の電気的特性を検査し、この検査
により動作不良と判定された小面積回路を周囲の正常な
小面積回路から電気的に切り離し、その不良回路と同機
能で正常な小面積回路を有する補修用ブロックを前記不
良回路上に搭載し、この補修用ブロックの正常回路と前
記周囲の正常回路とを電気的に接続することを特徴とす
る半導体チップの不良回路補修方法。7. A semiconductor chip in which an entire large-area circuit is divided into a plurality of small-area circuits, and the plurality of small-area circuits and their surrounding small-area circuits are electrically detachably connected to each other. A defective circuit repairing method, inspecting the electrical characteristics of the plurality of small area circuits, electrically disconnecting the small area circuit determined to be malfunctioning by this inspection from the surrounding normal small area circuit, A repair block having the same function as the defective circuit and a normal small area circuit is mounted on the defective circuit, and the normal circuit of the repair block and the surrounding normal circuit are electrically connected. Method for repairing defective circuit of semiconductor chip.
を前記不良回路上に固着し、その正常回路の電極端子と
前記周囲の正常回路の電極端子とをボンディングワイヤ
によって接続することを特徴とする請求項7記載の半導
体チップの不良回路補修方法。8. A repair block having a normal circuit on its upper surface is fixed onto the defective circuit, and the electrode terminals of the normal circuit and the electrode terminals of the surrounding normal circuit are connected by bonding wires. A method for repairing a defective circuit of a semiconductor chip according to claim 7.
を前記不良回路上に載置し、その正常回路の電極端子と
前記周囲の正常回路の電極端子とを接合することを特徴
とする請求項7記載の半導体チップの不良回路補修方
法。9. A repair block having a normal circuit on the lower surface is placed on the defective circuit, and the electrode terminals of the normal circuit and the electrode terminals of the surrounding normal circuit are joined together. 7. A method for repairing a defective circuit of a semiconductor chip according to 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26549192A JPH0689926A (en) | 1992-09-08 | 1992-09-08 | Semiconductor chip and method for repairing its defective circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26549192A JPH0689926A (en) | 1992-09-08 | 1992-09-08 | Semiconductor chip and method for repairing its defective circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0689926A true JPH0689926A (en) | 1994-03-29 |
Family
ID=17417925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26549192A Withdrawn JPH0689926A (en) | 1992-09-08 | 1992-09-08 | Semiconductor chip and method for repairing its defective circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0689926A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7148127B2 (en) * | 2001-06-12 | 2006-12-12 | Sony Corporation | Device mounting substrate and method of repairing defective device |
-
1992
- 1992-09-08 JP JP26549192A patent/JPH0689926A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7148127B2 (en) * | 2001-06-12 | 2006-12-12 | Sony Corporation | Device mounting substrate and method of repairing defective device |
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