JPH0688861A - Self-diagnosis and testing method of signal processing substrate - Google Patents

Abstract

PURPOSE:To enable a signal processor to quickly and easily specify a faulty location on a signal processing substrate by adding a simple test circuit to the processor so that the processor can compare signal data with test pattern data. CONSTITUTION:When the mode of the substrate is switched from a picture to a test mode, the select signal SEL of a register 10 changes from, for example, L to H and is inputted to a multiplexer 16. Then the data of the multiplexer 16 are changed from picture data to test pattern data prepared by a CPU 12 and selected test pattern data are inputted to the logic circuit and memory of a picture processing substrate 18 through a CPU interface(I/F) 14. In addition, the data held by the registers of a plurality of gate arrays are returned to the CPU 12 as output response data through the I/F 14. Therefore, the CPU 12 judges whether or not the holding (response) data of each register of the substrate 18 are proper by comparing the data with the test pattern data and, by reading out abnormality of the data, specifies an abnormal location, namely, a defective gate array.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis test method for a signal processing board, and particularly to a printing apparatus such as a printing plate making apparatus, an image exposing apparatus and an image recording apparatus of an image forming apparatus such as a copying machine and a printer. The present invention relates to a self-diagnosis test method for a signal processing board such as an image processing board.

[0002]

2. Description of the Related Art Conventionally, in a printing apparatus such as a printing plate making apparatus, a copying apparatus, an image forming apparatus such as a printer, an image reading device for reading a document image placed on a platen, a read image converted into an electrical signal. An image processing device that processes images and character information created by a computer or word processor and image recording that exposes the image processed image information to a recording material such as a photosensitive material and records it as a visible image or a latent image is used. There is.

In an image processing apparatus such as an image exposure apparatus and an image recording apparatus of such an image forming apparatus, a large number of control circuits, a large number of logic circuits and a large number of memories are used to process a large number of pixel data. ing. These numerous control circuits, logic circuits, and memories are integrated into ICs or LSIs (CPU, TTL, PLD) on a plurality of electric circuit boards having a predetermined pattern.
(PAL), LCA, gate array, standard cell, embedded array, ROM, RAM). Further, by configuring these electric circuits for image processing by using logic-configurable elements such as gate arrays, standard cells, and embedded arrays, the entire image processing circuit can be configured with a small number of image processing boards.

[0004]

When a failure occurs in these printing plate making apparatus and copying apparatus, a maintenance serviceman repeats analysis with a measuring instrument such as an oscilloscope or a logic analyzer to identify the failed board. Was. For this reason, there has been a problem that the work for specifying is complicated and it takes time to specify. Further, in such a board manufacturing process, there is a problem that it is necessary to develop an expensive function confirmation tester for each board.

Further, when an image processing electric circuit is constructed by using a gate array on an image processing substrate,
For gate array manufacturers, DC characteristic tests such as IIH, IOH, IIL, and IOL, and functional tests (function tests) for gate array single products, especially memory embedded logic circuit tests and scan path embedded logic circuits Although many tests have been performed such as the test of, it is difficult to perform these tests on the gate array mounted on the substrate by using the same test pattern. That is, it takes an enormous amount of time to perform all the test patterns used when the gate array was developed on the substrate and confirm all the functions of the gate array on the substrate. Since it has to be added to various boards, the board must be made larger, which requires more time, resulting in an increase in the board scale and a longer test time. There was a problem that it was difficult.

An object of the present invention is to solve the above problems of the prior art, and to perform a simple test on a signal processing device such as an image processing device using a signal processing substrate such as an image processing substrate using a plurality of logic circuits and memories. Another object of the present invention is to provide a self-diagnosis test method for a signal processing board, which can quickly and easily identify a failure location of the signal processing board by using this test circuit by adding a circuit.

[0007]

In order to achieve the above object, the present invention provides a CPU through a CPU interface.
Of a signal processing board having a plurality of logic circuits each connected to the logic circuits and arranged in a predetermined pattern, wirings connecting the logic circuits in a predetermined pattern, and a memory connected to the wirings between the logic circuits. When performing a self-diagnosis test, in the self-diagnosis test mode, the selector switches from signal data to test data having a predetermined test pattern generated by the CPU in response to input of a select signal from the CPU interface, and this input test pattern is changed. The signal is input to each of the logic circuit and the memory of the signal processing board through the CPU interface, and the output response pattern is returned to the CPU through the CPU interface again.
A self-diagnosis test method for a signal processing board, wherein U diagnoses a defective portion by comparing the input test pattern and the output response pattern. Here, it is preferable that the logic circuit is configured as an element such as a gate array for reducing the mounting size. The signal processing board is preferably an image processing board.

[0008]

In the self-diagnosis test method for the signal processing board of the present invention, by using the added test circuit, the signal data such as the actual image data and the test pattern data created by the CPU are switched, When the CPU executes the test program, these test data are input to a large number of logic circuits and memories of a signal processing board such as an image processing board on which the output response data is obtained, and the input test data and the output response data are obtained. If there is an abnormality by comparing with, the CPU itself identifies the failure location of the signal processing board such as the image processing board.

Therefore, according to the signal processing board self-diagnosis test method of the present invention, when a failure occurs when the signal processing board such as the image processing board is mounted on the signal processing apparatus such as the image processing apparatus in the market. Also, the failure location of the signal processing board such as the image processing board can be quickly identified only by causing the CPU itself to execute the test program.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal processing board self-diagnosis test method according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an image processing circuit which is a signal processing circuit for a self-diagnosis test for carrying out the self-diagnosis test method for a signal processing board according to the present invention. In the following description, an image processing board is representatively used as a signal processing board, but the present invention is not limited to this. In the figure, 10 is a register, 12 is a CPU (central processing unit), 14 is a CPU interface (CPU
I / F), 16 is a multiplexer (MPX), and 18 is an image processing board on which the self-diagnosis test method of the present invention is performed. The image processing circuit shown in FIG. 1 carries out a self-diagnosis test method according to the present invention, and a register 10 for holding test data and a test clock generated by a CPU and an MPX1 for switching between real image data and test data.
6 and 6 are added.

The test pattern data and test clock used in the self-diagnosis test method of the present invention are CPU 1
2 may be programmed in a memory (for example, the memory 38 shown in FIG. 3) such as a ROM or a RAM which is connected to the CPU 12 in advance. The software may include, for example, means for generating random numbers to create a test pattern. The register 10 is the CPU 1
It holds the 8-bit or 12-bit test pattern data created in 2 and is output serially or in parallel according to the test clock. The multiplexer (MPX) 16 switches between 8-bit or 12-bit actual data (image data) operated by an actual clock (image clock) and 8- or 12-bit test pattern data operated by a test clock. . Here, a selector may be used instead of the multiplexer 16.

For example, the register 10 and the multiplexer 16 can be configured as shown in FIG. The register 10 includes a portion 10a for holding test data and a portion 10b for outputting a select signal SEL. The select signal output portion 10b includes a decoder 20 and a D latch 22.
And outputs the select signal SEL. The multiplexer 16 includes AND circuits 24 and 26 and an OR circuit 28. One of the input terminals of the AND circuit 24 receives real image data and the other receives an inverted signal of the select signal SEL. , The other AND circuit 26
The test data is input to one of the input terminals of and the select signal SEL is input to the other. The outputs of both AND circuits 24 and 26 are input to both input terminals of the OR circuit 28.

Therefore, for example, when the select signal SEL output from the latch 22 of the select signal output section 10 of the register 10 is "L", the AND circuit 26 to which the "L" signal is input is inactive. , Test data is not output from the AND circuit 26, but the select signal SE
Since the inverted output of L becomes "H", the AND circuit 24 becomes active and the actual image data is output from the AND circuit 24. As a result, only the actual image data is input to the OR circuit 28, and only the actual image data is output from the OR circuit 28 and input to the image processing board 18. Therefore, when the select signal SEL is "L", the actual image data is selected from both data. On the other hand, the select signal S
When EL is "H", the AND circuit 26 becomes active contrary to the above case, so that the OR circuit 28 outputs the test data and only the test data is selected from the both data. .

The image processing board 18 is, for example, as shown in FIG. 3, gate arrays 30a, 30b, 30c, 30d and 30e in which logic circuits exhibiting a plurality of predetermined functions are formed.
And a plurality of memories 34a, 34b, 34c, 34d and wirings between them are arranged in a predetermined pattern. Each gate array 30a, 30b, 30c, 30
Registers 32a, 32b, 32c and 32 are provided in d and 30e.
d, 32e are formed and these registers 30a-30
e is all via the CPU interface 14,
It is connected to the CPU 12 incorporated in the CPU board 36. Here, the CPU board 36 is provided with a memory 38 for storing an operation program of the CPU 12, data necessary for executing the program, execution result data, and the like.
It is connected to U12.

The image processing substrate 18 on which the self-diagnosis test method of the present invention is implemented is not limited to the one in which a logic circuit (logic) having a predetermined function is constituted by the gate arrays 30a to 30e as shown in FIG. TTL, PLD (PA
L, GAL), LCA may be used to form a logic circuit, or a logic circuit or a logic circuit including a memory or the like may be formed using a logic-configurable element such as a standard cell or an embedded array. Good.

The self-diagnosis test method of the present invention is performed by the image processing circuit having the above-mentioned configuration. In the image processing circuit shown in FIG. 1, first, for example, when the image mode is switched to the test mode after mounting and at the time of use or failure, it is input from the CPU 12 to the multiplexer 16 via the register 10. At this time, the select signal SEL changes from “L” to “H”, for example, and when this select signal SEL is input to the multiplexer 16, the multiplexer 16 determines the CPU 1 from the actual image data.
The test pattern data is switched to the test pattern data created by the CPU operated by the test clock created in 2. The test pattern data selected by the multiplexer 16 in this way is input to the image processing board 18, causes the plurality of gate arrays 30a to 30e to perform a predetermined function, and the data held in the registers 32a to 32e therein is the CPU interface 14. Is returned to the CPU 12 as output response data via.

Therefore, the CPU 12 controls the image processing board 18
Registers 32a-3 of the gate arrays 30a-30e
It is determined by comparing whether or not the held data (response data) of 2e is correct response data based on the test pattern data created first, and the abnormality of the data is read, and the abnormal portion, that is, which gate array is the defective gate array. To identify The abnormal part and the failure part specified by the CPU 12 are directly displayed on a display device (display device) not shown, or once the same CP is displayed.
After being incorporated in the U board 36 and stored in the memory connected to the CPU 12, it is read and displayed as necessary, or printed as a hard copy. In this way, according to the method of the present invention, it is possible to easily and quickly identify a failure location or an abnormal location of the image processing board at the time of inspection after mounting or at the time of failure during use.

In the image processing circuit for implementing the self-diagnosis test method of the present invention, for example, in the image processing circuit shown in FIG. 1, the register 10 and the multiplexer 16, and further, a part or all of the CPU interface 14 is an image processing board. The gate array may be formed on the same substrate as 18 or on another substrate. Of course, similar to other logic circuits, other PLD (PA
L, GAL) or LCA, or may include logically configurable elements such as standard cells and embedded arrays including the CPU 12 and CPU interface 14.

Next, an example of a concrete circuit configuration in the CPU interface and the gate array of the image processing board on which the self-diagnosis test is carried out by the method of the present invention is shown in FIGS. A flowchart is shown in FIGS. 6 and 7, and a time chart thereof is shown in FIG.

FIG. 4 shows an example of the circuit configuration of the CPU interface 14, and FIG. 5 shows an example of the circuit configuration of the register 10 and the multiplexer (selector) 16 in the selected gate array. A CPU extending from the CPU 12 in the interface 14 shown in FIG.
The address bus 40 is input to a buffer (multi-input 3-state gate) 50 and a PAL 51 (address decoder), the output of which is input to a logic circuit (function: decoder) 52 configured by GAL, and from this circuit 52, chip select is performed. The (CS) signal is output, and a predetermined chip (gate array 80) is selected and input to this chip. On the other hand, the CPU data bus (8 bits) 41 to which the test pattern data (8 bits) generated by the CPU 12 is input is connected to the CPU data bus (8 bits) via bus transceivers (multi-input bidirectional 3-state gates) 53 and 54. ) 42, which is input to the gate array 80 selected by the CPU address bus. On the other hand, reference numeral 55 is a buffer (multi-input 3-state gate), and 56 is an inverter.

The chip select signal CS from the CPU interface 14 is input to the NOR circuit 57, and its output is input to the clock terminal of the parallel register 58. The input of this register 58 is the CPU data bus 42.
8-bit test data is input from the output, and its output is input to the demultiplexer (decoder) 59, and B, C,
The D command signal and others are output. On the other hand, the output CA0 of the buffer 50 and the buffer 5 of the CPU interface 14
The output nWR of 5 becomes the remaining input of the 3-input 1-output NOR circuit 57. Further, this output CA0 is inverted by the inverter 60 and becomes one input of the 2-input 1-output NOR circuit 61, and the above-mentioned chip select signal CS branches to NO.
It becomes the other input of the R circuit 61. The output of the NOR circuit 61 and the output nWR described above serve as an enable input of the demultiplexer (decoder) 59. The signal nRS
T indicates a clear signal.

Next, the register 10 (62, 6) shown in FIG.
3, 64) and multiplexer 16 (66, 67, 6)
8 and 69) are configured in the gate array 80,
The register 10 includes a B register 62 in which a B command signal is input to its clock terminal, a C register 63 in which a C command signal is input to its clock terminal, and a D register 64 in which a D command signal is input to its clock terminal. And the B register 62 and the C register 63 have the test data holding unit 1
0a, and the D register 64 has the select signal output unit 1
Configure 0b. On the other hand, the multiplexer 16 is composed of actual image data buffers 66 and 67 and test data buffers 68 and 69.
The control terminals of 6 and 67 are connected to the bit of the D register 64.
The two outputs (select signal SEL) are directly input to the control terminals of the buffers 68 and 69 after the bit2 outputs are inverted by the inverter 65, and these buffers 66, 67, 68 and 69 are input to the control terminals. It is configured to become active when "L" is input.

Here, the B, C and D registers 62, 63,
8-bit test data is input to the CPU 64 from the CPU data bus 42, and is input to the buffers 68 and 69 to be described later from the B and C registers 62 and 63 by the data buses 43 and 44, respectively. On the other hand, the D register 64 outputs bit0 output, bit1 output, bit2 output, and bit3 output, and the bit0 output is buffer 68.
As test clock 1, bit 1 output is buffer 6
8 as a line cycle signal (LSYNC), and b
The output of it2 is the buffer 6 as the select signal SEL.
6 and 67 directly, and buffers 68 and 69 to inverter 6
5 and the bit3 output is input to the buffer 69 as the test clock 2.

The 12-bit image data is input from the image bus 45 to the buffers 66 and 67, and the real clock 4
6, 47 and buffers 66, 67. The 12-bit image data is output from the buffers 66, 67, 68, 69 to the image bus 48. In FIG. 5, reference numerals 70 and 71 denote exclusive OR circuits, 7
2, 73, 74, and 75 are inverters, and 76 is a buffer.

The CPU interface 14, the register 10 and the multiplexer 16 shown in FIGS. 4 and 5 thus configured carry out a self-diagnosis test according to the flow charts shown in FIGS. 6 and 7 and the time chart shown in FIG.

First, when a negative pulse is output to the (a) chip select signal CS of the CPU interface 14 and the test mode is designated, the (b) D register designation signal of the negative pulse is given to the D register 64 at the same timing. Is input and written in the D register 64 so that the outputs of (g), (h), (d), and (i) bits 0 to 3 are set to "1" at the rising timing of this negative pulse. At the next test clock timing, the (e) B register designation signal (negative pulse) is input to the B register 62, and 8-bit test data input from the CPU data bus 42 is written at the rising timing thereof. Similarly, at the next test clock timing, (f) is set in the C register 63.
The C register designation signal (negative pulse) is input, and 8-bit test data input from the CPU data bus 42 is written at the rising timing thereof.

Next, all of the (g) bit0 output, (h) bit1 output, and (i) bit3 output of the D register 64 are set to "1", and then to "1", "0", and "1", respectively. Repeat 10 times. When the number of repetitions (the number of loops) reaches 10, similarly, (g) bit0 output, (h) bit1 output, (i) bi of the D register 64 are output.
The t3 output is set to "0", "1", "0", and subsequently "1", "1", "1" is repeated 50 times.
When the number of repetitions reaches 50, it is judged whether or not the test is finished. If not finished, B register 6
Return to the place where 8-bit test data is written in 2, and repeat the test. To end the test, the (d) bit2 output of the D register 64 is set to "0". In this way, the self-diagnosis test can be performed.

The self-diagnosis test method of the present invention can be applied not only to the image processing board, but also to an electric circuit and a signal processing board for which a failure diagnosis is required at the time of mounting or failure inspection.

[0030]

As described in detail above, according to the present invention,
The fault location of the signal processing board such as the image processing circuit board can be quickly identified only by adding a simple test circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an image processing circuit for implementing a self-diagnosis test method for a signal processing board according to the present invention.

FIG. 2 is a detailed configuration diagram of a part of the image processing circuit shown in FIG.

FIG. 3 is a detailed configuration diagram of another portion of the image processing circuit shown in FIG.

FIG. 4 is a specific configuration diagram of a part of the image processing circuit shown in FIG.

5 is a concrete configuration diagram of another portion of the image processing circuit shown in FIG. 1. FIG.

FIG. 6 is an example of a flowchart showing a part of a flow of a self-diagnosis test method for a signal processing board according to the present invention.

FIG. 7 is an example of a flowchart showing another part of the flow of the self-diagnosis test method for a signal processing board according to the present invention.

FIG. 8 is an example of a time chart of each part of the circuits shown in FIGS. 4 and 5.

[Explanation of symbols]

10 register 12 CPU 14 CPU interface 16 multiplexer (selector) 18 image processing circuit board 20 decoder 22 latch circuit 24, 26 AND circuit 28 OR circuit 30a, 30b, 30c, 30d, 30e gate array 32a, 32b, 32c, 32d, 32e Registers 34a, 34b, 34c, 34d Memory 36 CPU board 38 Memory

Claims (3)

[Claims] 1. A plurality of logic circuits each connected to a CPU via a CPU interface and arranged in a predetermined pattern, wirings connecting these logic circuits in a predetermined pattern, and wirings between the logic circuits. When performing a self-diagnosis test of a signal processing board having a memory connected thereto, in a self-diagnosis test mode, a selector outputs a predetermined test pattern generated by the CPU from signal data by inputting a select signal from the CPU interface. The test data is switched to the input test pattern, the input test pattern is input to each of the logic circuit and the memory of the signal processing board through the CPU interface, and the output response pattern is returned to the CPU through the CPU interface again. Let the CP
A self-diagnosis test method for a signal processing board, wherein U diagnoses a defective portion by comparing the input test pattern and the output response pattern. 2. The self-diagnosis test method for a signal processing board according to claim 1, wherein the logic circuit is configured as a gate array. 3. The self-diagnosis test method for a signal processing board according to claim 1, wherein the signal processing board is an image signal processing board.