JPH0687356B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention is provided with a booster circuit inside, and uses this boosted voltage to control the output of a high voltage supplied from the outside. Semiconductor integrated circuit.

(Prior Art) A non-volatile semiconductor memory device, particularly an EPROM using a double-gate type non-volatile memory element having a floating gate structure as a memory cell, is capable of rewriting data. It is used in various systems including the beginning. The double-gate type non-volatile memory device has two gate electrodes, a floating gate and a control gate, as is well known. If electrons are injected into the floating gate, the threshold voltage of the floating gate is increased, so that the memory element does not conduct even if a high level voltage, for example, 5 V is applied to the control gate. On the other hand, if electrons are not injected into the floating gate and it is in a neutral state, the threshold voltage remains at its original low value, and if a high level voltage is applied to the control gate, the memory element becomes conductive. In this way, data is stored by associating the conductive state and the non-conductive state of the memory element when a high level voltage is applied to the control gate with “1” and “0” of the data. The floating gate and the drain are applied with a voltage sufficiently higher than the normal power supply voltage (5V), for example, a voltage of 12.5V to 21V. By applying such a high voltage, impact ionization occurs in the channel region in the vicinity of the drain, and electrons generated from the impact ionization are injected into the floating gate. The electrons once injected into the floating gate remain in the floating gate unless the erase operation is performed.
The stored data will be retained in a non-volatile manner.

FIG. 11 is a circuit diagram showing a schematic configuration of a general EPROM using the above nonvolatile memory element as a memory cell. In the figure, WL1 to WLm are row lines to which the decode output from the row decoder 131 is supplied, and COL1 to COLn are column select lines to which the decode output from the column decoder 132 is supplied. The gates of the n column selection transistors C1 to Cn are connected to the lines COL1 to COLn, and these column selection transistors C1 to Cn are driven by the signals of the corresponding column selection lines COL1 to COLn. One end of each of the column selection transistors C1 to Cn is commonly connected to the node 133, and the other end thereof is connected to each of n column lines BL1 to BLn provided so as to intersect with the row lines WL1 to WLm. Has been done. Further, memory cells M11 to Mmn composed of double gate type MOS transistors having a floating gate and a control gate structure are provided at positions where the row lines WL1 to WLm intersect the column lines BL1 to BLn. . These memory cells M11
Each control gate of ~ Mmn is connected to the corresponding row line WL1 ~ WLm, each drain is connected to the corresponding column line BL1 ~ BLn, all sources are the application point of a predetermined voltage, for example 0V ground voltage.
Connected to VS. The source of the MOS transistor 134 is connected to the node 133. The drain of the transistor 134 is connected to the external program voltage VP, and the gate is connected to the output node of the data writing circuit 135. The data write circuit 135 outputs write data DIN set to the VS voltage or the high voltage according to the data “1” and “0” to be programmed. A sense amplifier circuit 136 is connected to the node 133, and the data corresponding to the potential of the node 133 is detected by the sense amplifier circuit 136 when reading data.

In the EPROM configured as described above, when data “0” is written in one memory cell, for example, M11, the signal DIN output from the data write circuit 135 is set to a high voltage, and the column decoder 132 outputs the decoded signal to select the column. Line COL1 is pulled high. The high voltage on DIN turns on the transistor 134, and the high voltage on the column selection line COL1 turns on the column selection transistor C1 to output the external program voltage VP to the column line BL1. At this time, the decode output of the row decoder 131 causes the row line WL1 to have a high voltage, and the high voltage is applied to both the control gate and the drain of the selected memory cell M11. As a result, electrons due to the impact ionization as described above are generated in the memory cell M11.
Is injected into the floating gate of and data "0" is written. On the other hand, when writing data “1” to the memory cell M11, the DIN output from the data write circuit 135 is 0V.
To be VS. At this time, the transistor 134 is turned off, so that the external program voltage VP is not output to the column line BL1. Therefore, the floating gate of the selected memory cell M11 maintains the neutral state.

By the way, recently, in order to achieve high integration, the nonvolatile memory element as described above has been miniaturized, and with this miniaturization,
The external program voltage VP is also low. Therefore, it is common to write data in the avalanche region, which has a high program efficiency, in consideration of shortening the program time and operating margin.

FIG. 12 shows the memory cell M11 of the EPROM of FIG. 11 when a high voltage is applied to the gates of the MOS transistor 134 and the MOS transistor C and a high voltage for programming is applied to the control gate of the memory cell M11. It is a figure which shows a write characteristic (drain voltage VD-drain current ID characteristic). A curve a in FIG. 12 shows the drain current dependence of the drain voltage of the memory cell M11, and a straight line d shows the load characteristic of the load circuit including the MOS transistor 134 and the MOS transistor C1 under the above conditions. The drain voltage and the drain current are applied at a point A where the curve a and the straight line d intersect. By the way, it is known that the channel length of the memory cell M11 always varies within a certain range in the manufacturing process. The drain current dependency of the drain voltage of the memory cell M11 when the channel length becomes longer than the specified value becomes a curve b, and when the channel length becomes shorter than the specified value, it becomes a curve c. The operating point at the time of writing when the channel length becomes long is the point B where the curve b and the straight line d intersect. Therefore, in this case, writing in the avalanche region becomes difficult and the write margin is reduced. On the other hand, the operating point at the time of writing when the channel length becomes short is the point C where the curve c and the straight line d intersect.
Becomes In this case, writing is sufficiently performed in the avalanche region, but the drain current increases significantly. Therefore, in order to perform stable writing even when the channel lengths of the memory cells vary and to make the drain current value almost constant, it is necessary to make the operating points at the time of writing almost the same. Therefore, for this purpose, the slope of the load characteristic may be reduced, for example, the straight line e. To this end, it has become common to apply a high voltage higher than the external program voltage VP to the gates of the MOS transistor 134 and the MOS transistor C to compensate for the voltage drop due to the threshold voltage in each transistor. There is.

By the way, a conventional EPROM generally has a single N-channel configuration using an N-channel MOS process, but in a microcomputer typified by a handheld computer, CMOS conversion is performed as power consumption is reduced. Has been. FIG. 13 shows a conventional case using the boosted voltage as described above.
FIG. 12 is a circuit diagram showing a configuration related to one column selection line COLi of the column decoder 132 (shown in FIG. 11) in an EPROM having a CMOS configuration. For example, with the normal read voltage VC set to 5V
Two in the CMOS NAND circuit 146, which includes the P-channel MOS transistor 141 and the N-channel MOS transistors 142 and 143 inserted between the ground voltage VS of 0V and the P-channel MOS transistor 145 inserted between the VC and the node 144. The signals from the column pre-decoders 147 and 148 are supplied. CMOS above
The output node 144 of the NAND circuit 146 is connected to one end of an N-channel MOS transistor 149 whose gate is constantly applied with the voltage VC, and the other end of the MOS transistor 149 is a P-channel MOS transistor 150 and an N-channel MOS transistor 151. Is connected to the input node of the CMOS inverter 152. The output node of the CMOS inverter 152 is connected to the corresponding column selection line COLi. The source of the N-channel MOS transistor 151 in the inverter 152 is connected to the ground voltage VS. Further, the input node of the inverter 152 is connected to the column selection line COLi to which the gate corresponds.
The drain of the P-channel MOS transistor 153 connected to is connected.

Reference numeral 154 is a booster circuit that boosts the external program voltage VP and outputs a voltage HV higher than VP. This booster circuit 154
The high voltage HV obtained by
Is supplied to. The voltage switching circuit 155 switches and outputs the high voltage HV when programming data and the voltage VC when reading data. The output voltage from the voltage switching circuit 155 is supplied to the sources of the P-channel MOS transistors 150 and 153, respectively.

FIG. 14 shows a column predecoder 14 used in the above column decoder.
FIG. 7 is a circuit diagram showing a specific configuration of 7 or 148. This column predecoder is for an input address of 2 bits, and these 2-bit addresses A1 and A2 are supplied to a CMOS NAND circuit 161 composed of P-channel and N-channel MOS transistors, and further this CMOS NAND circuit. The output of 161 is supplied to the CMOS inverter 162. The output of the inverter 162 is used as the output of the column predecoder to output the thirteenth signal.
It is supplied to the CMOS NAND circuit 146 in the figure.

In such a circuit, the high voltage HV is output from the voltage switching circuit 155 during data programming. Now, according to the input address, the CMOS NAND circuit 146 of FIG.
When the output of is set to "0" level (0V), the input node of the inverter 152 is also set to "0" level accordingly. At this time, the P-channel MOS transistor 150 in the inverter 152 is
Are turned on and the N-channel MOS transistor 151 is turned off. As a result, the high voltage HV from the voltage switching circuit 155 is output to the column selection line COLi. At this time, the high voltage HV is supplied to the gate of the P-channel MOS transistor 153, so that the transistor 153 remains non-conductive.

When the output of the CMOS NAND circuit 146 is set to the "1" level (5V) during data programming, the input node of the inverter 152 becomes approximately 5V through the N-channel MOS transistor 149, and the P-channel MOS transistor in the inverter 152 becomes. 15
0 is non-conductive, the N-channel MOS transistor 151 is conductive, and the voltage VS of 0 V is output to the column selection line COLi. At this time, the gate of the P-channel MOS transistor 153 also becomes the ground voltage, the transistor 153 becomes conductive, and the high voltage HV is supplied to the input node of the inverter 152.
As a result, the P-channel MOS transistor 150 in the inverter 152 becomes sufficiently non-conductive, and the outflow of current from the high voltage HV to the column selection line COLi is prevented. At this time, one end of the N-channel MOS transistor 149 is set to 5V by the output of the CMOS NAND circuit 146, and its gate is always set to 5V, so that the transistor 149 becomes non-conductive.
Therefore, there is no possibility that the high voltage HV will be applied to the CMOS NAND circuit 146 via the transistor 149.

When reading data, the voltage V
Since C is output, at this time, the voltage VC of 5V which is the output of the CMOS NAND circuit 146 or the ground voltage VS of 0V is output to the corresponding column selection COLi.

By the way, since the conventional EPROM provided with the column decoder having the configuration as shown in FIG. 13 uses a high voltage when programming data, there is a problem that the latch-up phenomenon is easily induced by the CMOS configuration. . This latch-up phenomenon means, for example, a parasitic NPN transistor formed by an N-channel MOS transistor formed in a P-type substrate and a parasitic PNP transistor formed by a P-channel MOS transistor formed in an N-well region constitute a parasitic thyristor. This is a phenomenon in which this parasitic thyristor is turned on by being triggered by a high voltage, and a DC through current is generated between the power supplies. In order to prevent the occurrence of this latch-up phenomenon, a high voltage system circuit, for example, the booster circuit in the circuit shown in FIG.
154, voltage switching circuit 155, P-channel MOS transistor 15
3, P channel and N that constitute the CMOS inverter 152, etc.
It is necessary to adopt a high breakdown voltage structure for each channel MOS transistor. In the case of a P-channel transistor, for example, this high breakdown voltage structure transistor is constructed as shown in the sectional view of FIG. That is, a source 172 and a drain 173 made of a P-type high concentration region are provided in the N well region 171, and a gate 175 is provided on a channel 174 between the regions 172 and 173. In order to increase the breakdown voltage, a low concentration P-type region 176 is provided on the side of the drain 173 in contact with the channel 174. Such a structure is known as a so-called LDD structure. However, this LDD structure transistor needs to have a larger element area than a normal one. Further, when a P-channel MOS transistor is formed using a P-type substrate, this P-channel MOS transistor is formed in the N well region, and at that time, the N well region is set to the same potential as its source. There is a need.
Therefore, the N-well region of the P-channel MOS transistor having a high breakdown voltage does not need to have a high breakdown voltage.
It must be provided independently of the N well region of the S transistor. In addition, in order to suppress the generation of leak current as much as possible, the N well region of the P channel MOS transistor to which a high voltage is applied must be separated from other internal elements by a sufficient distance.

(Problems to be Solved by the Invention) As described above, in the related art, by adopting a high breakdown voltage structure for both P-channel and N-channel MOS transistors in order to prevent the occurrence of latch-up, the entire area becomes large. However, there is a drawback that the chip size becomes large.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of preventing the occurrence of latch-up and preventing the chip size from increasing. .

[Configuration of the Invention] (Means and Actions for Solving Problems) A semiconductor integrated circuit of the present invention is a CM that operates at a first voltage and sets its output node to a first voltage or a reference voltage.
An OS circuit, an output circuit for controlling output of a second voltage higher than the first voltage to a signal output node, and a first gate connected between the output node of the CMOS circuit and the signal output node. A separation MOS transistor to which a control signal is applied, the CMOS circuit having a high conduction resistance of the separation MOS transistor after a lapse of a period of outputting the second voltage to the signal output node. Is set to a reference voltage, and then the conduction resistance of the MOS transistor for separation is lowered by the first control signal.

By setting the output node of the CMOS circuit to the reference voltage while keeping the conduction resistance of the isolation MOS transistor high as described above, the second voltage output to the signal output node becomes the isolation MOS transistor. And is discharged through the N-channel MOS transistor in the CMOS circuit. At this time, no voltage higher than the absolute value of the threshold voltage of the MOS transistor for isolation is applied to the CMOS circuit side.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration related to one column selection line COLi of a column decoder 132 (shown in FIG. 11) when the present invention is applied to the EPROM shown in FIG. For example, two enhancement-type (hereinafter referred to as E-type) P-channel MOS transistors 2 and 3 are inserted in parallel between the node 1 and the normal read voltage VC set to 5V, and the node 1 Two E-type N-channel MOS transistors 4 and 5 are inserted in series between the ground voltage VS and the ground voltage VS.
An input CMOS NAND circuit 6 is configured. The output signals from the column predecoder 7 are supplied to the gates of the transistors 2 and 4 in the CMOS NAND circuit 6, and the output signals from the column predecoder 8 are supplied to the gates of the transistors 3 and 5. It The output node 1 of the CMOS NAND circuit 6 is connected to the input node of a CMOS inverter 11 including a P-channel MOS transistor 9 and an N-channel MOS transistor 10. The output node 12 of the inverter 11 is a depletion type (hereinafter,
It is connected to one end of an N-channel MOS transistor 13 (referred to as D type), and the other end of this transistor 13 is connected to the corresponding column selection line COLi. The control signal S3 is basically a ground voltage (“0”) when programming data.
Level) and voltage VC (“1” when reading data)
Level) signal.

Reference numeral 14 is an output circuit for outputting a high voltage to the column selection line COLi, and a voltage HV1 lower than the external program voltage VP by the threshold voltage of the E-type N-channel MOS transistor is applied to the node 15 at the node 16, for example. Is, for example, a voltage HV2 higher than the voltage VP by a threshold voltage of one E-type N-channel MOS transistor, and at the node 17, for example, a voltage higher than the voltage VP by a threshold voltage of two E-type N-channel MOS transistors. HV3 is applied respectively. High voltage HV2 and HV3 above
Are output from the booster circuit described later. Between the nodes 16 and 18 is a D-type N channel MOS transistor 1
9 is inserted. The gate of the transistor 19 is connected to the column selection line COLi. Further, an E-type N-channel MOS transistor 20 and a D-type N-channel MOS transistor 21 are inserted in series between the node 18 and the column selection line COLi, and the gate of the transistor 20 has the high voltage.
It is connected to the node 17 of HV3, and the gate of the transistor 21 is connected to the column selection line COLi. Furthermore the above node
An E-type N-channel MOS transistor 22 is provided between 18 and 15.
Is inserted, and the gate of this transistor 22 is connected to the node 15.

FIG. 2 is a circuit diagram showing a specific configuration of the column predecoder 7 in the circuit of the above embodiment. In FIG. 2, the voltage VC
Between the node 31 and the node 31, three E-type P-channel MOS transistors 32, 33, 34 are inserted in parallel, and between the node 31 and the voltage VS, three E-type N-channel MOS transistors. 35, 36, 37 are inserted in series. These transistors form a 3-input CMOS NAND circuit 38, and the control signal S2 is applied to the gates of the transistors 32 and 35,
Address A1 is applied to the gates of transistors 33 and 36, and address A2 is applied to the gates of transistors 34 and 37.
Is applied. The output of the NAND circuit 38 is the voltages VC and VS.
E-type P-channel and N-channel MO inserted between
It is applied to the CMOS inverter 39 composed of S transistors. The output of the inverter 39 is applied to the transistors 2 and 4 in FIG. 1 as the output of the column predecoder 7. The other column predecoder 8 is also configured similarly to this, and only differs from the case of FIG. 2 in the 2-bit address input.

Next, the operation of the circuit configured as described above will be described. First, when data is read from the memory cell M shown in FIG. 11, that is, in the read mode, both control signals S2 and S3 are "1" as shown in the timing chart of FIG.
It becomes a level (5V). Moreover, the high voltages HV1, HV2, HV3 of the nodes 15, 16 and 17 are all set to the ground voltage VS. Here, when the control signal S2 becomes "1" level, the transistor 32 in FIG.
35 becomes conductive, and the NAND circuit 38 substantially operates as a 2-input NAND circuit. At this time, if the outputs of the column predecoders 7 and 8 are both at "1" level, the signal at the output node 1 of the NAND circuit 6 becomes "0" level and the signal at the output node 12 of the inverter 11 becomes 5V "1". "Become a level. At this time, since a signal of 5V is applied to the gate of the D-type transistor 13 and the transistor 13 is conducting, the column selection line COLi also becomes 5V "1" level via the transistor 13. On the other hand, when at least one of the outputs of the column predecoders 7 and 8 is at "0" level, the signal of the output node 1 of the NAND circuit 6 is at "1" level and the signal of the output node 12 of the inverter 11 is at "0" level. And the column selection line COLi also becomes 0V.

Next, in the program mode for programming data in the memory cell M shown in FIG. 11, the control signal S2 is set to "1" level and the control signal S3 is set to "0" level as shown in FIG. It At this time, each node 1 in FIG.
A predetermined high voltage is applied to each of 5, 16 and 17. If the outputs of the column predecoders 7 and 8 are both "1" level, the signal of the output node 1 of the NAND circuit 6 becomes "0" level and the signal of the output node 12 of the inverter 11 becomes 5V of VC. . At this time, 0V is applied to the gate of the D-type transistor 13.
Is applied, the voltage corresponding to the absolute value of the threshold voltage of the D-type transistor is output to the column selection line COLi via the transistor 13. For example, this voltage is 2.5V-3V
It is a degree. Therefore, the transistors 21 and 19 whose gates are connected to the column selection line COLi become conductive, and at this time, the high voltage HV1 is applied to the node 15 and the high voltage HV is applied to the node 17.
Since V3 is applied respectively, transistors 22 and 20
Therefore, the high voltage HV1 is output to the column selection line COLi through the transistors 22, 20 and 21 in series,
The voltage rises to almost HV1. Further, since the high voltage VH2 is applied to the node 16 and the voltage VH3 higher than the high voltage HV2 by the threshold voltage of one E-type N-channel MOS transistor is applied to the gate of the transistor 20, , Column select line COLi has transistors 19, 20 and 21
The high voltage HV2 is output via the series. At this time, D
Since the voltage VC of 5 V at the output node 12 of the inverter 11 is applied to one end of the transistor 13 of the mold, the transistor 12 becomes conductive. Therefore, there is no possibility that the high voltage HV2 output to the column selection line COLi will be applied to the transistors forming the low voltage type CMOS inverter 11. Then, by outputting the high voltage HV2 to the column selection line COLi,
One transistor Ci shown in FIG. 11 connected to this line COLi becomes conductive. At this time, since the gate voltage HV2 is set to a voltage higher than the high voltage VP by the threshold voltage of one E-type MOS transistor, the high voltage VP is output to the corresponding column line BL.

On the other hand, if at least one of the column predecoders 7 and 8 is at "0" level during programming, the signal at the output node 1 of the NAND circuit 6 becomes "1" level and the output node 12 of the inverter 11 becomes The signal goes to "0" level. Therefore, the column selection line COLi is set to 0V via the D-type transistor 13. At this time, from the node 15 of the high voltage HV1 to the transistors 22, 20, 21, 13 and the N channel MOS in the inverter 11.
A current flows through the transistor 10 in series. At this time, each of the transistors 22, 20, 21, 13, 10 is set so that the voltage of the node 18 becomes equal to or higher than the absolute value of the threshold voltage of the transistor 19.
If the respective element dimensions are set, the transistor 19 becomes non-conductive, and current loss from the boosted high voltage HV2 does not occur. Where E-type MOS transistor 1
By setting the value of the conduction resistance of 7 to be high, the D-type MOS transistor 21 can be omitted.

By the way, in EPROM, in order to determine whether the write data is correct after data programming,
Immediately after the programming, the read operation of the write data is performed. This is normally called the verify mode. In this verify mode, as shown in FIG. 3, the control signal S2 is set to "0" level during a certain period at the beginning of the mode, and then the normal read operation is performed. It is set to "1" level as in the mode. Further, the control signal S3 is set to the "1" level after the signal S2 is changed from the "0" level to the "1" level.

In the verify mode, as in the normal read mode, the column selection line COLi
It is necessary to output 5V voltage VC or 0V voltage VS. At this time, if the signal S3 is set to the "1" level from the time when the program mode ends, the D-type transistor 13
And the high voltage HV2 applied to the column selection line COLi in the program mode is a low voltage circuit circuit.
Applied to. At this time, the P channel in the inverter 11
If the MOS transistor 9 is conductive, the high voltage HV2 is applied to the p ⁺ diffusion region which is the drain region of the P-channel MOS transistor 9, the potential of this diffusion region becomes higher than the n well potential, and the forward current is generated. It causes a flow and latch-up. However, in the above-described embodiment circuit, at the beginning of this verify mode, the D-type transistor 13 is still non-conductive because the control signal S3 is kept at "0" level, and the voltage of the node 12 is the type-2. It does not rise above the absolute value of the threshold voltage of the transistor. Moreover, at the beginning of the verify mode, the control signal S2 is set to the "0" level for a predetermined period, so that the transistor 32 becomes conductive in the column predecoder of FIG. 2 and the signal of the output node 31 of the NAND circuit 38 is addressed. It becomes "1" level regardless of. This allows
The output of the inverter 39 becomes "0" level, and the signal of the output node 1 of the NAND circuit 6 in the circuit of FIG. 1 becomes "1" level. That is, while the control signal S2 is at "0" level, the N-channel MOS transistor 10 in the inverter 11 is turned on regardless of the address. As a result, the high voltage HV2 applied to the column selection line COLi in the program mode is discharged through the transistor 13 and the transistor 10. For this reason, the column selection line COLi
The latch-up of the low voltage system circuit due to the high voltage HV2 applied to the circuit is prevented. The high voltage HV3 is the control signal S2.
Becomes "0" level while becomes "0" level. High voltage HV2
The control signal S2 goes to "1" level after the discharge of the signal, which enables the column predecoder to operate by address, and the control signal S3 goes to "1" level, which turns on the transistor 13. Become.

The circuit shown in FIG. 1 is provided in the number n corresponding to the number of column selection lines in the circuit shown in FIG. If the EPROM shown in FIG. 11 has a multi-bit configuration, the circuit of FIG. 1 is provided by the number of bits. In such a case, the high voltage applied to the nodes 15, 16 and 17 can be shared by all circuits.

By the way, in the circuit shown in FIG. 1, the transistors of the high-voltage circuit to which a high voltage is applied, that is, the transistors 13, 19, 20, 21, and 22 are all N-channel type,
For all of these, for example, a high breakdown voltage structure such as the LDD structure described above is adopted. Therefore, in the high voltage system circuit, P
The channel MOS transistor is unnecessary, and latch-up, which has been a problem in the past, does not occur. Moreover, since a P-channel MOS transistor having a high breakdown voltage structure is not required, there is no N well region to which a high voltage is applied, and thus the entire area can be reduced. Further, when reading data, the direct current consumption can be reduced to 0 as in the case of the conventional CMOS configuration.

That is, in the above embodiment, the high voltage system circuit is an N channel
It is composed of only MOS transistors, and at the time of programming data, it selectively outputs a high voltage to improve the write characteristics of the memory cell, and
The current consumption can be reduced to 0 as in the case of the CMOS configuration. Moreover, it is possible to prevent latch-up due to a high voltage in the verify mode.

FIG. 4 is a circuit diagram showing a configuration of a signal generating circuit for generating the control signal S2 based on the control signal S1 which is set to "0" level in the program mode and set to "1" level in the other periods. Control signal S1 is P channel and N channel MOS
It is input to the CMOS inverter 41 composed of transistors. The output of the inverter 41 is input to the delay circuit 42. The output of the delay circuit 42 and the control signal S1 are 2
The control signal S2 is input to a CMOS NAND circuit 43 composed of P-channel and N-channel MOS transistors, and the control signal S2 is obtained as an output signal of the NAND circuit 43.

FIG. 5 is a circuit diagram showing a specific configuration of a booster circuit that outputs the boosted high voltages HV2 and HV3. In this step-up circuit, an odd number of E / D-type inverters 47 each having a D-type MOS transistor 45 as a load transistor and an E-type MOS transistor 46 as a drive transistor are provided in series, and a D-type inverter 47 is provided between the inverters. A delay circuit including a MOS transistor 48 and a capacitor 49 is provided, the output of the final stage inverter is fed back to the first stage inverter, and the inverted signal of the control signal S1 is applied to the gate between all the inverters 47 and the ground voltage VS. A ring oscillating circuit portion 51 formed by providing an E-type MOS transistor 50 is provided. In the ring oscillator circuit section 51, when the control signal is set to the "1" level, the transistor 50 is turned on to enable each inverter 47 to operate, and the final stage inverter 47 outputs the pulse signal OSC of a predetermined cycle. Is output.

Further, this booster circuit is provided with a booster unit 52 of a so-called charge pump system. When the pulse signal OSC is output from the ring oscillation circuit section 51 at the time of data programming, the voltage of the node 54 via the capacitor 53 sequentially rises as the pulse signal OSC changes. This node 54
Is output to the output node 17 of the voltage HV3 via the E-type MOS transistor 55 for rectification. Further above node 1
The voltage of 7 is output to the output node 16 of the voltage HV2 through the E-type MOS transistor 56 for rectification. In addition, the control signal S1
Is set to "1" level, D-type MOS transistor 5
7 and E type MOS transistor 58 are connected in series to node 17
Is set to the ground voltage VS, and similarly, the node 16 is set to the ground voltage VS via the D-type MOS transistor 59 and the E-type MOS transistor 60 in series. It should be noted that all the transistors forming this booster circuit are N-channel transistors. Further, the high voltage HV1 is output-controlled, for example, via a MOS transistor to which an external program voltage VP is applied at one end and the voltage obtained by the booster 52 is applied to the gate.

By the way, in the EPROM, not only the column coder but also the row decoder and the data writing circuit output a high voltage.

FIG. 6 is a circuit diagram showing the configuration of another embodiment of the present invention. This embodiment circuit shows the row decoder 131 of the EPROM shown in FIG. In this circuit, for example, three E-type N channel MOs are connected between the node 71 and the ground voltage VS.
S transistors 72, 73, 74 are inserted in series. The output of a row predecoder described later is applied to the gates of these MOS transistors 72, 73, 74. Further above node 71
Has m E-type N-channel MOS transistors corresponding to the number of row lines WL.
One end of each of the transistors 75-j (i = 1, ..., M) is connected. Only one of the transistors 75-j is conductively controlled based on an address not shown. A P-channel MOS transistor 76-j as a load transistor is inserted between the other end of each transistor 75-j and the voltage VC. At the other end of each transistor 75-j, each C composed of P-channel and N-channel MOS transistors is provided.
The input node of the MOS inverter 77-j is connected.
D is applied to the output node 78-j of each CMOS inverter 77-j.
Type N-channel MOS transistor 79-j is connected to one end thereof. The control signal S3 is applied to the gate of the transistor 79-j, and the other end of the transistor 79-j is connected to the corresponding one row line WLj. Above line W
The Lj is provided with an output circuit 80-j for controlling the output of the high voltage VP. This output circuit 80-j is an E-type N-type transistor inserted in series between the node 81 to which the high voltage VP is applied and the row line Lj.
It is composed of a channel MOS transistor 82 and a D-type N-channel MOS transistor 83. A voltage higher than VP is applied to the gate of the transistor 82, and the gate of the transistor 83 corresponds to it. Line WL
connected to j.

FIG. 7 is a circuit diagram showing a specific configuration of one row predecoder that outputs gate control signals for the transistors 72, 73 and 74 in FIG. In this circuit, for example, when the address input is 2 bits, three E-type P-channel MOS transistors 86, 87, 88 are inserted in parallel between the voltage VC and the node 85, and the node 85 and the ground are connected. Three E-type N-channel MOS transistors 89, 90, 91 are inserted in series with the voltage VS, and these transistors form an address.
A 3-input CMOS NAND circuit 92 for inputting A11, A12 and the control signal S2 is configured. The output of the NAND circuit 92 is input to a CMOS inverter 93 composed of P-channel and N-channel MOS transistors, and the output of the inverter 93 is applied to the circuit of FIG. 6 as the output of the one row predecoder.

In the circuit of this embodiment, the control signal S3 is set to the "0" level for the row line WLj to which the high voltage VP has been output via the output circuit 80 in the program mode, during the subsequent predetermined period in the verify mode. By D-type transistor 79
Are turned off. Then, while the transistor 79 is in the non-conducting state, the output from the row predecoder in FIG. 7 is forcibly set to "0" level during the period of the control signal S2, and the node 71 is set to "0" level. It will not be done.
Therefore, the input node of the inverter 77 is set to "1" level by the transistor 76 provided on the row line WL selected in the program mode, and the N-channel MOS transistor in the inverter 77 is rendered conductive. As a result, the high voltage output to this row line WL is
As in the case of the embodiment circuit shown in the figure, a non-conductive D-type MOS
It is discharged through the transistor 79 and the N-channel MOS transistor in the inverter 77.

FIG. 8 is a circuit diagram showing the configuration of still another embodiment of the present invention. This embodiment circuit shows the EPROM data write circuit 135 shown in FIG. Two E-type P-channel MOS transistors 101 and 102 and an E-type N-channel MOS transistor 103 are connected in series between the voltage VC and the ground voltage VS. Further, an E-type N channel M is connected between the connection node 104 of the transistors 102 and 103 and the ground voltage VS.
OS transistor 105 is connected, and CMOS NOR circuit 1
06 is configured. Then, data data is applied to the gates of the transistors 102 and 103, and the transistors 101 and 105
The control signal S1 is applied to the gate of the. Above node
The CMOS inverters 115 to 118 composed of E-type P-channel MOS transistors 107 to 110 and E-type N-channel MOS transistors 111 to 114 are connected in multiple stages to 104, and the output node of the final stage inverter 118 is connected. 119 is connected to one end of a D-type N-channel MOS transistor 120 whose gate receives the control signal S3. The other end of the transistor 120 is connected to the output node 121 of the write data DIN. Further, the node 121 is connected to an output circuit 14 'in which the transistor 20 is omitted from the output circuit 14 in the circuit shown in FIG.

In the data write circuit of this embodiment circuit, DIN is always set to the ground voltage VS and is not set to VC when reading data. Therefore, there is no possibility that current will flow into the node 16, so that the transistor 20 for cutting off this current path is unnecessary.

9 and 10 are circuit diagrams each showing a configuration of a modified example of the embodiment circuit shown in FIG. In the circuit of the first embodiment, the N channel in the inverter 11 in the verify mode is used.
A transistor controlled by the control signal S2 is provided in the column predecoder so that the MOS transistor 10 is rendered conductive for a predetermined period regardless of the address. On the other hand, in the modified circuit of FIG. 9, an N-channel MOS transistor 23 controlled by the control signal S2 is inserted between the transistor 5 and the ground voltage VS, and a P-channel MOS transistor controlled by the control signal S2. The transistor 24 is inserted between the voltage VC and the node 1.

Further, in the modified circuit of FIG. 10, P controlled by the control signal S2
A channel MOS transistor 25 is inserted between the voltage VC and the transistor 9, and an N channel MOS transistor 26 controlled by a control signal S2 is inserted between the output node 12 of the inverter 11 and the ground voltage VS. It is the one.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, the case where the D-type MOS transistor 13 is used in the embodiment circuit of FIG. 1 has been described. This is the E-type when the control signal S3 can be applied with a signal boosted higher than VC. Can be used.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of preventing the occurrence of latch-up and preventing the chip size from increasing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the structure of an embodiment of the present invention, and FIG.
FIG. 4 is a circuit diagram showing a specific configuration of the column predecoder used in the circuit shown in FIG. 1, FIG. 3 is a timing chart for explaining the operation of the circuit of the embodiment, and FIG.
FIG. 5 is a circuit diagram showing a concrete structure of a control signal generating circuit used in the circuit shown in FIG. 5, FIG. 5 is a circuit diagram showing a concrete structure of a booster circuit used in the circuit shown in FIG. 1, and FIG. FIG. 7 is a circuit diagram showing a structure of another embodiment, FIG. 7 is a circuit diagram showing a concrete structure of a row predecoder used in the circuit shown in FIG.
FIG. 8 is a circuit diagram showing a configuration of still another embodiment of the present invention, FIGS. 9 and 10 are circuit diagrams showing a configuration of a modified example of the implementation circuit of FIG. 1, and FIG. 11 is an EPROM. Circuit diagram showing the general configuration, Fig. 12 is the EPROM characteristic diagram of Fig. 11, Fig. 1
FIG. 3 is a circuit diagram showing a part of the structure of a conventional EPROM column decoder, FIG. 14 is a circuit diagram of a column predecoder used in the column decoder of FIG. 13, and FIG. 15 shows a high breakdown voltage structure. It is a sectional view of the adopted MOS transistor. 6 ... CMOS NAND circuit, 11 ... CMOS inverter, 12 ...
Output node of CMOS inverter, 13 ... Depletion type N-channel MOS transistor, 14 ... Output circuit, 19 ...
... depletion type N-channel MOS transistor, 20
...... Enhancement type N channel MOS transistor, 21 ...... Depletion type N channel MOS transistor, 22 ...... Enhancement type N channel MOS transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masamichi Asano Inoue Masamichi, Kawasaki-shi, Kanagawa 1 Komushiba-shi, Kawasaki-shi Kanagawa factory (72) Inventor Hidenobu Minagawa 25, Kawasaki-ku, Kawasaki-ku, Kanagawa 1 Toshiba Microcomputer Engineering Co., Ltd. (72) Inventor Yuichi Tatsumi 25, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 1 Toshiba Microcomputer Engineering Co., Ltd. (56) Reference Japanese Patent Laid-Open No. 61-50289 (JP, A)

Claims (5)

[Claims] 1. A CMOS circuit operating at a first voltage, an output circuit for controlling output of a second voltage higher than the first voltage to a signal output node, an output node of the CMOS circuit and the signal output. A separating MOS transistor inserted between the node and the gate to which the first control signal is applied,
After the period of outputting the second voltage to the signal output node, the output node of the CMOS circuit is discharged while the conduction resistance of the MOS transistor for isolation remains high, and then the first control signal causes the output node of the CMOS circuit to discharge. A semiconductor integrated circuit characterized in that it is configured to reduce the conduction resistance of a MOS transistor for isolation. 2. The semiconductor integrated circuit according to claim 1, wherein the output circuit is composed of a single-channel MOS transistor. 3. The output circuit comprises a first node to which a third voltage is applied, a second node to which a second voltage higher than the third voltage is applied, and the second node. Node and third
A first depletion-type MOS transistor having a gate connected to the signal output node and a gate inserted between the first node and a third node. And an enhancement type second MOS transistor connected between the second voltage source and the signal output node and a fourth voltage higher than the third voltage is applied to the gate of the enhancement type second MOS transistor. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is formed of the third MOS transistor. 4. A third voltage applied to the second node and a fourth voltage applied to the third MOS transistor are output from a booster circuit that boosts the second voltage, respectively. The semiconductor integrated circuit according to claim 3, 5. The output circuit is inserted between the first node to which the second voltage is applied and the first node and the second node, and the gate is higher than the second voltage. Enhancement-type first MOS to which a high third voltage is applied
3. The semiconductor according to claim 2, comprising a transistor and a second MOS transistor inserted between the second node and the signal output node and having a gate connected to the signal output node. Integrated circuit.