JPH0686024A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To evade the enlargement of a circuit scale and the complication of processing and to reduce the deviation in offsetting voltages. CONSTITUTION:Respective photoelectric conversion circuits 3-1-3-n are provided with photoelectric converting elements for generating a photoelectric current corresponding to incident light quantity and output signal output based on the photoelectric current from the photoelectric converting elements. Also, the photoelectric conversion circuits 4-1-4-n for correction are respectively arranged near the respective photoelectric conversion circuits 3-1-3-n corresponding to the photoelectric conversion circuits. The constitution of the respective photoelectric conversion circuits for the correction is the same as the corresponding photoelectric conversion circuits. Light shielding is applied to the photoelectric converting elements and the offsetting voltage is outputted as the signal output. Thus, by correcting the signal output from the photoelectric conversion circuits 3-1-3-n by the signal output from the photoelectric conversion circuits 4-1-4-n for the correction, the deviation of the offsetting voltage can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device for a digital (color) copying machine, desktop publishing (D).
The present invention relates to a photoelectric conversion device used in an image data input device such as TP), a document reading device such as a facsimile, and an image pickup device such as a VDT.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram of a conventional photoelectric conversion device. This photoelectric conversion device includes a plurality of photoelectric conversion circuits 51-1 to 51-n arranged in an array or matrix corresponding to each pixel (each bit) and each photoelectric conversion circuit 51-1 to 51-n. Is output to the common signal line CM, a timing generation circuit 52 for outputting the photoelectric conversion result from the common signal line CM as an output signal in time series, a switch S19 for initializing the potential of the common signal line CM, and the common signal line CM. And a buffer B8 for impedance-converting the output signal to obtain a final signal output OUT. Each of the photoelectric conversion circuits 51-1 to 51-n has the same configuration as each other and is composed of elements such as a photoelectric conversion element, an amplification element, a resetting element, and a reading element.

9 (a) and 9 (b) are time charts for explaining the operation of the photoelectric conversion device having the above configuration. Note that FIG. 9B is an enlarged view of the portion indicated by reference numeral PT1 in FIG. 9A in the time axis direction. 8 and 9
The operation of this photoelectric conversion device will be described with reference to (a) and (b). First, when the start pulse ST is input to the timing generation circuit 52, the timing generation circuit 52 outputs the control signals CTL1 to C in synchronization with the clock CLK.
TLn is sequentially added to the photoelectric conversion circuits 51-1 to 51-n. As a result, each of the photoelectric conversion circuits 51-1 to 51
For −n, photoelectric conversion is sequentially performed, and each photoelectric conversion result is output to the common signal line CM in time series, and finally output from the buffer B8 as a signal output OUT. After that, the switch S19 is turned on by the control signal CTLR from the timing generation circuit 52 to initialize the potential of the common signal line CM, and the start pulse ST is input again to repeat the same operation, for example, for each line. Scanning can be performed.

[0004]

By the way, in such a photoelectric conversion device, each of the photoelectric conversion circuits 51-1 to 51-n has an offset voltage due to a difference in element characteristics in manufacturing or a temperature gradient. Vary. Note that FIG.
In the signal output OUT of FIGS. 9A and 9B, the offset voltage component is shown by a broken line. In order to correct the variation in the offset voltage, conventionally, all bits, that is, the offset voltages of all the photoelectric conversion circuits 51-1 to 51-n are output, and these are written in the memory as correction data. , Photoelectric conversion circuits 51-1 to 5-5
1-n is read, and each photoelectric conversion circuit 51
The correction data corresponding to the read data of -1 to 51-n is subtracted. However, in such a correction process, since the correction data of all bits must be stored in the memory, a considerable memory capacity is required, and the correction data is subtracted from the read data. Is required. Therefore, there is a drawback that the circuit scale becomes large and the processing becomes complicated. Further, although such an arithmetic process can reduce the variation in the offset voltage due to the difference in the device characteristics in manufacturing, it cannot reduce the variation in the offset voltage due to the temperature change and the like. was there.

The present invention avoids an increase in circuit scale and complication of processing, and not only offset voltage variations caused by differences in device characteristics during manufacturing but also offset voltage variations caused by temperature changes and the like. An object of the present invention is to provide a photoelectric conversion device capable of reducing variations.

[0006]

In order to achieve the above object, the invention according to claim 1 is a photoelectric conversion device having at least one photoelectric conversion circuit, wherein each photoelectric conversion circuit responds to the amount of incident light. A photoelectric conversion element that generates a photocurrent is provided, and a signal output based on the photocurrent from the photoelectric conversion element is output. Further, a correction photoelectric conversion circuit is provided near each photoelectric conversion circuit. Are arranged corresponding to the photoelectric conversion circuits, and each correction photoelectric conversion circuit is
It has the same configuration as the corresponding photoelectric conversion circuit, but is characterized in that the photoelectric conversion element is shielded from light and the offset voltage is output as a signal output. As described above, since the signal output from the photoelectric conversion circuit can be corrected by the signal output from the correction photoelectric conversion circuit arranged in the vicinity of each photoelectric conversion circuit, it is possible to increase the circuit scale and processing. It is possible to avoid complication and reduce not only the variation of the offset voltage caused by the difference in the device characteristics in manufacturing but also the variation of the offset voltage caused by the temperature change and the like.

According to the second aspect of the invention, the first aspect is
In the photoelectric conversion device described above, a difference between a signal output from a certain photoelectric conversion circuit and a signal output from a correction photoelectric conversion circuit corresponding to the photoelectric conversion circuit is calculated, and an arbitrary constant offset voltage is added to this difference. It is characterized in that correction means for outputting the superimposed voltage as a final output signal is further provided. In the invention according to claim 3,
3. The photoelectric conversion device according to claim 2, wherein the correction means has a capacitor, and a signal output from a certain photoelectric conversion circuit is added to one terminal of the capacitor, and the other terminal of the capacitor is added. In addition, the signal output from the correction photoelectric conversion circuit corresponding to the photoelectric conversion circuit is added, and when the final output signal is read,
An arbitrary offset voltage is applied to one terminal or the other terminal of the capacitor, and the voltage of the other terminal or the one terminal of the capacitor is read out as a final output signal. Like this one
The difference between the signal output from one photoelectric conversion circuit and the signal output from the correction photoelectric conversion circuit corresponding to the photoelectric conversion circuit is taken, and a voltage obtained by superimposing an arbitrary constant offset voltage on this difference is finally output. By further providing the correction means for outputting as a signal, the offset voltage can be corrected in this device, and the signal output set to an arbitrary DC voltage level can be obtained. The connection with the stage becomes easier, and the burden of the power supply voltage can be reduced.

According to a fourth aspect of the present invention, in a photoelectric conversion device having a photoelectric conversion circuit group including a plurality of photoelectric conversion circuits, the plurality of photoelectric conversion circuits forming the photoelectric conversion circuit group operate sequentially. , A signal output based on a photocurrent corresponding to the amount of incident light is sequentially output, and first and second correction photoelectric conversion circuits are arranged at both ends of the photoelectric conversion circuit group. Based on the signal voltage from the first and second correction photoelectric conversion circuits,
A feature is that a plurality of offset voltages are generated and are output as a correction output for the signal output from the plurality of photoelectric conversion circuits that constitute the photoelectric conversion circuit group. According to a fifth aspect of the present invention, in the photoelectric conversion device according to the fourth aspect, the plurality of offset voltages are output from the first correction photoelectric conversion circuit.
Offset voltage, the second offset voltage output from the second correction photoelectric conversion circuit, and the third offset voltage obtained by averaging the first offset voltage and the second offset voltage. , The photoelectric conversion circuit group is divided into first, second and third blocks from the first correction photoelectric conversion circuit toward the second correction photoelectric conversion circuit,
The first, second, and third offset voltages are output as correction outputs for the output signals from the photoelectric conversion circuits belonging to the first, second, and third blocks, respectively. I am trying. As a result, it is possible to avoid an increase in the circuit scale and complexity of processing, and not only a variation in the offset voltage due to a difference in device characteristics during manufacturing,
It is also possible to reduce variations in offset voltage due to temperature changes and the like.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a photoelectric conversion device according to the present invention. This photoelectric conversion device is provided with a plurality of photoelectric conversion units U1 to Un arranged in an array or matrix corresponding to each pixel (each bit). Each of the photoelectric conversion units U1 to Un has the same configuration. For example, the n-th (n-th bit pixel) photoelectric conversion Un is the photoelectric conversion circuit 3-n.
And a correction photoelectric conversion circuit 4-n arranged at a position close to the photoelectric conversion circuit 3-n.

FIG. 2 is a diagram showing a configuration example of one photoelectric conversion unit U (for example, Un). In this example, the photoelectric conversion circuit 3 of the photoelectric conversion unit U includes a photoelectric conversion element 1, an amplification element Q1, a switch S1 for initializing the gate potential of the amplification element Q1 to VR1, and a source of the amplification element Q1. It has a switch S2 for initializing the potential to VR2 and a switch S3 for outputting the output signal of the photoelectric conversion circuit 3 (the potential of the source of the amplifying element Q1) to the signal line 12. Here, one terminal of the photoelectric conversion element 1 is connected to the gates of the switch S1 and the amplification element Q1, and the other terminal of the photoelectric conversion element 1 is connected to the sources of the switches S2 and S3 and the amplification element Q1. Therefore, the photoelectric conversion element 1 has a gate / source connected to the amplification element Q1.
An inter-cell potential is applied. The photoelectric conversion element 1 is composed of, for example, a photodiode, and the amplification element Q
1 is, for example, a depletion type N-channel MOS / F
It is composed of ET.

The correction photoelectric conversion circuit 4 also has the same structure as the photoelectric conversion circuit 3. That is, the correction photoelectric conversion circuit 4 includes the photoelectric conversion element 1, the amplification element Q1, the switch S1, the switch S2, and the switch S of the photoelectric conversion circuit 3.
A photoelectric conversion element 2, an amplification element Q2, a switch S4, a switch S5, and a switch S6 having the same function are provided corresponding to No. However, unlike the photoelectric conversion element 1 of the photoelectric conversion circuit 3, the photoelectric conversion element 2 of the correction photoelectric conversion circuit 4 is shielded from light.

Further, in FIG. 1, each of the photoelectric conversion units U1 to Un is controlled by control signals CTL1 to CTLn from the timing generation circuit 11. Focusing on one photoelectric conversion unit U (for example, Un), the control signal CTLn (control signals 5, 6, 6) from the timing generation circuit 11 is included in this photoelectric conversion unit U.
7) is added, among them, the control signal 5 includes the switch S of the photoelectric conversion circuit 3 and the switch S of the correction photoelectric conversion circuit 4.
4 is controlled to be ON / OFF, and the control signal 6 is the switch S2 of the photoelectric conversion circuit 3 and the switch S of the correction photoelectric conversion circuit 4.
The ON / OFF of 5 is controlled, and the control signal 7 is the switch S of the photoelectric conversion circuit 3 and the switch S of the correction photoelectric conversion circuit 4.
6 is controlled to be turned on and off. In other words, the photoelectric conversion device 3 and the correction photoelectric conversion circuit 4 are controlled in operation by the common control signal CTLn from the timing generation circuit 11, that is, the control signals 5, 6, and 7.
When the switches S3 and S6 are turned on, the common signal line CM
An output signal is output to each of 1 and CM2.

In the photoelectric conversion device of FIG. 1, the common signal line CM1 has a switch S7 for initializing the potential of the common signal line CM1 and an output signal output to the common signal line CM1. A buffer B1 for converting and amplifying is connected, and a switch S8 for initializing the potential of the common signal line CM2 is connected to the common signal line CM2.
The output signal output to the common signal line CM2 is connected to a buffer B2 that performs impedance conversion and amplification, and the switches S7 and S8 are the timing generation circuit 11
On / off control is performed by a common control signal CTLR from.

Next, the operation of the photoelectric conversion device of FIG. 1 will be described with reference to FIG.
An explanation will be given using the time charts of (a) and (b). Note that FIG. 3B is an enlarged view of the portion indicated by reference numeral PT2 in FIG. 3A in the time axis direction. In this photoelectric conversion device, the start pulse ST is first transmitted to the timing generation circuit 1
When input to 1, the timing generation circuit 11 sequentially applies the control signals CTL1 and CTLn synchronized with the clock CLK to the photoelectric conversion units U1 to Un. Accordingly, the photoelectric conversion circuits and the correction photoelectric conversion circuits of the photoelectric conversion units U1 to Un perform photoelectric conversion. Now, focusing on the photoelectric conversion circuit 3 of one photoelectric conversion unit U (for example, the nth bit photoelectric conversion unit Un), the control signal CTLn (5, 6, 7) synchronized with the clock CLK is added from the timing generation circuit 11. As a result, the switches S1 and S2 are turned on first, and the potential of the gate of the amplification element Q1 becomes VR1 and the potential of the source thereof becomes V1.
The photoelectric conversion circuit 3 is initialized as R2. Next, when S2 is turned off, the potential of the source of the amplification element Q1 becomes VR1 + Vth by charging the parasitic capacitance of S2 and the floating capacitance of the source. That is, the gate potential becomes higher than the gate potential by the gate-source voltage Vth. After that, when S1 is turned off, for example, reading of an image starts, and a photoelectric current according to the amount of incident light flows through the photoelectric conversion element 1 during a certain reading period. Photoelectric conversion element 1
When light is incident on and a photocurrent flows, the photocurrent starts to be accumulated in the capacitance (storage capacitance) connected to the gate of the amplification element Q1. In this way, the charge based on the photocurrent is accumulated in the capacitor connected to the gate of the amplification element Q1, so that the potential of the gate rises and the potential of the gate rises, and at the same time, the potential of the source also becomes parasitic of S2. While charging the capacitance and stray capacitance of the source, it rises by the rise of the gate potential. In this way, the amplification element Q1 functions as a source follower whose source voltage changes following the gate voltage.

The photoelectric conversion circuit 3 is initialized again after a certain reading time (accumulation time) has passed, but S3 is turned on in a half cycle of the clock CLK immediately before the initialization, and the source just before the initialization is started. Is output to the common signal line CM1 as an output signal. That is, in the photoelectric conversion circuit 3, an optical signal corresponding to the amount of light incident on the photoelectric conversion element 1 is output to the common signal line CM1, impedance-converted by the buffer B1 and output as a signal output OUT1. Then, in the next half cycle of the clock CLK, S3 is turned off, S7 is turned on, and the potential of the common signal line CM1 is initialized to, for example, “0” V. At the same time, S1 and S2 are turned on. When turned on, the amplification element Q1 is initialized. Correction photoelectric conversion circuit 4 of photoelectric conversion unit U
Also operates under the same control as the photoelectric conversion circuit 3, and the potential of the source of the amplifying element Q2 is output signal OU immediately before initialization.
The signal is output as T2 to the common signal line CM2, but since the photoelectric conversion circuit 4 for correction has the photoelectric conversion element 2 shielded from light, light does not enter the photoelectric conversion element 2, and therefore the common signal line is not received. The output signal output to the CM 2 indicates the offset voltage of the photoelectric conversion circuit 4.

The clock C is also applied to the photoelectric conversion units U2 to Un of the 2nd bit, the 3rd bit, ..., And the nth bit.
Similar processing is sequentially performed with a shift of a predetermined period in synchronization with LK. That is, the output signal from the photoelectric conversion circuit 3, that is, the optical signal is sequentially output as the output signal OUT1, and the output signal from the correction photoelectric conversion circuit 4, that is, the offset voltage is sequentially output as the output signal OUT2.

By the way, each of the photoelectric conversion units U1 to U
The n photoelectric conversion circuit 3 has an offset voltage (output voltage in a state where no light is incident), and the output signal OU
This offset voltage is superposed on a pure optical signal component at T1, but this offset voltage is due to variations in device characteristics in manufacturing, temperature gradient, temperature change, etc. Bits are not constant, and vary from bit to bit. Note that FIG.
In the signal output OUT1 of (a) and (b), the offset voltage component is indicated by a broken line. In the first embodiment, the correction photoelectric conversion circuit 4 produces an offset voltage for each bit in order to reduce such a variation in the offset voltage for each bit in the photoelectric conversion circuit 3. That is, between circuit cells located close to each other, manufacturing variations, temperature gradients,
Alternatively, paying attention to the fact that the factors of variations due to temperature changes and the like can be made almost equal, and in each bit, that is, in each photoelectric conversion unit U1 to Un, the correction photoelectric conversion circuit 4 is arranged in a position close to the photoelectric conversion circuit 3. is doing. As a result, a photoelectric conversion unit such as Un
In the above, the output signal OUT2 output from the correction photoelectric conversion circuit 4, that is, the offset voltage, is a good approximation of the offset voltage of the photoelectric conversion circuit 3 of this unit Un, and this can be used as the correction signal. . That is, the output signal OUT1 and the output signal OUT
By performing differential amplification with respect to 2 and subtracting the output signal OUT1, the offset voltage can be almost removed from the output signal OUT1 and only the optical signal component can be read.

As described above, even when the offset voltage of the photoelectric conversion circuit 3 varies for each bit due to not only the difference in element characteristics but also the temperature change and the like, the output signal OUT1 and the output signal OUT2 are obtained for each bit. If the differential output of DIF is performed as the differential output DIF, the offset voltage can be almost removed, and only the optical signal component can be almost extracted, and an output with a very small offset voltage variation can be easily obtained. it can. Therefore, there is no need for a memory for writing correction data or a complicated arithmetic processing circuit, and it is possible to avoid an increase in circuit size and processing, and to avoid complications, and to prevent not only manufacturing element characteristics but also temperature changes. It is possible to extremely reduce the variation in the offset voltage caused by it.

FIG. 4 is a diagram showing a second embodiment of the photoelectric conversion device according to the present invention. In addition, in FIG. 4, it is assumed that a plurality of photoelectric conversion units U1 to Un similar to those shown in FIG. 1 are connected to the common signal lines CM1 and CM2.
In the second embodiment, means for performing arithmetic control on the output signals OUT1 and OUT2 from the buffers B1 and B2 is further provided. That is, the switches S11, S
12, a capacitor C1, and switches S13 and S20
And a buffer B3 are further provided. here,
The switch S11 is connected to one terminal 18 of the capacitor C1.
When the switch S13 is on, the output signal OUT1 from the buffer B1 is applied, and when the switch S13 is on, a predetermined voltage V3 is applied. Also, the capacitor C
The output signal OUT2 from the buffer B2 is applied to the other terminal 19 of 1 when the switch S12 is on, and the potential difference from the one terminal 18 of the capacitor C1 is output when the switch S12 is off. ing.

The operation of the second embodiment having such a configuration will be described with reference to the time charts of FIGS. 5 (a) and 5 (b).
Note that FIG. 5B is an enlarged view of the portion indicated by reference numeral PT3 in FIG. 5A in the time axis direction. Also, FIG.
For convenience of description, (a) and (b) are illustrated as a case where almost no light is incident on the photoelectric conversion circuit 3. In this photoelectric conversion device, for example, until the switches S3 and S6 of the photoelectric conversion circuit 3 and the correction photoelectric conversion circuit 4 of the photoelectric conversion unit U1 of the first bit are turned on, the switch S
7, S8, S11, S12, S20 are on, switch S
13 is off, and the signal output OUT3 from the buffer B3 is almost "0" V. Switch S3
When S6 is turned on, switches S7, S8, S13, S
20 is turned on / off in the same phase and the same cycle as the clock CLK, and the switches S11 and S12 are turned on / off in the opposite phase and the same cycle as the clock CLK. That is, when the switches S3 and S6 are turned on, the output signals from the photoelectric conversion circuit 3 and the correction photoelectric conversion circuit 4 are output to the common signal lines CM1 and CM2, respectively, and the buffers B1 and B1.
2 is output as signal outputs OUT1 and OUT2, that is, voltages Va and Vb. In the first half cycle of the clock CLK, the switches S11 and S12 are turned on, so the signal output OUT1 (voltage Va) from the buffer B1.
Is one terminal 1 of the capacitor C1 via the switch S11
Join 8 In addition, the output signal OUT2 from the buffer B2
(Voltage Vb) is supplied to the capacitor C via the switch S12.
1 to the other terminal 19 of 1. Therefore, the switches S3,
When S6 is on, in the first half cycle of the clock,
The capacitor C1 has a signal output OUT1 and an output signal OU.
A difference from T2, that is, a potential difference Vs (= Vb-Va) is added.

In the next half cycle of the clock, the switch S
3, S6, S11, S12 are turned off, and switch S
7, S8, S13 and S20 are turned on. As a result, the photoelectric conversion circuit 3 and the correction photoelectric conversion circuit 4 have the common signal line C
Separated from M1 and CM2, each common signal line C
M1 and CM2 are reset to "0" V by switches S7 and S8. At the same time, the capacitor C1
Is also disconnected from the common signal lines CM1 and CM2, the DC voltage V3 is applied to one terminal 18 of the capacitor C1 via the switch S13, and the other terminal 19 of the capacitor C1 is buffered via the switch S20. It is connected to B3. As a result, the other terminal 19 of the capacitor C1 has a voltage difference (V3-V
s) is output, and this voltage (V3-Vs) is impedance-converted by the buffer B3 to output the signal OU.
It is finally output as T3.

In this way, the operation of the 1st bit photoelectric conversion unit U1 is performed, and the 1st bit signal output OU
After T3 is output, the operations of the photoelectric conversion units U2 to Un of the 2nd bit to the nth bit are sequentially performed by the same procedure, and the signal output OUT3 of the 2nd bit to the nth bit is sequentially output. . By the way, the above voltage (V
3-Vs), the voltage difference Vs is equal to the signal output OUT1.
Is the voltage difference between the signal output OUT2 and the signal output OUT2, which is the signal output OUT1 from the photoelectric conversion circuit 3 in which the offset voltage is superimposed on the pure optical signal component, as described in the first embodiment.
The offset voltage is almost removed from the signal, and only the pure optical signal component is extracted. Therefore, the final signal output OUT3 output from the buffer B3 has very little variation in offset voltage, and is a signal obtained by superimposing a constant offset voltage V3 on a substantially pure optical signal component, and for each bit of the offset voltage. It is possible to obtain the signal output OUT3 having a very small variation. The offset voltage V3 can be set arbitrarily, which facilitates connection with the next stage.

Further, the output of the photoelectric conversion circuit 3 is positive type (the output voltage becomes larger with respect to the ground level as the input light becomes larger), but the signal output is negative type (the output voltage becomes the ground level). Becomes smaller)
By converting to, it is possible to make it difficult to be restricted by the power supply voltage and the like.

As described above, in the photoelectric conversion device of the second embodiment, the same effect as in the first embodiment can be obtained, and the signal output O of the photoelectric conversion circuit 3 is provided inside the device.
Since the offset voltage for the UT1 is configured to be corrected, an external differential amplification process is unnecessary, and an output signal set to an arbitrary DC voltage level can be obtained, so that the next stage Can be easily connected, and the load of the power supply voltage can be reduced.

FIG. 6 is a block diagram of a third embodiment of the photoelectric conversion device according to the present invention. The photoelectric conversion device shown in FIG. 6 includes a correction photoelectric conversion circuit 4a, photoelectric conversion circuits 3 _{1 to} 3 ₁₀₀₀ for the _{1st to} 1000th bits, and 1001st photoelectric conversion circuits.
Photoelectric conversion circuit 3 from bit to 2000th bit
And ₁₀₀₁ to 3 _2000, the photoelectric conversion circuit 3 ₂₀₀₁ to 3 ₃₀₀₀ up to the 2001-th bit to 3000 bit, a correction for the photoelectric conversion circuit 4b is the same control signal and the above-mentioned from the timing generating circuit 11 CTL ( 5, 6, 7) are sequentially controlled, and these output signals are controlled by the common signal line CM.
3 are sequentially output.

That is, each correction photoelectric conversion circuit 4a, 4
b has the same configuration as the correction photoelectric conversion circuit 4 shown in FIG. 2, and the switches S4, S5, S6 are on / off controlled by control signals 5, 6, 7 from the timing generation circuit 11, respectively. , When switch S6 is on,
The output signal is output to the common signal line CM3. Further, each of the photoelectric conversion circuits 3 _{1 to} 3 ₃₀₀₀ has the same configuration as that of the photoelectric conversion circuit 3 shown in FIG. 2, and the switches S1, S2, S3 have the control signals 5, 6, 6 from the timing generation circuit 11. On / off control is performed by 7 respectively, and an output signal is output to the common signal line CM3 when the switch S3 is on. However, in the photoelectric conversion device of FIG. 6, the correction photoelectric conversion circuits 4a and 4a
b are arranged at both ends of the photoelectric conversion circuit groups 3 _{1 to} 3 ₃₀₀₀ , respectively.

Further, the common signal line CM3 is on / off controlled by a control signal CTLR from the timing generation circuit 11, and a switch S18 for initializing the common signal line CM3 and a switch S18 when the switch S18 is on. A buffer B4 for impedance-converting and amplifying the output signal output to the common signal line CM3 is provided, and the output signal from the buffer B4 is further amplified by the buffer B5 and output as the signal output OUT5. Has become.

A first charging circuit 104 and a second charging circuit 105 are connected to the signal line 103 from the buffer B4. The first charging circuit 104 includes the switch S14 and the signal line 103 when the switch S14 is on.
A capacitor C2 that charges the output signal above, a buffer B6 that amplifies the voltage of the capacitor C2, and a switch S16.
And the second charging circuit 105 has a switch S
15, a capacitor C3 that charges an output signal on the signal line 103 when the switch S15 is on, and a capacitor C3.
It has a buffer B7 for amplifying the voltage of 3 and a switch S17.

Here, the switch S14 is on / off controlled by a control signal 7 from the timing generation circuit 11 applied to the correction photoelectric conversion circuit 4a.
That is, when the output signal from the correction photoelectric conversion circuit 4a is output to the common signal line CM3, the switch S14 is turned on. Also, switch S15
Is controlled to be turned on / off by a control signal 7 from the timing generation circuit 11 applied to the correction photoelectric conversion circuit 4b. That is, the correction photoelectric conversion circuit 4b
The switch S15 is turned on when the output signal from the output terminal is output to the common signal line CM3.

Further, in the apparatus of FIG. 6, the switches S16,
Control signals 27 and 28 for controlling on / off of S17
Is provided with a controller 107 for generating
Reference numeral 16 denotes an ON state when an output signal is output from the _{1st to} 2000th bit photoelectric conversion circuits 3 _{1 to} 3 _{2000, and} from the 2001th to 3000th bit photoelectric conversion circuits 3 _{2001 to} 3 _3000. When the output signal is being output, it is controlled to be off, and the switch S17 is
1st to 1000th bit photoelectric conversion circuit 3
OFF when the output signal is output from _{1 to} 3 ₁₀₀₀ , 3 _{1001 from} the 1001st bit to the 3000th bit
When the output signal is output from 3 to _3000, it is controlled to be turned on.

Further, the output voltage from the first charging circuit 104 and the output voltage from the second charging circuit 105 are averaged,
Averaging circuit 108 for making this the corrected output OUT6
Is provided.

Next, the operation of the photoelectric conversion device having such a configuration will be described with reference to the time chart of FIG. In the photoelectric conversion device of FIG. 6, when the start pulse ST is applied to the timing generation circuit 11, the switch S18 is turned on by the control signal CTLR and the common signal line CM3 is initialized. After that, the switch S18 is turned off, and the correction photoelectric conversion circuit 4a and the photoelectric conversion circuits 3 _{1 to} 3 are generated by the control signals (5, 6, 7) from the timing generation circuit 11.
₃₀₀₀ and the correction photoelectric conversion circuit 4b sequentially operate, and these output signals are sequentially output to the common signal line CM3, impedance-converted by the buffers B4 and B5, amplified, and output as the output signal OUT5. . At this time, the output signal from the buffer B4 is the first charging circuit 1
04, added to the second charging circuit 105.

That is, first, the switches S14 and S1
5, S16 and S17 are off, the output signal from the correction photoelectric conversion circuit 4a is output to the common signal line CM3,
When the impedance is converted by the buffer B4 and output, the output is charged in the capacitor C2 by turning on the switch S14 by the control signal 7 from the timing generation circuit 11. Next, when the photoelectric conversion result of the first bit (photoelectric conversion circuit 3 ₁ ) is output to the common signal line CM3, the switch S14 is turned off and the capacitor C2
Voltage is held. Further, the switch S16 is turned on by the control signal 27 from the control unit 107, and the hold voltage of the capacitor C2 is output to the averaging circuit 108. Subsequently, the photoelectric conversion result after the second bit (photoelectric conversion circuit 3 ₂ ) is sequentially output, but the state of the switches S16 and S17 is the photoelectric conversion result at the 1000th bit (photoelectric conversion circuit 3 ₁₀₀₀ ). Does not change.
That is, the switch 16 remains on, and the switch S17 remains off until the 1000th bit. Therefore, from the averaging circuit 108, the hold voltage of the capacitor C2, that is, the offset voltage from the correction photoelectric conversion circuit 4a is output from the averaging circuit 108 until the output from the 1st bit to the 1000th bit is output.
It is output as 6. Next, at the same time that the 1001st bit (photoelectric conversion circuit 3 ₁₀₀₁ ) is output, the control unit 107
The control signal 28 from turns on the switch S17. The switch S16 remains on. Next, the 1002nd bit (photoelectric conversion circuit 3 ₁₀₀₂ )
Subsequent photoelectric conversion results are sequentially output. At this time,
The states of the switches S16 and S17 do not change until the 2000th bit (photoelectric conversion circuit 3 ₂₀₀₀ ) photoelectric conversion result is output. That is, the switch S16 remains on until the 2000th bit, and the switch S17 also remains on. Therefore, from the 1001st bit to the 2000th bit, the average voltage of the capacitors C2 and C3 is output from the averaging circuit 108 as the correction output O.
It is output as UT6. However, since the voltage of the capacitor C3 is 0 V only for the first scan, the correction output O
UT6 has 1 of the voltage held in the capacitor C2.
A voltage of / 2 will be output. The switch S16 turns off at the same time when the photoelectric conversion result of the 2001th bit (photoelectric conversion circuit 3 ₂₀₀₁ ) is output.
Remains on. Subsequently, the photoelectric conversion results after the 2002th bit (photoelectric conversion circuit 3 ₂₀₀₂ ) are sequentially output, but the state of the switches S16 and S17 is output at the 3000th bit (photoelectric conversion circuit 3 ₃₀₀₀ ) which is the final bit. Does not change until Therefore, the averaging circuit 108 outputs the hold voltage of the capacitor C3 as the correction output OUT6. However, as mentioned above,
Since the voltage of the capacitor C3 is 0V only for the first scan, 0V is output to the correction output OUT6. Then, finally, the output from the correction photoelectric conversion circuit 4b is output to the common signal line CM3. At this time, the switch S15 is turned on by the control signal 7 from the timing generation circuit 11, and the output voltage from the correction photoelectric conversion circuit 4b is impedance-converted by the buffer B4 and the capacitor C3.
Will be charged. With the above, the first scanning is completed. The second and subsequent scans are performed in the same manner as described above, but in the second and subsequent scans, the hold voltage of the capacitor C3 is the voltage of the correction photoelectric conversion circuit 4b obtained in the first scan.

As a result, in the second and subsequent scans, as shown in FIG. 7, the offset voltage of the correction photoelectric conversion circuit 4a is from the 1st to 1000th bits, 1001-2.
Up to the 000th bit, the average offset voltage between the correction photoelectric conversion circuit 4a and the correction photoelectric conversion circuit 4b, 2001 to
Up to the 3000th bit, the offset voltage of the correction photoelectric conversion circuit 4b and the correction output OUT6 for three blocks are obtained, and the correction output OUT6 is used to perform differential amplification with the signal output. As a result, the variation in offset voltage can be reduced.

At this time, the correction photoelectric conversion circuit 4a,
4b can use a portion that is generally provided in a photoelectric conversion device such as a CCD sensor and that does not perform photoelectric conversion (called optical black and is provided before and after the photoelectric conversion circuit). It is possible to reduce the variation in the offset voltage without increasing the scale (that is, reducing the load of post-treatment such as the memory for writing the correction data and the arithmetic processing circuit).

Further, in the above example, the case where the photoelectric conversion circuits for 3000 bits are provided has been described, but the present invention can be similarly applied to an arbitrary number of photoelectric conversion circuits.

[0037]

As described above, according to the first aspect of the invention, the signal output from the photoelectric conversion circuit is generated by the signal output from the correction photoelectric conversion circuit arranged near each photoelectric conversion circuit. Since it is configured to be able to correct, the circuit scale is prevented from increasing and the processing complexity is reduced, and
It is possible to reduce not only the variation in the offset voltage due to the difference in the device characteristics in manufacturing but also the variation in the offset voltage due to the temperature change and the like.

According to the inventions of claims 2 and 3,
The photoelectric conversion device according to claim 1, wherein a difference between a signal output from a certain photoelectric conversion circuit and a signal output from a correction photoelectric conversion circuit corresponding to the photoelectric conversion circuit is calculated, and this difference is set to an arbitrary constant value. Since the correction means for outputting the voltage on which the offset voltage is superimposed as the final output signal is further provided, the offset voltage can be corrected in this device, and the DC voltage level can be set to an arbitrary level. It is possible to obtain an excellent signal output, facilitate the connection with the next stage, and further reduce the burden on the power supply voltage.

According to the inventions of claims 4 and 5,
First and second correction photoelectric conversion circuits are arranged at both ends of the photoelectric conversion circuit group, respectively, and a plurality of offset voltages are generated based on the signal voltages from the first and second correction photoelectric conversion circuits. Is generated and is output as a correction output for the signal output from the plurality of photoelectric conversion circuits forming the photoelectric conversion circuit group, so that the circuit scale is increased and the processing is prevented from becoming complicated. Moreover, it is possible to reduce not only the variation in the offset voltage due to the difference in the device characteristics in manufacturing but also the variation in the offset voltage due to the temperature change and the like.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a photoelectric conversion device according to the present invention.

FIG. 2 is a diagram showing a configuration example of one photoelectric conversion unit of the photoelectric conversion device shown in FIG.

FIG. 3 is a time chart for explaining the operation of the photoelectric conversion device in FIG.

FIG. 4 is a configuration diagram of a second embodiment of the photoelectric conversion device according to the present invention.

5 is a time chart for explaining the operation of the photoelectric conversion device in FIG.

FIG. 6 is a diagram showing a third embodiment of the photoelectric conversion device according to the present invention.

FIG. 7 is a time chart for explaining the operation of the photoelectric conversion device in FIG.

FIG. 8 is a configuration diagram of a conventional photoelectric conversion device.

9 is a time chart for explaining the operation of the photoelectric conversion device in FIG.

[Explanation of symbols]

 U1 to Un Photoelectric conversion unit 3 Photoelectric conversion circuit 4, 4a, 4b Correction photoelectric conversion circuit 11 Timing generation circuit 103 Signal line 104 First charging circuit 105 Second charging circuit 107 Control unit 108 Averaging circuit CM1, CM2 CM3 Common signal line C1 Capacitor

Claims (5)

[Claims] 1. In a photoelectric conversion device having at least one photoelectric conversion circuit, each photoelectric conversion circuit has a photoelectric conversion element that generates a photocurrent according to the amount of incident light, and the photoelectric current from the photoelectric conversion element is converted into a photoelectric current. A photoelectric conversion circuit for correction is arranged in the vicinity of each photoelectric conversion circuit so as to correspond to the photoelectric conversion circuit, and each correction photoelectric conversion circuit corresponds to the corresponding photoelectric conversion circuit. A photoelectric conversion device having the same configuration as a photoelectric conversion circuit, but the photoelectric conversion element is shielded from light, and an offset voltage is output as a signal output. 2. The photoelectric conversion device according to claim 1,
The difference between the signal output from a certain photoelectric conversion circuit and the signal output from the correction photoelectric conversion circuit corresponding to the photoelectric conversion circuit is calculated, and a voltage obtained by superimposing an arbitrary constant offset voltage on this difference is finally determined. The photoelectric conversion device is further provided with a correction means for outputting as a different output signal. 3. The photoelectric conversion device according to claim 2,
The correction means has a capacitor, a signal output from a certain photoelectric conversion circuit is added to one terminal of the capacitor, and the other terminal of the capacitor corresponds to the photoelectric conversion circuit. The signal output from the correction photoelectric conversion circuit is added, and when reading the final output signal, an arbitrary offset voltage is applied to one or the other terminal of the capacitor, and the other or one terminal of the capacitor is added. The photoelectric conversion device is characterized in that the voltage of is read out as a final output signal. 4. A photoelectric conversion device having a photoelectric conversion circuit group composed of a plurality of photoelectric conversion circuits, wherein the plurality of photoelectric conversion circuits constituting the photoelectric conversion circuit group operate in sequence and a photocurrent corresponding to an amount of incident light. The signal output based on the above is sequentially output, and the first and second correction photoelectric conversion circuits are arranged at both ends of the photoelectric conversion circuit group, respectively. On the basis of the signal voltage from the correction photoelectric conversion circuit, a plurality of offset voltages are generated, and this is output as a correction output for the signal output from the plurality of photoelectric conversion circuits forming the photoelectric conversion circuit group. A photoelectric conversion device characterized in that 5. The photoelectric conversion device according to claim 4,
The plurality of offset voltages include a first offset voltage output from the first correction photoelectric conversion circuit and a second offset voltage.
The second offset voltage output from the correction photoelectric conversion circuit of, and the third offset voltage obtained by averaging the first offset voltage and the second offset voltage are used,
The photoelectric conversion circuit group is functionally divided into first, second, and third blocks from the first correction photoelectric conversion circuit toward the second correction photoelectric conversion circuit, and the first, second, and third blocks are provided. The photoelectric conversion device is configured to output the first, second, and third offset voltages as correction outputs for the output signals from the photoelectric conversion circuits belonging to the block.