JPH0685608A - Stack filter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by performing the analysis processing with the data value included in a window used as the threshold value and then outputting the maximum threshold value with which the binary filter output is set at '1'. CONSTITUTION:A serial/parallel converter means 1 converts (n) pieces of serial data included in the input signal (n>=3). Then two pieces of different data of nC2 sets are compared with each other by nC2 pieces of comparators 3. Then a decision signal is outputted. Then (n) pieces of vectors consisting of the binary data are obtained by (n) pieces of vector generator means 4 based on the decision signal. Meanwhile (n) pieces of binary filters 5 applies an arithmetic operation to each vector in the Boolean algebra, and a minimum value detector 6 detects the minimum one of those vectors having the operational results of '1' to detect a detection signal. Then a selector means 7 selects one of (n) pieces of data, i. e., the output of the means 1 based on the detection signal. In such a constitution, the circuit scale can be reduced for a stack filter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a television or V
The present invention relates to a non-linear filter used for the purpose of noise reduction in a video device such as a TR or a video camera, particularly a stack filter.

[0002]

2. Description of the Related Art In recent years, a stack filter, which is a new processing mode of a non-linear digital filter represented by a median filter, has been proposed (for example, IEEE Trans.Acoust., Speech, Signal).
Process. ASSP-34, 898-911, 1986).

The process of the stack filter will be briefly described below. Here, as an example, a process will be described in which the characteristics of a median filter are realized by a stack filter having a window width (the number of pieces of data to be processed) of 3. Figure 5
FIG. 3 is a block diagram showing the basic configuration of a stack filter. The outline of the processing is shown in FIGS. 6 and 7.

First, an outline of the process of the stack filter will be described with reference to FIGS. 6 and 7. In the figure, the processing by the conventional median filter is shown along the path of the thick arrow in the figure.

In the conventional processing, a data string (here, 2-bit data) shown as an input in the upper left portion of FIG.
The data string passes through the median filter shown at the top and is shown as an output in the upper right part. Since the window width of this filter is 3, it outputs the second largest value for the three input data.

When this process is performed by the stack filter, the process is performed along the path indicated by the thin arrow in the figure.

First, since the input data string is 2 bits, the possible values of the data are 4 levels. Of these, input data values are observed at each level except 0, and a 1-bit data string is created with the observed level as a threshold.
The reason for excluding 0 is that even if this processing is performed at level 0, the resulting data string is all "1" and has no information.

This will be described with reference to FIG. When data with values of 1, 3, and 2 are input as shown in the figure, first, with the level of 1 as the threshold, "1" if the value of the input data is above the threshold, and "0" if it is less than the threshold. Data string (1,1,1) by the process
To get Similarly, the data string (0,1,1) is obtained with the level of 2 as the threshold, and the data string (0,1,0) is obtained with the level of 3 as the threshold. Hereinafter, this process is referred to as a disassembly process.

The three kinds of data strings decomposed into 1 bit on each level as described above are respectively passed through a binary filter represented by Boolean algebra as shown in FIG. 6 to obtain a 1-bit output data string. Here, since the median filter is configured, the transfer function of the binary filter has three input data x ₁ and x ₁ in order from the oldest one in terms of time.
₂ and x ₃ ,

[0010]

[Equation 1]

[0011] In the above formula, “·” is the logical product,
"+" Represents a logical sum. The stack filter thus simplifies the filter transfer function.

In the conventional median filter, since the sorting process for rearranging the data in the descending order is required, the circuit must be complicated. However, if the stack filter process is performed, the transfer function is realized by hardware. Will be easier.

Finally, a 2-bit output data string is obtained by adding all the outputs of the binary filters. Hereinafter, this process is called a combining process. The result is equal to the result of the path along the thick arrow in the figure.

The above is the processing method by the stack filter, but in order to perform this processing, it is necessary that the transfer function of the binary filter satisfies a certain condition. Next, this point will be described.

As shown in FIG. 6, the input data is divided into a plurality of 1-bit data strings by the decomposition processing in the stack filter. Focusing on the data of the decomposition results at the same time (vertical direction in the figure), a bar graph It is possible to find the property that the column of “0” exists on the column of “1” as shown in FIG. For example, when the input data value is 2, the decomposition result is lined with "1" up to level 2 and is "0" at level 3.

This is a natural result, but it should be noted that this property must also be maintained at the output of the binary filter.

To simplify the explanation, this is expressed by a mathematical expression.
To do. Input data string z₁, z₂, ・ ・ ・, Z _nDifferent for 2
One level L₁And L₂The result of the above decomposition,

[0018]

[Equation 2]

And

[0020]

[Equation 3]

[0021] Now, for all k where 1 ≦ k ≦ n,

[0022]

[Equation 4]

When is satisfied,

[0024]

[Equation 5]

It will be expressed as follows. Using this, the above mentioned properties are

[0026]

[Equation 6]

It can be expressed as Where vina
The transfer function of the refilter is S_(・)And the output is S_(x)Oh
And S _(y)Expressed as S_(x)And S_(y)Do not hold between
The properties that must be

[0028]

[Equation 7]

Therefore, the following conditions are derived from (Equation 6) and (Equation 7).

[0030]

[Equation 8]

After all, the transfer function S _{(.) Of the} binary filter
It means that the condition necessary for (4) is only required to satisfy (Equation 8). The transfer function with such properties is
It is known that none of the product terms include negation.

If the above processing is performed faithfully, a hardware configuration as shown in FIG. 5 is required.

FIG. 5 is a block diagram showing the configuration when the input data is 8-bit data.

The serial-parallel conversion means 1 synchronizes the three pieces of data inputted from the input terminal 8. Vector generation means 4
-1 to 4-255 perform decomposition processing on the output of the serial-parallel conversion unit 1 at each level from 1 to 255, and have a length of 3
To generate a 1-bit data string. This can be regarded as a three-dimensional vector having binary elements.

The binary filters 5-1 to 5-255 perform the arithmetic operations shown in, for example, (Equation 1) on the output vectors of the vector generating means 4-1 to 4-255, respectively.

The adder 19 performs synthesis processing on the output values of all binary filters to obtain outputs.

[0037]

However, in the above method, the above-mentioned decomposition and synthesis processing is not so problematic if the input data is 2 to 3 bits, but as in the case of FIG. For data, 255 vector generating means and binary filters are required, which is unrealistic.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a stack filter that performs a practical decomposition / synthesis process.

[0039]

In order to achieve this object, a stack filter of the present invention comprises a serial / parallel conversion means for converting n (n ≧ 3) serial data from an input signal into parallel data. Of the n outputs of the serial-parallel conversion means,
_N C ₂ large and small comparators that generate comparison signals by taking out two different ones and compare them, and n pieces that generate a vector composed of binary elements from each output of the large and small comparators Between the vector generation means and each element of each vector output from the n number of vector generation means, n number of filter means for performing a process represented by Boolean algebra and n number of filter means outputs are predetermined. And a minimum value detector for detecting a vector having the smallest magnitude among the n vectors output from the n vector generating means, and outputting a detection signal, One of the n outputs of the serial-parallel conversion means corresponding to the output of the value detector
It has a configuration of selecting means for selecting and outputting the individual outputs.

[0040]

According to the present invention, with the above-described configuration, the magnitude comparison is performed between two different data, the minimum required binary data sequence is obtained using the result, and these data sequences are passed through the binary filter. After that, of the output values of the binary filter that are 1, the decomposition level that generates the data string with the maximum number of 0s is obtained and output.

[0041]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a stack filter having a window width of 3 according to the first embodiment of the present invention.

First, the concept of the decomposition process in the present invention will be described first. Now, since the window width is 3, consider the input data as shown in FIG. The data are x ₁ , x ₂ , and x ₃ from the oldest in time, and the values are m ₁ , m ₂ , and m ₃ , respectively. However,

[0044]

[Equation 9]

It is Now, if this data string is decomposed on an arbitrary level L (1≤L≤255), 1 is obtained.
The bit data string is as follows.

[0046]

[Equation 10]

That is, no matter how many bits the input data has, when the window width is 3, there are at most four types of data strings obtained as a result of the decomposition. In addition, since the first data string (0,0,0) is not required in the synthesizing process as described above, only three types of data strings need to be processed. Therefore, three binary filters are sufficient.

Next, the processing for obtaining the above three types of data strings will be described. Looking at the point where the data string changes by changing L from 1 to 255, it is between m ₁ and m ₁ +1, between m ₂ and m ₂ +1 and between m ₃ and m ₃ +1. This is level m
It means that all necessary data strings can be obtained by performing the decomposition on ₁ , m ₂ and m ₃ . That is, 3 input
It is only necessary to create a data string with each data value as a threshold.

This will be specifically described with reference to FIG. The data input from the input terminal 8 becomes _three parallel data x ₁ , x ₂ , x _{3 in the} serial-parallel converter 1.

The first magnitude comparator 3a compares the magnitudes of x ₁ and x ₂ , and compares x ₁ with the threshold level (“1” if x ₂ ≧ x ₁ and x ₂ <x ₁ If present, "0") is output to the first vector generation means 4a as a ₁₂ , and at the same time, the comparison result a _{21 in} which x ₂ is the threshold level is output to the second vector generation means 4b.

Similarly, the second magnitude comparator 3b compares the magnitudes of x ₁ and x ₃ , and the comparison result a _{13 in} which x ₁ is the threshold level is sent to the first vector generating means 4a and x ₃ is turned to the threshold level. The comparison result a ₃₁ is output to the third vector generating means 4c.

Similarly, the third magnitude comparator 3c compares the magnitudes of x ₂ and x ₃ , and the comparison result a _{23 in} which x ₂ is the threshold level is sent to the second vector generating means 4b and x ₃ is turned to the threshold level. And outputs the comparison result a ₃₂ to the third vector generation means 4c.

In the first vector generating means 4a, the outputs a ₁₂ and a _{13 of} the first and second magnitude comparators 3a and 3b are used.
Then, a three-element vector is generated.

When the above operation is applied when the data shown in FIG. 2 is input, both x ₂ and x ₃ are x ₁
Since they are larger, both a ₁₂ and a ₁₃ are “1”.

Now, suppose that the above magnitude comparison is performed on x ₁ and x ₁ and the result is represented by a _11.
Since ₁₁ is naturally "1", vector generated _{(a 11, a 1 2,} a 13) is

[0056]

[Equation 11]

It becomes This is the decomposition result on level m ₁ . The generated vector is output to the first binary filter 5a and the minimum value detector 6.

[0058] Similarly, in the second and third vector generation means 4b and 4c, respectively Level m ₂ on the decomposition result _{(a 21, a 22, a} 23) and m ₃ on the decomposition result (a _31, a ₃₂ , a ₃₃ )

[0059]

[Equation 12]

To obtain These vectors are also second
And to the third binary filters 5b and 5c, and at the same time, to the minimum value detector 6.

First to third binary filters 5a to 5c
In, the arithmetic processing represented by 1-bit logical sum is performed. A specific example of the binary filter having the transfer function of (Equation 1) is as shown in FIG. This will be explained in a little more detail. For example, by substituting (a ₁₁ , a ₁₂ , a ₁₃ ) into (Equation 1), a ₁₁ is “1” as described above,

[0062]

[Equation 13]

Therefore, only the OR circuit 11-1 can be used. Similarly, (a ₂₁ , a ₂₂ , a ₂₃ ) and (a ₃₁ , a ₃₂ ,
a ₃₃ ), OR circuits 11-2 and 11 respectively.
It can consist of only -3.

If the transfer function of the binary filter is a median filter as shown in (Equation 1), the output values S _{1 to} S ₃ of the _first to third binary filters 5a to 5c are

[0065]

[Equation 14]

It becomes Considering (Equation 10) here,
It can be seen that the output value of the binary filter is 0 for a data string decomposed on an arbitrary level L such that m ₂ <L ≦ 255 and m ₃ <L ≦ m _2, so that between the decomposition level L and the filter output. The following formula is established.

[0067]

[Equation 15]

This is supported by (Equation 8). The output of each binary filter is output to the minimum value detector 6.

In the minimum value detector 6, among the output vectors of the first to third vector generating means 4a to 4c, the output values of the first to third binary filters 5a to 5c are "1". Detects the smallest size and outputs the detection signal to the selecting means 7. The algorithm will be described here. In the original method, all the output values of the binary filter are added and output. Therefore, in this case, the sum of m ₃ “1” s from level 1 to m ₃ , that is, m ₃ is the combined result. Become. Since m ₁ <m ₃ <m ₂ , it can be seen that this stack filter operates as a median filter.

However, paying attention to (Equation 15), in order to obtain the combined result, the maximum decomposition level (m _{3 in this} case) that gives a data string in which the output result of the binary filter is “1” is given. You know that you can ask.

A method of obtaining this level will be described below. First, all the data strings in which the output of the binary filter is "1" are obtained. In this case (0,1,1) and (1,1 ,,
1).

If the maximum number of "0" s is obtained, the decomposition level that gives the data string becomes the required level. In the present case, the maximum number of "0" is (0,1,1), so the decomposition level that gives this is m
It becomes ₃ .

Since m ₃ is the value of the input data x ₃ , a synthetic output can be obtained by using x ₃ itself as an output value.

The above algorithm is organized and rewritten.
The data strings on the decomposition levels m ₁ , m ₂ , and m ₃ are y ₁ ,
y ₂ , y ₃ , that is,

[0075]

[Equation 16]

It is expressed as Further, representative of the output value of the binary filter for the y _1, y _2, y ₃ and S _1, S _2, S _3, respectively. At this time, (a) First, if S ₁ = 1, the provisional output value is set to x ₁ . S ₁
If = 0, x ₁ is excluded from the output value candidates.

(B) Next, if S ₂ = 1 then y ₁ and y ₂ are compared, and if y ₂ has more “0” s, the provisional output value is x ₂
And If S ₂ = 0, x ₂ is excluded from the output value candidates.

(C) Further, if S ₃ = 1 then y ₁ and y ₃ or y ₂ and y ₃ are compared, and if y ₃ has more “0” s, the provisional output value is set to x ₃ . . If S ₃ = 0, x ₃ is excluded from the output value candidates.

(D) The final provisional output value is output from the processing results of (a) to (c). Based on the above algorithm, one of the three outputs of the serial-parallel converter 1 is selected by the selection means 7, and the output terminal 9 is selected.
Output to.

A concrete circuit for realizing the above algorithm is shown in FIG. The output signal S _{1 of} the first binary filter 5a is input to the NAND circuit 12, and when S ₁ = 1 the values of S ₂ and S ₃ are continuously checked. If S ₂ = 1 then y ₁ and y ₂
And if S ₃ = 1 then y ₁ and y ₃ are compared.

As described in the explanation of the decomposition processing, for example, between y ₁ and y ₂ ,

[0082]

[Equation 17]

Since the above relation holds, the condition to be satisfied when the number of “0” s in y ₂ is larger than that in y ₁ is:

[0084]

[Equation 18]

It is However, considering that a ₁₁ and a ₂₂ are always “1”, the second condition of the above equation does not hold, so

[0086]

[Formula 19]

It can be simplified as follows. This condition is AND circuit 10
−1 and the OR circuit 11-4. Therefore, S
If (Equation 19) is satisfied with ₂ = 1, the AND circuit 10-4 outputs "H".

Similarly, in comparing y ₁ and y ₃ ,

[0089]

[Equation 20]

If the condition is satisfied, the number of "0" s in y ₃ is larger than that in y ₁ . This condition is AND circuit 1
0-2 and OR circuit 11-5. Therefore,
If S ₃ = 1 in equation (20) is satisfied, the AND circuit 10-5 outputs the "H".

S ₁ = 1 and AND circuits 10-4 and 1
0-5 NAND circuit 12 when the output is "L" of the outputs "L", the switching selection means 7-1 to the "L" side, and selects and outputs the x _1.

When S ₁ = 0 or when the output of the AND circuit 10-4 or 10-5 is "H", the NAND circuit 12 outputs "H", and the selecting means 7-1 is set to the "H" side. Switch to
Remove x ₁ from the output value candidates.

The case where x ₁ is out of the output value candidates will be described below. First, if S ₂ = 1, the value of S ₃ is checked in the same manner, and S ₃ =
If 1, then y ₂ and y ₃ are compared.

[0094]

[Equation 21]

If the condition is satisfied, the number of "0" s in y ₃ is larger than that in y ₂ . This condition is AND circuit 1
0-3 and OR circuit 11-6. Therefore,
If S ₃ = 1 in (Equation 21) is satisfied, the AND circuit 10-6 outputs the "H".

When S ₂ = 1 and the output of the AND circuit 10-6 is "L", the NAND circuit 13 outputs "L" and switches the selecting means 7-2 to the "L" side, x ₂ To output.

When S ₂ = 0 or the output of the AND circuit 10-6 is "H", the NAND circuit 13 outputs "H", switches the selecting means 7-2 to the "H" side, and x ₃ is set. Select and output.

As a result, among the outputs of the first to third vector generating means, the vector having the maximum number of 0's is detected among the vectors in which the output value of the binary filter is "1", and the vector is generated. You can ask the level.

As described above, in the present invention as shown in the embodiment,
Even for 8-bit data and the like, the stack filter can be configured with a relatively small amount of hardware.

In the present embodiment, the median filter is taken as an example, and the transfer function of the binary filter is set as in (Equation 1). However, when realizing another characteristic, as described in the section of the conventional example. If the expression does not include negation in any product term,
The above discussion holds as well.

[0101]

As described above, according to the present invention, the serial / parallel conversion means, the _n C ₂ magnitude comparators, the n vector generation means, the n filter means, the minimum value detector, It is equipped with a selection means and compares two different data,
After obtaining the minimum required binary data string using the result and passing these data strings through the binary filter, the data string with the maximum number of 0 is generated among the output values of the binary filter being 1. By obtaining and outputting the decomposition level of the stack filter, a stack filter with a relatively small-scale hardware can be realized, and its implementation effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a stack filter according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining the processing in FIG.

FIG. 3 is a logic circuit diagram showing an example of the binary filter in FIG.

FIG. 4 is a block diagram showing an example of a synthesis processing circuit.

FIG. 5 is a block diagram showing a configuration of a conventional stack filter.

FIG. 6 is a schematic diagram showing an outline of processing of a conventional stack filter.

FIG. 7 is a schematic diagram for explaining the concept of disassembly processing in a conventional stack filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial / parallel conversion means 3 Large / small comparator 4 Vector generation means 5 Binary filter 6 Minimum value detector 7 Selection means

Claims (3)

[Claims] 1. A serial-parallel conversion means for converting n (n ≧ 3) serial data into parallel data from an input signal, and two different outputs out of n outputs of the serial-parallel conversion means. _N C ₂ large and small comparators for comparing the magnitudes to generate comparison signals, and n vector generating means for generating a vector composed of binary elements from each output of the large and small comparators, Between each element of each vector output from the n number of vector generation means, n number of filter means for performing a process represented by Boolean algebra, and a condition of the n number of filter means outputs being a predetermined value A minimum value detector for detecting the smallest one of the n vectors which is the output of the n vector generating means and outputting a detection signal, and an output of the minimum value detector. Correspondingly, n of the serial-parallel conversion means A stack filter, comprising: selecting means for selecting and outputting one of the outputs, and using the output of the selecting means as an output signal. 2. The stack filter according to claim 1, wherein the filter means is a binary median filter whose transfer function has the characteristics of a median filter. 3. The stack filter according to claim 1, wherein the filter means is a binary asymmetric median filter whose transfer function has the characteristics of an asymmetric median filter.