JPH0685414A - Printed wiring board for mounting semiconductor device - Google Patents

Printed wiring board for mounting semiconductor device

Info

Publication number
JPH0685414A
JPH0685414A JP23376792A JP23376792A JPH0685414A JP H0685414 A JPH0685414 A JP H0685414A JP 23376792 A JP23376792 A JP 23376792A JP 23376792 A JP23376792 A JP 23376792A JP H0685414 A JPH0685414 A JP H0685414A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
linear expansion
semiconductor device
expansion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23376792A
Other languages
Japanese (ja)
Inventor
Keiji Nagamatsu
啓至 永松
Kaname Iwasaki
要 岩崎
Mitsutoshi Sano
光俊 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Plastics Inc
Original Assignee
Mitsubishi Plastics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Plastics Inc filed Critical Mitsubishi Plastics Inc
Priority to JP23376792A priority Critical patent/JPH0685414A/en
Publication of JPH0685414A publication Critical patent/JPH0685414A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a printed wiring board suitable for the wiring board used for the surface mounting with which a semiconductor device can be mounted in the state of high density. CONSTITUTION:The printed wiring board consists of an iron-nickel alloy plate on which copper is clad on both surfaces, and the printed wiring board is formed by laminating metal foil and an insulating layer, consisting of heat-proof thermoplastic resin having Young's modules (ASTMD-882) of 200 to 800kg/mm<2>, at least on one side of a metal plate having the linear expansion coefficient (ASTMD-696) of 6X10<-6>mm/mm deg.C or lower. This is the printed wiring board used for mounting of a semiconductor device having the thickness of an insulating layer of 20 to 200mum, the linear expansion coefficient of the entire laminated board of 2X10<-6> to 8X10<-6>mm/mm deg.C. As a result, cracks and the like are hardly generated on the connection part even when a hot-cold cycle is added, and a layer type semiconductor device can be surface-mounted in the state of high density. As a result, this printed wiring board has a high utilizational efficiency for the printed wiring board and the like used for motorcar control device of wide range of working temperature.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、特に大型の半導体素子
を高密度に実装することができる表面実装用の配線板に
適したプリント配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board suitable for a surface mounting wiring board capable of mounting large-sized semiconductor elements at high density.

【0002】[0002]

【従来技術とその課題】プリント配線板は回路形成や半
導体素子を実装する目的で、種々の電子機器等に供給さ
れている。近年、高密度実装のためにリードのないチッ
プ型の半導体素子をプリント配線板上の所定回路位置に
直接ハンダ付けを行ないハンダ部で両者を接合するいわ
ゆる表面実装用の配線板の開発が取り進められている。
2. Description of the Related Art Printed wiring boards are supplied to various electronic devices for the purpose of forming circuits and mounting semiconductor elements. In recent years, the development of so-called surface mount wiring boards, in which lead-free chip type semiconductor elements are directly soldered to predetermined circuit positions on the printed wiring board for high-density mounting and the two are joined at the solder part Has been.

【0003】しかしながら、上記半導体素子が表面実装
されたプリント配線板に冷熱の温度サイクルが加わる
と、半導体素子と配線板との間のハンダ付けした接続部
分にクラックが発生し、導通不良や素子が配線板から剥
離しやすいという問題があり、特に自動車の制御装置用
プリント配線板等の動作温度が広い用途で問題が生じ易
かった。このようなクラックの発生に対する対策として
は、配線板の熱膨張率を半導体素子のものにできるだけ
近ずけることが検討されているが、単に線膨張率を近ず
けるだけでは両者の接続部分でのクラックの発生を防止
するという効果が少なかった。特に高機能化に伴ない実
装する半導体素子が大型化(5〜10mm角程度)する
に従って、半導体素子自体の発熱が大きくなり、クラッ
クの発生が起こりやすい傾向にある。
However, when a cold temperature cycle is applied to a printed wiring board on which the above-mentioned semiconductor element is surface-mounted, cracks occur at the soldered connection portion between the semiconductor element and the wiring board, leading to defective conduction and the element. There is a problem that it is easily peeled off from the wiring board, and the problem is likely to occur particularly in applications having a wide operating temperature such as a printed wiring board for a control device of an automobile. As a countermeasure against such cracks, it has been considered to make the thermal expansion coefficient of the wiring board as close as possible to that of the semiconductor element. The effect of preventing the occurrence of cracks was small. In particular, as a semiconductor element to be mounted becomes larger (about 5 to 10 mm square) with higher functionality, heat generation of the semiconductor element itself increases and cracks tend to occur.

【0004】[0004]

【課題を解決するための手段】本発明は、上記問題点を
解消し大型の半導体素子を実装できるプリント配線板を
見い出したものであって、その要旨とするところは、両
面に銅を被覆してなる鉄ーニッケル合金板からなり、線
膨張率(ASTMD−696)が6×10-6mm/mm
℃以下である金属板の少なくとも片面に、線膨張率が3
×10-5〜8×10-5mm/mm℃で、かつヤング率
(ASTMD−882)が200〜800Kg/mm2
の範囲の耐熱性熱可塑性樹脂からなる絶縁層及び金属箔
を積層してなり、上記絶縁層の厚みが20〜200μm
の範囲であると共に積層板全体の線膨張率が2×10-6
〜8×10-6mm/mm℃の範囲である半導体素子実装
用プリント配線板に存する。
DISCLOSURE OF THE INVENTION The present invention has solved the above problems and has found a printed wiring board on which a large-sized semiconductor element can be mounted. The gist of the invention is to coat copper on both sides. Made of an iron-nickel alloy plate with a linear expansion coefficient (ASTM D-696) of 6 × 10 -6 mm / mm
The linear expansion coefficient is 3 on at least one side of the metal plate whose temperature is ℃ or less.
× 10 −5 to 8 × 10 −5 mm / mm ° C. and Young's modulus (ASTMD-882) of 200 to 800 Kg / mm 2
And an insulating layer made of a heat-resistant thermoplastic resin in the range of 10 and a metal foil are laminated, and the thickness of the insulating layer is 20 to 200 μm.
And the linear expansion coefficient of the whole laminated plate is 2 × 10 −6
It exists in the printed wiring board for mounting a semiconductor element in the range of up to 8 × 10 −6 mm / mm ° C.

【0005】本発明基板に用いる金属板は、線膨張率
(ASTMD−696)が6×10-6mm/mm℃以下
のものであり、具体的には、鉄−ニッケル合金(以下
「FeーNi合金」という)の表面に銅層を冶金的に被
覆したものを使用する。Fe−Ni合金の線膨張率は、
金属成分の含有比率によって異なり、本発明の線膨張率
を満足させるにはNi含有率が35〜45重量%のもの
がよい。また、上記合金に銅層を被覆したものは線膨張
率が若干大きくなるが、放熱性の向上が図れ、また銅層
を電源層やグランド層として利用できるという利点があ
る。
The metal plate used in the substrate of the present invention has a coefficient of linear expansion (ASTM D-696) of 6 × 10 -6 mm / mm ° C. or less. Specifically, it is an iron-nickel alloy (hereinafter referred to as “Fe- Ni alloy ”) having a copper layer metallurgically coated on its surface is used. The linear expansion coefficient of Fe-Ni alloy is
It depends on the content ratio of the metal component, and in order to satisfy the linear expansion coefficient of the present invention, the Ni content is preferably 35 to 45% by weight. Further, the above alloy coated with a copper layer has an advantage that the coefficient of linear expansion is slightly increased, but the heat dissipation is improved and the copper layer can be used as a power source layer or a ground layer.

【0006】上記の金属板としては必要に応じて複数の
貫通孔を設けたものも使用できる。つぎに金属板の片面
又は両面には絶縁層を被覆するが、この絶縁層に使用す
る耐熱性熱可塑性樹脂としては、線膨張率(ASTMD
−696)が3×10-5〜8×10-5mm/mm℃で、
かつヤング率(ASTMD−882)が200〜800
Kg/mm2 の範囲を満足するものを使用する必要があ
る。
As the above-mentioned metal plate, a plate provided with a plurality of through holes can be used if necessary. Next, one side or both sides of the metal plate is coated with an insulating layer. As the heat resistant thermoplastic resin used for this insulating layer, the linear expansion coefficient (ASTMD
-696) is 3 × 10 −5 to 8 × 10 −5 mm / mm ° C.,
And Young's modulus (ASTMD-882) is 200-800
It is necessary to use those satisfying the range of Kg / mm 2 .

【0007】この絶縁層が冷熱温度サイクル時に部品と
基板間の線膨張率の差によるせん断応力等を吸収する役
割をするものと考えられる。
It is considered that this insulating layer plays a role of absorbing shear stress and the like due to the difference in linear expansion coefficient between the component and the substrate during the cooling / heating temperature cycle.

【0008】上記樹脂層に使用する具体的な樹脂として
は、ポリフェニレンサルファイド、ポリエーテルエーテ
ルケトン、ポリエーテルサルフォン、ポリフェニレンオ
キサイド等で上記特性を満足するものを使用できる。ま
た絶縁層に設ける金属箔としては、通常銅箔が使用され
る。
Specific resins used in the resin layer include polyphenylene sulfide, polyether ether ketone, polyether sulfone, polyphenylene oxide, etc., which satisfy the above characteristics. Copper foil is usually used as the metal foil provided on the insulating layer.

【0009】つぎに上記構成からなる各素材を用いて熱
プレス等により積層し一体化する。熱プレス条件は、使
用する耐熱性熱可塑性樹脂の種類等により異なるが、プ
レス温度を使用する樹脂の流動開始温度以上、プレス圧
を面圧力5〜100Kg/cm2 の範囲で、減圧条件下
で行なうと、ボイドの発生が防止できて好ましい。得ら
れた積層板は、後続のプリント配線板製造工程に送ら
れ、金属箔へのパターン印刷、エッチング、水洗、スル
ーホール形成等の通常の処理を行い、最終的なプリント
配線板が得られる。
Next, the materials having the above-mentioned constitutions are laminated and integrated by hot pressing or the like. The hot pressing conditions vary depending on the type of heat-resistant thermoplastic resin used, etc., but the pressing temperature is not less than the flow start temperature of the resin to be used, the pressing pressure is in the range of 5 to 100 Kg / cm 2 , and the depressurizing condition is It is preferable to do so because voids can be prevented from occurring. The obtained laminated board is sent to the subsequent printed wiring board manufacturing process, and is subjected to usual processing such as pattern printing on a metal foil, etching, washing with water, and formation of through holes to obtain a final printed wiring board.

【0010】[0010]

【実施例】実施例 下記の内容でプリント配線板を得た。 金属板:Fe−Ni合金板(Ni含有率36重量%)の
両側に銅層を被覆(厚さ比率が銅:Fe−Ni合金板:
銅)=1:8:1で線膨張率3×10-6(mm/mm
℃)板厚は800μm。
EXAMPLES Example A printed wiring board having the following contents was obtained. Metal plate: Fe-Ni alloy plate (Ni content 36% by weight) is coated with copper layers on both sides (thickness ratio is copper: Fe-Ni alloy plate:
Copper) = 1: 8: 1 and coefficient of linear expansion 3 × 10 −6 (mm / mm
C.) Plate thickness is 800 μm.

【0011】絶縁層:ポリエーテルエーテルケトン(線
膨張率5×10-5mm/mm℃、ヤング率460Kg/
mm2 ) 層厚は100μm。
Insulating layer: polyether ether ketone (coefficient of linear expansion 5 × 10 −5 mm / mm ° C., Young's modulus 460 kg /
mm 2 ) The layer thickness is 100 μm.

【0012】上記金属板の両面に上記絶縁層及び銅箔
(18μm厚)を載置後、加熱加圧し積層一体化した。
積層体全体の線膨張率は3.5×10-6(mm/mm
℃)。得られた積層体を用いて「冷熱サイクル」試験を
行なったところ4200サイクル以上問題がなかった。
After placing the insulating layer and the copper foil (18 μm thick) on both sides of the metal plate, they were heated and pressed to be laminated and integrated.
The linear expansion coefficient of the entire laminate is 3.5 × 10 −6 (mm / mm
C). When a "cooling / heating cycle" test was conducted using the obtained laminate, there was no problem for 4200 cycles or more.

【0013】ここで冷熱サイクル試験は上記積層板から
なるプリント配線板上に半導体素子(10mm角)をハ
ンダバンプを用いリフロー法でハンダ接合し、−65℃
〜125℃の冷熱サイクルを繰り返し、その部分での電
気抵抗を測定し接合部分でのクラックの発生を検知して
クラックが発生するまでのサイクル数を測定したもので
ある。
Here, in the cooling / heating cycle test, a semiconductor element (10 mm square) was solder-bonded by a reflow method to a printed wiring board composed of the above-mentioned laminated plate by using a solder bump, and the temperature was -65 ° C.
By repeating the cooling / heating cycle of up to 125 ° C., the electrical resistance at that portion was measured, the occurrence of cracks at the joint was detected, and the number of cycles until cracks were generated was measured.

【0014】[0014]

【発明の効果】上述したように、本発明のプリント配線
板によれば、冷熱サイクルが加わっても接続部分にクラ
ック等が発生しにくく、大型の半導体素子を高密度に表
面実装することができるため、動作温度が広い自動車の
制御装置用プリント配線板等への利用性が大きい。
As described above, according to the printed wiring board of the present invention, cracks and the like are unlikely to occur at the connection portion even when a thermal cycle is applied, and large semiconductor elements can be surface-mounted at high density. Therefore, it is highly applicable to printed wiring boards for control devices of automobiles having a wide operating temperature.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 両面に銅を被覆してなる鉄ーニッケル合
金板からなり、線膨張率(ASTMD−696)が6×
10-6mm/mm℃以下である金属板の少なくとも片面
に、線膨張率が3×10-5〜8×10-5mm/mm℃
で、かつヤング率(ASTMD−882)が200〜8
00Kg/mm2 の範囲の耐熱性熱可塑性樹脂からなる
絶縁層及び金属箔を積層してなり、上記絶縁層の厚みが
20〜200μmの範囲であると共に積層板全体の線膨
張率が2×10-6〜8×10-6mm/mm℃の範囲であ
る半導体素子実装用プリント配線板。
1. An iron-nickel alloy plate having copper coated on both sides, having a linear expansion coefficient (ASTMD-696) of 6 ×.
The linear expansion coefficient is 3 × 10 −5 to 8 × 10 −5 mm / mm ° C. on at least one surface of the metal plate having a temperature of 10 −6 mm / mm ° C. or less.
And Young's modulus (ASTMD-882) is 200 to 8
The insulating layer and the metal foil made of a heat-resistant thermoplastic resin in the range of 00 Kg / mm 2 are laminated, and the thickness of the insulating layer is in the range of 20 to 200 μm and the linear expansion coefficient of the entire laminated plate is 2 × 10. A printed wiring board for mounting a semiconductor element in the range of -6 to 8 x 10 -6 mm / mm ° C.
JP23376792A 1992-09-01 1992-09-01 Printed wiring board for mounting semiconductor device Pending JPH0685414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23376792A JPH0685414A (en) 1992-09-01 1992-09-01 Printed wiring board for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23376792A JPH0685414A (en) 1992-09-01 1992-09-01 Printed wiring board for mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH0685414A true JPH0685414A (en) 1994-03-25

Family

ID=16960256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23376792A Pending JPH0685414A (en) 1992-09-01 1992-09-01 Printed wiring board for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH0685414A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095623B2 (en) 2002-05-27 2006-08-22 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095623B2 (en) 2002-05-27 2006-08-22 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus
US7170012B2 (en) 2002-05-27 2007-01-30 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus

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