JPH0685412A - Feedback wiring pattern for electronic circuit - Google Patents

Feedback wiring pattern for electronic circuit

Info

Publication number
JPH0685412A
JPH0685412A JP25887692A JP25887692A JPH0685412A JP H0685412 A JPH0685412 A JP H0685412A JP 25887692 A JP25887692 A JP 25887692A JP 25887692 A JP25887692 A JP 25887692A JP H0685412 A JPH0685412 A JP H0685412A
Authority
JP
Japan
Prior art keywords
wiring pattern
noise
feedback
ground
ground plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25887692A
Other languages
Japanese (ja)
Inventor
Seiichi Tokuhisa
誠一 徳久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP25887692A priority Critical patent/JPH0685412A/en
Publication of JPH0685412A publication Critical patent/JPH0685412A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference

Abstract

PURPOSE:To prevent the mixing of noise into a feedback circuit and also to prevent the superpositioning of noise on the output by a method wherein the earth pattern, with which the earthing wires on the former stage and the latter stage of an electronic circuit are connected, are provided side by side, and at the same time, they are connected to the earthing wire of the electronic circuit at one point. CONSTITUTION:As the ground plane 4, which is stratified on a feedback wiring pattern 3, is connected to an earthing wire at a point 10 on the former stage, and the ground plane 4 is insulated an earth pattern on the other points, the current between machines is allowed to flow to the earth pattern 5, and it is not allowed to flow on the ground plane 4. Accordingly, no induced electromotive force is generated on the feedback wiring pattern 3, the and mixing of noise is prevented. Also, the earth pattern 5 is symmetrically provided side by side to the feedback wiring pattern 3. Accordingly, the induced electromotive force by the electromagnetic flux becomes equal, no noise is generated on the voltage between an output terminal 8a and the earthing wire 8b of the output terminal, and the superposition of noise can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子回路の帰還配線パ
ターンに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedback wiring pattern for electronic circuits.

【0002】[0002]

【従来の技術】従来、電子回路の帰還配線パターンは、
それに混入する雑音、出力電圧に現れる雑音等に対して
は十分検討されているとは云えなかった。そこで従来の
帰還配線パターンの欠点をオーディオ用負帰還アンプリ
ファイヤーの場合を例に取り、図を用いて説明する。
2. Description of the Related Art Conventionally, feedback wiring patterns for electronic circuits are
It cannot be said that sufficient consideration has been given to noise mixed therein and noise appearing in the output voltage. Therefore, the drawbacks of the conventional feedback wiring pattern will be described with reference to the drawings, taking the case of an audio negative feedback amplifier as an example.

【0003】電源トランスを有する電子機器同士を接続
すると、そのアース間には高周波成分を含む機器間電流
が雑音電流として流れる。この機器間電流は、電子機器
の入力のアースから電源トランスの一次巻線と二次巻線
の静電容量を経由してAC電源へ流れる。あるいは電子
機器の入力のアースから電子機器の出力へ流れる。その
ため、機器間電流は電子回路の前段と後段のアースを経
由する。
When electronic devices having a power transformer are connected to each other, an inter-device current containing a high frequency component flows as a noise current between the grounds. This inter-device current flows from the ground of the input of the electronic device to the AC power source via the capacitance of the primary winding and the secondary winding of the power transformer. Alternatively, it flows from the ground of the input of the electronic device to the output of the electronic device. Therefore, the inter-device current passes through the grounds at the front and rear of the electronic circuit.

【0004】多くのオーディオ用負帰還アンプリファイ
ヤーの場合、帰還配線パターンは後段から前段へ接続さ
れているため、前段と後段の間を流れる機器間電流によ
って、帰還配線パターンに誘導起電力による雑音が生じ
る。例えば、図2に示すような片面がグランドプレーン
の両面基板が使用されていると、そのグランドプレーン
を流れる機器間電流によって帰還配線パターンに誘導起
電力による雑音が生じる。このため出力点の出力信号
に、この誘導起電力による雑音が重畳する原因となって
いた。なお、図2及び後述する図1は配線基板上に実装
される部品の内、説明に必要なもの以外は省略して描い
てある。
In many negative feedback amplifiers for audio, since the feedback wiring pattern is connected from the latter stage to the former stage, noise due to induced electromotive force is generated in the feedback wiring pattern due to the inter-device current flowing between the former stage and the latter stage. Occurs. For example, when a double-sided board having a ground plane on one side as shown in FIG. 2 is used, noise due to induced electromotive force is generated in the feedback wiring pattern by the inter-device current flowing through the ground plane. For this reason, this induced electromotive force causes noise to be superimposed on the output signal at the output point. It should be noted that FIG. 2 and FIG. 1 to be described later are illustrated by omitting the components mounted on the wiring board except those necessary for explanation.

【0005】一方、アンプリファイヤーのきょう体内で
発生する電磁フラックスのため、帰還配線パターン及び
グランドには誘導起電力による雑音が発生する。きょう
体内の電磁フラックスは電源トランスや出力段から多く
発生するが、従来のアンプリファイヤーは帰還配線パタ
ーン及びグランドに発生する誘導起電力に対して配慮さ
れていなかったため、特に出力段から発生する電磁フラ
ックスの影響を強く受け、出力電圧に雑音が現れる欠点
があった。
On the other hand, due to the electromagnetic flux generated in the housing of the amplifier, noise is generated in the return wiring pattern and the ground due to the induced electromotive force. A large amount of electromagnetic flux is generated in the housing from the power transformer and the output stage, but since the conventional amplifier did not pay attention to the induced electromotive force generated in the return wiring pattern and the ground, the electromagnetic flux generated especially from the output stage. There was a drawback that the output voltage was affected by the noise.

【0006】以上のことを図3の等価回路図で説明す
る。アンプリファイヤー13は理想オペレーショナルア
ンプリファイヤーとする。グランドプレーンに流れる機
器間電流によって、帰還配線パターンに誘起される雑音
電圧をVn1とする。そのときアンプリファイヤーは雑音
−Vn1を発生する。
The above will be described with reference to the equivalent circuit diagram of FIG. The amplifier 13 is an ideal operational amplifier. Let Vn1 be the noise voltage induced in the feedback wiring pattern by the inter-device current flowing in the ground plane. The amplifier then produces noise -Vn1.

【0007】また、入力電圧をVin、抵抗11aをR
a、抵抗11bをRb、電磁フラックスによって帰還回
路内で生じる誘導起電力をVn2、アースで生じる誘導起
電力をVn3とすると、通常はVn3≠Vn2なので、その差
Vn3−Vn2が出力電圧に雑音として現れる。以上を数式
で示すと、出力電圧Voutは式1で表される。 Vout=Vin(1+Rb/Ra)−Vn1+Vn3−Vn2 … 式1
Further, the input voltage is Vin and the resistor 11a is R
Letting a be Rb, the resistance 11b be Rb, the induced electromotive force generated in the feedback circuit by the electromagnetic flux be Vn2, and the induced electromotive force generated at the ground be Vn3, Vn3 is not equal to Vn3. appear. When the above is expressed by a mathematical expression, the output voltage Vout is expressed by Expression 1. Vout = Vin (1 + Rb / Ra) -Vn1 + Vn3-Vn2 Equation 1

【0008】[0008]

【発明が解決しようとする課題】本発明が解決しようと
する課題は、従来の帰還配線パターンの欠点であった、
機器間電流の誘導起電力によって帰還回路に雑音が混入
すること。及び係る電子回路のきょう体内で発生する電
磁フラックスによって出力電圧に雑音が現れることを防
止することにある。
The problem to be solved by the present invention is a drawback of the conventional feedback wiring pattern.
Noise is mixed in the feedback circuit due to the induced electromotive force of the current between devices. And to prevent noise from appearing in the output voltage due to the electromagnetic flux generated in the housing of the electronic circuit.

【0009】[0009]

【課題を解決するための手段】上記の課題を達成するた
めに、プリント基板上の帰還配線パターンにグランドプ
レーンを重層し、電子回路前段と後段のアースを接続す
るアースパターンを、帰還配線パターンに重層させたグ
ランドプレーンとは絶縁して並設する。電子回路前段と
後段のアースを接続するアースパターンは帰還配線パタ
ーンに対してほぼ対称に並設する。帰還配線パターンに
重層させたグランドプレーンは一ヶ所で係る電子回路の
アースに接続する。
In order to achieve the above-mentioned object, a ground plane is layered on a return wiring pattern on a printed circuit board, and an earth pattern for connecting a ground at a front stage and a rear stage of an electronic circuit is used as a return wiring pattern. Insulate from the stacked ground planes and install them side by side. The ground patterns that connect the grounds of the front and rear stages of the electronic circuit should be installed substantially symmetrically with respect to the return wiring pattern. The ground plane that is layered on the return wiring pattern is connected to the ground of the electronic circuit concerned at one place.

【0010】[0010]

【作用】以上のように構成すると、帰還配線パターンに
重層させたグランドプレーンは一ヶ所でアースと接続さ
れており、その他はアースパターンと絶縁されているた
め機器間電流による雑音電流がグランドプレーンを流れ
ることは無いから、帰還配線パターンに機器間電流によ
る誘導起電力が生じることはなく、帰還回路に雑音が混
入することは無い。
[Operation] With the above configuration, the ground plane that is layered on the return wiring pattern is connected to the ground at one place, and the others are insulated from the ground pattern, so noise current due to inter-device current causes the ground plane to pass through. Since it does not flow, an induced electromotive force due to an inter-device current does not occur in the feedback wiring pattern, and noise is not mixed in the feedback circuit.

【0011】また、アースパターンが帰還配線パターン
と並設されているため、きょう体内で発生する電磁フラ
ックスによる誘導起電力Vn3とVn2はほぼ等しくするこ
とが可能になり、Vn3−Vn2=0となって出力電圧に雑
音が現れることは無い。
Further, since the ground pattern is provided in parallel with the return wiring pattern, the induced electromotive forces Vn3 and Vn2 due to the electromagnetic flux generated in the housing can be made substantially equal, and Vn3-Vn2 = 0. No noise appears in the output voltage.

【0012】[0012]

【実施例】図1は本発明の実施例であって、1は配線基
板、2は配線基板の絶縁材、3は帰還配線パターン、4
は帰還配線パターンに重層させたグランドプレーン、5
は帰還配線パターンに並設されているアースパターンで
電子回路前段と後段のアースを接続する、6は回路前段
のグランドプレーン、7は回路後段のグランドプレー
ン、8aは出力端子、8bは出力端子のアース、9は出
力トランジスタ、10は帰還配線パターンに重層させた
グランドプレーンが一ヶ所でアースと接続されている
点、11aは帰還抵抗、11bは帰還抵抗、12aは入
力端子、12bは入力端子のアースである。
FIG. 1 shows an embodiment of the present invention, in which 1 is a wiring board, 2 is an insulating material for the wiring board, 3 is a return wiring pattern, and 4 is a wiring pattern.
Is a ground plane that is layered on the return wiring pattern, 5
Is a grounding pattern arranged in parallel with the feedback wiring pattern to connect the grounds of the front and rear stages of the electronic circuit. Ground, 9 is an output transistor, 10 is a point where a ground plane laminated on the feedback wiring pattern is connected to the ground at one place, 11a is a feedback resistor, 11b is a feedback resistor, 12a is an input terminal, and 12b is an input terminal. It is earth.

【0013】このような構成になっているから、帰還配
線パターン3に重層させたグランドプレーン4は前段の
一ヶ所10でアースと接続されているのみで、その他は
アースパターン5とは絶縁されているから、機器間電流
はアースパターン5を流れ、グランドプレーン4を流れ
ることは無い。従って帰還配線パターン3に機器間電流
による誘導起電力が生じることはなく、式1はVn1=0
で帰還回路に機器間電流による雑音が混入することは無
い。
Due to such a structure, the ground plane 4 layered on the return wiring pattern 3 is only connected to the ground at one place 10 in the previous stage, and the others are insulated from the ground pattern 5. Therefore, the inter-device current flows through the ground pattern 5 and does not flow through the ground plane 4. Therefore, an induced electromotive force due to an inter-device current does not occur in the feedback wiring pattern 3, and the equation 1 is Vn1 = 0.
Therefore, the noise due to the current between devices is not mixed in the feedback circuit.

【0014】また、きょう体内の電磁フラックスは電源
トランスや出力段のトランジスタ9から多く発生する
が、アースパターン5は帰還配線パターン3に対して対
称に並設されているため、電磁フラックスによる誘導起
電力Vn3とVn2は等しくなり、式1はVn3−Vn2=0と
なり、出力端子8aと出力端子のアース8b間の電圧に
雑音が現れることは無い。
Further, a large amount of electromagnetic flux is generated in the housing from the power transformer and the transistor 9 in the output stage. However, since the ground pattern 5 is symmetrically arranged with respect to the return wiring pattern 3, induction induced by the electromagnetic flux is caused. The electric powers Vn3 and Vn2 are equal to each other, the expression 1 is Vn3-Vn2 = 0, and noise does not appear in the voltage between the output terminal 8a and the ground 8b of the output terminal.

【0015】[0015]

【発明の効果】以上説明したように、帰還回路に雑音が
混入することがなく、出力に雑音が重畳することは無
い。さらに帰還回路に雑音が入力されることによって起
こる歪も防ぐことが出来る。また、きょう体内で発生す
る電磁フラックスに対しては、帰還回路とアースパター
ンが同一の誘導起電力を生じるため、お互いに相殺さ
れ、出力に雑音が現れることも無い。
As described above, noise is not mixed in the feedback circuit and noise is not superimposed on the output. Furthermore, distortion caused by noise input to the feedback circuit can be prevented. Further, with respect to the electromagnetic flux generated in the housing, the feedback circuit and the ground pattern generate the same induced electromotive force, so that they cancel each other out, and noise does not appear in the output.

【0016】従って、電子機器にこの帰還配線パターン
を採用した場合では、低雑音とすることが可能である。
特にオーディオアンプリファイヤーに応用した場合で
は、機器間電流に誘導される高周波ノイズが帰還回路に
入力されることが減少するため、TIM歪など、高周波
ノイズによってひきおこされるオーディオアンプリファ
イヤーの歪も減少し、低雑音でしかも聴感上非常に良好
な音質のオーディオアンプリファイヤーとすることがで
きる。
Therefore, when this feedback wiring pattern is adopted in the electronic equipment, it is possible to reduce the noise.
Especially when applied to audio amplifiers, high-frequency noise induced by inter-device current is less likely to be input to the feedback circuit, so distortion of audio amplifiers caused by high-frequency noise, such as TIM distortion, is also reduced. It can be an audio amplifier that has low noise and very good sound quality in terms of hearing.

【0017】なお、本発明は上記した実施例に限定され
るものではなく、帰還配線パターンに重層するグランド
プレーンを二層にして、その間に帰還配線パターンを挟
装することもできる。また、アースパターンは帰還配線
パターンに重層させたグランドプレーンの両脇に配置す
るばかりでなく、多層基板を用いグランドプレーンの外
側に重層する構成に対しても適用可能である。また、本
発明はオーディオ用負帰還アンプリファイヤーについて
のみ説明したが、帰還回路を有する一般の電子回路にも
適用可能である。
The present invention is not limited to the above-described embodiment, but the ground planes which are superposed on the return wiring pattern may be two layers, and the return wiring pattern may be sandwiched therebetween. Further, the ground pattern is not only arranged on both sides of the ground plane layered on the return wiring pattern, but also applicable to a configuration in which a multi-layer substrate is used to layer on the outside of the ground plane. Further, although the present invention has been described only for the negative feedback amplifier for audio, it can be applied to a general electronic circuit having a feedback circuit.

【0018】機器間電流に関する参考文献としては次の
ものがある。「MJ 無線と実験誠文堂新光社 199
2年 6月号 p.133 メーカー製品を凌ぐアンプ
製作術(2) 電源・アース電位の考察 徳久誠一」
The following are references regarding the current between devices. "MJ radio and experiment Seibundo Shinkosha 199
June 2nd year p. 133 Amplifier manufacturing techniques that surpass manufacturer's products (2) Consideration of power supply and earth potential Seiichi Tokuhisa ”

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る帰還配線パターンの実施例を示す
斜視図である。
FIG. 1 is a perspective view showing an embodiment of a return wiring pattern according to the present invention.

【図2】従来の帰還配線パターンを示す斜視図である。FIG. 2 is a perspective view showing a conventional return wiring pattern.

【図3】雑音源を示す等価回路図である。FIG. 3 is an equivalent circuit diagram showing a noise source.

【符号の説明】[Explanation of symbols]

1 配線基板 2 絶縁材 3 帰還配線パターン 4 帰還配線パターンに重層させたグランドプレー
ン 5 帰還配線パターンに並設されているアースパタ
ーン 6 前段のグランドプレーン 7 後段のグランドプレーン 8a 出力端子 8b 出力端子のアース 9 出力トランジスタ 10 帰還配線パターンに重層させたグランドプレー
ンが一ヶ所でアースと接続されている点 11a 帰還抵抗 11b 帰還抵抗 12a 入力端子 12b 入力端子のアース 13 理想オペレーショナルアンプリファイヤー
1 wiring board 2 insulating material 3 return wiring pattern 4 ground plane layered on the return wiring pattern 5 ground pattern arranged in parallel with the return wiring pattern 6 ground plane at the front stage 7 ground plane at the rear stage 8a output terminal 8b output terminal ground 9 Output Transistor 10 Point where the ground plane laminated to the feedback wiring pattern is connected to the ground at one place 11a Feedback resistor 11b Feedback resistor 12a Input terminal 12b Input terminal ground 13 Ideal operational amplifier

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】帰還回路を有する電子回路において、配線
基板上の帰還配線パターンにグランドプレーンを重層
し、係る電子回路前段と後段のアースを接続するアース
パターンを帰還配線パターンに重層させたグランドプレ
ーンとは絶縁して並設し、帰還配線パターンに重層させ
たグランドプレーンは一ヶ所で係る電子回路のアースに
接続したことを特徴とする電子回路の帰還配線パター
ン。
1. In an electronic circuit having a feedback circuit, a ground plane is layered on a feedback wiring pattern on a wiring board, and a ground plane is connected to the feedback wiring pattern so as to connect the grounds of the preceding and subsequent stages of the electronic circuit. A return wiring pattern for an electronic circuit, characterized in that the ground planes, which are insulated from each other and arranged in parallel, are connected to the ground of the electronic circuit concerned at one place.
JP25887692A 1992-09-03 1992-09-03 Feedback wiring pattern for electronic circuit Pending JPH0685412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25887692A JPH0685412A (en) 1992-09-03 1992-09-03 Feedback wiring pattern for electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25887692A JPH0685412A (en) 1992-09-03 1992-09-03 Feedback wiring pattern for electronic circuit

Publications (1)

Publication Number Publication Date
JPH0685412A true JPH0685412A (en) 1994-03-25

Family

ID=17326269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25887692A Pending JPH0685412A (en) 1992-09-03 1992-09-03 Feedback wiring pattern for electronic circuit

Country Status (1)

Country Link
JP (1) JPH0685412A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100708378B1 (en) * 2004-07-24 2007-04-18 주식회사 대우일렉트로닉스 Print pattern design method for power supply and ground of dc to dc converter
JP2007324511A (en) * 2006-06-05 2007-12-13 Cmk Corp Differential impedance aligned printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100708378B1 (en) * 2004-07-24 2007-04-18 주식회사 대우일렉트로닉스 Print pattern design method for power supply and ground of dc to dc converter
JP2007324511A (en) * 2006-06-05 2007-12-13 Cmk Corp Differential impedance aligned printed circuit board

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