JPH0685205A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain an SRAM wherein it can make a memory cell size small without spoiling the symmetry of elements constituting a memory cell and of the layout pattern of an interconnection and its structure is resistant to soft errors. CONSTITUTION:Transistors QD1, QA1 and a noninverted bit line 121a or the like which constitute a noninverted bit line circuit 101 are formed inside a first plane on a P<-> semiconductor substrate, transistors QD2, QA2 and an inverted bit line 122a or the like which constitute a noninverted bit line circuit 102 are formed inside a second plane on the P<-> semiconductor substrate so as to be overlapped with the noninverted bit line circuit 101, and both circuits are connected by through holes 151, 152.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high-density design associated with an increase in capacity of a static RAM memory (hereinafter referred to as SRAM memory).

[0002]

2. Description of the Related Art FIG. 4 is a diagram for explaining a high resistance load type memory cell constituting a conventional SRAM memory, and FIG. 4 (a) is a circuit diagram showing an example of a circuit configuration of the memory cell. .

In FIG. 4 (a), reference numeral 200 denotes the high resistance load type memory cell, and in this memory cell 200, a power source V
A resistor R1 and a driver transistor QD1 connected in series between cc and ground and a resistor R2 and a driver transistor QD2 connected in series are connected in parallel, and one gate of the driver transistors QD1 and QD2 is the drain of the other. That is, it is connected to the connection point with the resistor. An access transistor QA1 is connected between the drain of the driver transistor QD1 and the non-inverted bit line B, and an access transistor QA2 is connected between the drain of the driver transistor QD2 and the inverted bit line / B. A word line W is connected to.
As described above, the high resistance load type memory cell 200 is composed of a high resistance portion, a driver transistor for latching data, and an active transistor used for writing and reading data, and these are connected to the non-inverted bit line and the inverted bit line. It has a configuration provided to the opposite.

FIG. 4B shows a layout pattern of constituent elements and wirings for realizing the circuit configuration of FIG. 4A. In the figure, 202a to 202f are selected on the P ⁻ semiconductor substrate 201. In the N ⁺ diffusion regions formed in a uniform manner, these form a plane pattern that is substantially symmetrical. 211
a is a first polysilicon layer which is formed so as to pass over a predetermined portion of the P ⁻ semiconductor substrate 1 and constitutes the word line W, and which is the diffusion regions 202a and 202b and the first polysilicon layer sandwiched between these diffusion regions. The driver transistor QA1 is formed from a part of one polysilicon layer, and the access transistor QA2 is formed from the diffusion regions 202c and 202d and a part of the first polysilicon layer sandwiched between these diffusion regions. There is.

Further, 211b and 211c are first polysilicon layers formed on a predetermined region of the P ^- semiconductor substrate 1 and are diffusion regions 202f and 202e and a part of the first polysilicon layer 211b sandwiched between them. And the driver transistor QD1 is composed of
And 202b and a part of the first polysilicon layer 211c sandwiched between them, the driver transistor QD2 is formed.

Reference numeral 212 is the driver transistor Q.
A second polysilicon layer 221c for connecting the drain of D1 and the gate of the driver transistor QD2,
Reference numerals 221b are contact holes for connecting the second polysilicon layer 212 to the drain of the driver transistor QD1 and the gate of the driver transistor QD2, respectively. The drain of the driver transistor QD2 and the gate of the drain transistor QD1 are connected by a contact hole 221a.

Reference numeral 213 is a third polysilicon layer for supplying the power source Vcc, which is connected to the gate of the drain transistor QD1 via the contact hole 221d, that is, the first polysilicon layer 211b, and the driver transistor QD2 via the contact hole 221e. Gate of the, that is, the first
It is connected to the polysilicon layer 211c. The resistors 121 and 122 are formed by the polysilicon layer embedded in the contact holes 211d and 211e.

Further, 214a and 214b are aluminum wirings forming a non-inverted bit line and an inverted bit line, respectively, which are connected to the sources of the access transistors QA1 and QA2 through contact holes 221f and 221g, respectively. The first polysilicon layers 211b and 211c and the aluminum wirings 214a and 214b are symmetrically arranged here, and the first polysilicon layer 211a and the third polysilicon layer 212 have a symmetrical pattern. .

The following operation will be described. In the high resistance type memory cell 200 having such a configuration, when the word line W is activated, the access transistors QA1 and QA2 are turned on and the storage nodes, that is, the driver transistors QD1 and QD1.
The signal level of the drain of D2 is transmitted to the non-inverted bit line B and the inverted bit line / B as information, whereby the stored information is read. In contrast to writing, writing is the opposite of
The word line W is activated and the access transistor QA
With 1 and QA2 turned on, complementary signals are applied to the non-inverted bit line B and the inverted bit line / B, and these are latched by the driver transistors QD1 and QD2 to store information in the storage node.

[0010]

However, in the conventional static type memory cell having such a structure, four transistors are necessary to form the memory cell, and therefore,
There is a limit to the area reduction of the memory cell, and there is a problem in the chip size and the like in the development of the large capacity memory.

In the memory cell 200, the gate of the driver transistor QD1 and the drain of the driver transistor QD2 are connected by a part of the diffusion region 202b, whereas the gate of the driver transistor QD2 and the driver transistor QD1. Of the driver transistor QD1 due to the difference in resistance value and capacitance value between the diffusion region 202b and the second polysilicon layer 212.
And QD2 differ in response time and power required for driving. As a result, a difference in load capacitance between the non-inverted bit line and the inverted bit line causes a difference in response time between the high level and the low level.

Further, a difference occurs in the information holding level at each storage node, that is, the holding voltage of one of the high level and the low level becomes weak, and in particular, the elements and wirings constituting the memory cell are covered with the mold resin. However, since the memory cell has a structure facing the mold resin, there is a problem that a soft error is likely to occur.

The present invention has been made to solve the above-mentioned problems, and the memory cell size can be reduced without impairing the symmetry of the layout pattern of the elements and wirings constituting the memory cell, An object is to obtain a semiconductor memory device having a structure that is resistant to soft errors.

[0014]

In a semiconductor memory device according to the present invention, a static memory cell designed so that layout patterns of constituent elements and wirings are line-symmetrical is provided, and the layout pattern is arranged along the line-symmetrical axis. 2
The constituent element and the wiring portion corresponding to the divided first division pattern and the constituent element and the wiring portion corresponding to the second division pattern are formed on the substrate in a vertically overlapping manner.

The present invention provides the semiconductor memory device as described above,
The constituent elements and wiring portions corresponding to the first division pattern are access transistors and driver transistors on the non-inverted bit line side, and non-inversion bit lines and word lines, and the constituent elements and wiring portions corresponding to the second division pattern. The wiring parts are an access transistor and a driver transistor on the inverted bit line side, an inverted bit line and a word line, and the bit lines, word lines and transistors forming the static memory cell are
Of the polysilicon layer, the first to third aluminum wiring layers, and the first and second diffusion layers.

[0016]

According to the present invention, the static memory cell designed such that the layout patterns of the constituent elements and wirings are line-symmetrical corresponds to one of the divided patterns obtained by dividing the layout pattern into two along the line-symmetrical axis. Since the constituent element and the wiring portion to be formed and the constituent element and the wiring portion corresponding to the other division pattern are formed on the substrate in the vertical direction, the symmetry of the layout pattern of the element and the wiring that configures the memory cell is impaired. Therefore, the memory cell size can be reduced, and a large-capacity memory cell with a small area can be realized.

Further, since the non-inverted bit line system circuit and the inverted bit line system circuit are formed on different planes on the substrate, it is necessary to realize the same structure in which the patterns of elements and wirings are symmetrical in both circuits. Therefore, it is possible to eliminate the difference in characteristics between the two circuits. This makes it possible to prevent the response time between the high level and the low level from deviating from each other and the holding voltage of one level from becoming weak.

Further, in the present invention, a multi-layered structure for forming the constituent elements and wirings of the static memory cell is provided with first to sixth polysilicon layers and first to third layers.
Since the aluminum wiring layer and the first and second diffusion layers are provided and the aluminum wiring layer is provided as the uppermost layer of the aluminum wiring layer, the memory cell is electromagnetically shielded by the aluminum wiring layer. Since the probability of arrival of alpha rays from the memory cell to the memory cell is reduced, the soft error tolerance can be improved.

[0019]

Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. Figure 1
FIG. 2A is a perspective view for explaining the structure of a static memory cell that constitutes a semiconductor memory device according to an embodiment of the present invention. FIG. 2A is a second view on the substrate of elements and wirings that constitute the memory cell. FIG. 2B is a plan view of the layout pattern on the first plane of the substrate of the elements and wirings forming the memory cell viewed from above, and FIG. 3 is the above plan view. FIG. 6 is a schematic cross-sectional view showing a connection relationship between elements and wirings on a first plane and elements and wirings on a second plane.

In the figure, reference numeral 100 denotes a high resistance load type memory cell having the same circuit configuration as that of the conventional memory cell 200 and designed so that layout patterns of constituent elements and wirings are line symmetrical. A component and a wiring portion corresponding to the first division pattern obtained by dividing the pattern into two along the line symmetry axis and a component and a wiring portion corresponding to the second division pattern are vertically arranged on the P ⁻ semiconductor substrate 1. It is formed by overlapping.

Reference numeral 101 denotes a constituent element and a wiring portion corresponding to the first division pattern, which is mainly a non-inverted bit line 121.
a, a word line 111, a non-inverted bit line system circuit including an access transistor QA1 and a driver transistor QD1 on the side of the non-inverted bit line, and 102 is a constituent element and a wiring portion corresponding to the second division pattern. It is an inverted bit line system circuit including a line 122a, a word line 115, an access transistor QA2 and a driver transistor QD2 on the non-inverted bit line side. The components and wirings of these circuits 101 and 102 are the first to the fifth.
The polysilicon layers 111 to 115 and the sixth polysilicon layer, and the first to third aluminum wiring layers 121 to 123,
It is formed in a multilayer structure having first diffusion layers 110 and 150.

More specifically, in the non-inverted bit line system circuit 101, the first diffusion layer 110 is the N ⁺ diffusion region 110a selectively formed on the P ⁻ semiconductor substrate 1.
.About.110c. The word line W is formed on the predetermined portion of the P ⁻ semiconductor substrate 1 by the first portion.
A polysilicon layer 111 is formed, and the access transistor Q includes the diffusion regions 110b and 110c and a part of the first polysilicon layer 111 sandwiched between the diffusion regions 110b and 110c.
A1 is configured. A second polysilicon layer is formed on a predetermined portion of the P ⁻ semiconductor substrate 1, and the driver transistor is formed by the diffusion regions 110a and 110b and a part of the second polysilicon layer sandwiched therebetween. QD1 is configured. Incidentally, 110a1 is a P ⁺ diffusion region formed in the N ⁺ diffusion region 110a.

Reference numeral 113 is a third polysilicon layer for supplying the power supply Vcc, and through the contact hole 141, the drain (diffusion region 110) of the driver transistor QD1.
connected to b). Further, 121a is a first aluminum wiring layer which constitutes a non-inverted bit line, and the contact hole 1
It is connected via 42 to the source of the access transistor QA1. 121b is the first aluminum wiring layer 12
A first aluminum wiring layer which is formed in parallel with 1a and supplies a ground potential, is connected to the N ⁺ diffusion region 110a and the P ⁺ diffusion region 110a1 through the contact hole 143.

On the other hand, in the inversion bit line system circuit 102, the diffusion layer 150 is the N ⁺ diffusion regions 150a to 150c selectively formed on the lower surface of the P ⁻ semiconductor layer 2.
It consists of A fifth polysilicon layer 115 forming the word line W is formed on a predetermined portion of the lower surface of the P ⁻ semiconductor layer 2, and the diffusion region 150b is formed.
And 150c and the fifth polysilicon layer 1 sandwiched between them.
The access transistor QA2 is configured with a part of 15. Further, a fourth polysilicon layer 114 is formed on a predetermined portion of the lower surface of the P ⁻ semiconductor layer 2, and the diffusion regions 150a and 150b and a part of the fourth polysilicon layer 114 sandwiched therebetween form the fourth polysilicon layer 114. The driver transistor QD2 is configured. Reference numeral 150a1 is a P ⁺ diffusion region formed in the N ⁺ diffusion region 150a.

Reference numeral 161 is the third power source for supplying the power source Vcc.
The polysilicon layer 113 and the driver transistor Q
A contact hole for connecting the drain (diffusion region 150b) of D2, 122a is a second aluminum wiring layer forming an inverted bit line, and the source (diffusion region 150c) of the access transistor QA2 via the contact hole 162.
It is connected to the. Also, 122b is formed in parallel with the second aluminum wiring layer 122a, and is for supplying a ground potential to the second aluminum wiring layer 122a.
Aluminum wiring layer, N ⁺ via contact hole 163
It is connected to the diffusion region 150a and the P ⁺ diffusion region 150a1.

Reference numeral 152 is the above-mentioned inverted bit line system circuit 10.
A through hole for connecting the gate of the second driver transistor QA2 and the drain of the driver transistor QD1 of the non-inverting bit line system circuit 101, and 151 is the gate of the driver transistor QD1 of the non-inverting bit line system circuit 101 It is a through hole for connecting to the drain of the driver transistor QD2 of the bit line system circuit 102. Each of the contact holes 141 to 143 and the through hole 152 has a structure in which a part of the polysilicon layer or the aluminum layer on the upper side is buried.
The through hole 151 and the contact holes 161 to
Regarding 163, since the semiconductor layer 2 is formed on the upper side thereof, it has a structure in which the sixth polysilicon layer is embedded. Here, the resistors R1 and R are formed by the polysilicon layer embedded in the contact holes 141 and 161.
2 is configured.

Further, 123 is a third aluminum layer which is formed on the entire surface of the P ⁻ semiconductor layer 2 via a protective oxide film 170 and which supplies a ground potential to the second aluminum layer from the outside, and a contact hole 164. Is connected to the P.sup. ⁺ Diffusion region 150a1 through. Note that 111a and 112
Reference numerals a, 114a and 115a are gate oxide films forming the above transistors.

Next, the function and effect will be described. Here, the read and write operations of data from the memory cell are the same as those of the conventional memory cell, and the non-inverted bit line related circuit 10
Signal transmission / reception between 1 and the inverted bit line system circuit 102 is performed through the through holes 151 and 152.

In the memory cell having such a configuration, the driver transistor QD1 and the access transistor QA1 that form the non-inverted bit line system circuit 101, the first polysilicon layer 121a that forms the non-inverted bit line, and the like are formed on the P ^- semiconductor substrate 1. A first driver transistor QD1 and an access transistor QA1 that form an inverted bit line system circuit 102 and a non-inverted bit line that are formed in the upper first plane.
The polysilicon layer 122a and the like are formed on the P ⁻ semiconductor substrate 1 as a second layer.
Since the non-inverted bit line system circuit 101 is formed to overlap in the plane and the two circuits are connected by the through holes 151 and 152, the memory is formed without impairing the symmetry of the layout pattern of the elements and wirings forming the memory cell. There is an effect that the cell size can be reduced and a large-capacity memory cell with a small area can be realized. Further, since the non-inverted bit line system circuit 101 and the inverted bit line system circuit 102 are formed on different planes on the substrate, it is possible to realize the same structure in which the patterns of elements and wirings are symmetrical in both circuits. It is possible to eliminate the difference in characteristics between the two circuits. As a result, there is an effect that it is possible to prevent the response time between the high level and the low level from deviating and the holding voltage of one level from becoming weak.

Further, since the aluminum wiring layer 123 is formed as the uppermost layer of the multilayer structure constituting the memory cell 100, the memory cell is electromagnetically shielded by this aluminum wiring layer, and externally inside the memory cell. The arrival probability of the alpha wire is reduced, which has the effect of improving the soft error tolerance.

[0031]

As described above, according to the semiconductor memory device of the present invention, a static memory cell designed so that the layout patterns of constituent elements and wirings are line-symmetrical can be obtained by using the layout pattern as the line-symmetrical axis. A memory cell is formed because the constituent element and the wiring portion corresponding to one of the divided patterns and the constituent element and the wiring portion corresponding to the other divided pattern, which are divided in two along There is an effect that the memory cell size can be reduced without impairing the symmetry of the layout pattern of elements and wirings, and a large-capacity memory cell with a small area can be realized.

Further, since the non-inverted bit line system circuit and the inverted bit line system circuit are formed on different planes on the substrate, it is necessary to realize the same structure in which the patterns of elements and wirings are symmetrical in both circuits. Therefore, it is possible to eliminate the difference in characteristics between the two circuits. As a result, there is an effect that it is possible to prevent the response time between the high level and the low level from deviating and the holding voltage of one level from becoming weak.

Further, according to the present invention, in the semiconductor memory device, a multilayer structure for forming the constituent elements and wirings of the static type memory cell is provided with first to sixth polysilicon layers and first to third layers. Since the aluminum wiring layer and the first and second diffusion layers are provided and the aluminum wiring layer is provided as the uppermost layer of the aluminum wiring layer, the memory cell is electromagnetically shielded by the aluminum wiring layer. Therefore, the probability of the alpha ray reaching the memory cell is reduced, which has the effect of improving the soft error tolerance.

[Brief description of drawings]

FIG. 1 is a perspective view for explaining the structure of a static memory cell that constitutes a semiconductor memory device according to an embodiment of the present invention.

2 (a) and 2 (b) are plan views showing layout patterns on the second and first planes of elements and wirings constituting the memory cell.

FIG. 3 is a schematic cross-sectional view showing a connection relationship between the elements and wirings on the first plane and the elements and wirings on the second plane.

FIG. 4 is a diagram for explaining a high resistance load type memory cell forming a conventional SRAM memory, FIG. 4 (a) is a circuit diagram showing an example of a circuit configuration of the memory cell, and FIG. 4 (b). FIG. 4 is a plan view showing a layout pattern of constituent elements and wirings for realizing the circuit configuration of FIG. 4 (a).

[Explanation of symbols]

1 P ^- semiconductor substrate 12 P ^- semiconductor layer 100 high resistance load type memory cell 101 non-inverted bit line system circuit 102 inverted bit line system circuit 110, 150 first and second diffusion layers 110a to 110c first diffusion region 111 -115 1st-5th polysilicon layer 121-123 1st-3rd aluminum layer 150a-150c 2nd diffusion area QD1, QD2 driver transistor QA1, QA2 access transistor

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[Procedure amendment]

[Submission date] November 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

FIG. 4B shows a layout pattern of constituent elements and wirings for realizing the circuit configuration of FIG. 4A. In the figure, 202a to 202f are selected on the P ⁻ semiconductor substrate 201. In the N ⁺ diffusion regions formed in a uniform manner, these form a plane pattern that is substantially symmetrical. 211
a is a first polysilicon layer which is formed so as to pass over a predetermined portion of the P ⁻ semiconductor substrate 1 and constitutes the word line W, and which is the diffusion regions 202a and 202b and the first polysilicon layer sandwiched between these diffusion regions. The access transistor QA1 is formed of a part of one polysilicon layer, and the access transistor QA2 is formed of the diffusion regions 202c and 202d and a part of the first polysilicon layer sandwiched between these diffusion regions. There is.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

Reference numeral 152 is the above-mentioned inverted bit line system circuit 10.
A through hole for connecting the gate of the second driver transistor Q D2 and the drain of the driver transistor Q D1 of the non-inversion bit line system circuit 101, 151 is the gate of the driver transistor Q D1 of the non-inversion bit line system circuit 101, It is a through hole for connecting to the drain of the driver transistor QD2 of the inverted bit line system circuit 102. Each of the contact holes 141 to 143 and the through hole 152 has a structure in which a part of the polysilicon layer or the aluminum layer on the upper side is buried.
The through hole 151 and the contact holes 161 to
Regarding 163, since the semiconductor layer 2 is formed on the upper side thereof, it has a structure in which the sixth polysilicon layer is embedded. Here, the resistors R1 and R are formed by the polysilicon layer embedded in the contact holes 141 and 161.
2 is configured.

Claims (3)

[Claims] 1. A semiconductor memory device having a static memory cell designed such that layout patterns of constituent elements and wirings are line-symmetrical, wherein the static memory cell has the layout pattern along the line-symmetric axis. A semiconductor memory characterized in that a constituent element and a wiring corresponding to one of the two divided patterns and a constituent element and a wiring corresponding to the other divided pattern are vertically stacked on a substrate. apparatus. 2. The semiconductor memory device according to claim 1, wherein the constituent elements and wirings corresponding to the first division pattern are an access transistor and a driver transistor on the inversion bit line side, and an inversion bit line and a word line. The constituent elements and wirings corresponding to the second division pattern are access transistors and driver transistors on the non-inverted bit line side, and non-inverted bit lines and word lines, and the static memory cells are the bit lines. , The word line and each transistor are formed in a multilayer structure having first to sixth polysilicon layers, first to third aluminum wiring layers, and first and second diffusion layers. A semiconductor memory device characterized by being present. 3. The semiconductor memory device according to claim 2, wherein the multilayer structure has an aluminum wiring layer as an uppermost layer thereof.