JPH0684369A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the readout time of the data of the memory cell from being increased as much as a conventional case even when the parastic capacity of the bit line is increased because the number of memory cells connected to a bit line is increased in accordance with the high integration of a SRAM. CONSTITUTION:In the memory cell constituted of flip flop parts M1-M4 and transfer gate parts M5 and M6, bipolar transistors Q1 and Q2 are provided. Therefore, when bipolar transistors Q5 and Q6 are added, the load driving ability of field effect transistors M3 and M4 can be apparently made larger as much as the emitter ground current amplification factor of the bipolar transistor hFE nearly about 100 times. Therefore, even when the parastic capacity of the bit line is increased in accordance with the high integration of the SRAM, the readout time of the data of the memory cell is not increased so much as the conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
SRAM, which is especially a flip-flop type memory cell
The present invention relates to a technique suitable for increasing the speed of (Static Random Access Memory).

[0002]

2. Description of the Related Art At present, a flip-flop type memory cell composed of field effect transistors is widely used in a MOS LSI SRAM. Generally, a field effect transistor has a smaller area than a bipolar transistor,
A memory cell formed of a field effect transistor has an advantage that it has a smaller area than a memory cell formed of a bipolar transistor and is suitable for high integration. But,
In general, a field effect transistor has a smaller load driving capability than a bipolar transistor, and therefore as the number of cells connected to a bit line increases as the degree of integration increases, it is possible that the field effect transistor alone charges and discharges the bit line at a sufficiently high speed. It's getting harder.

[0003]

FIG. 2 is a view showing a conventional example, showing a flip-flop type memory cell composed of field effect transistors. In the figure, WL is a word line, BL and BR are bit lines, and VC and VE are power supplies. The memory cells are field effect transistors M1 to M
6, M1 to M4 are flip-flop sections, and M5 and M6 are transfer gate sections. In this memory cell, when M1 is turned on, M4 is turned on, M2,
M3 turns off and enters the first stable state. When M1 is turned off, M4 is turned off and M2 and M3 are turned on.
Becomes stable. Therefore, the present memory cell has data "depending on whether it is in the first or second stable state".
Stores 0 "or" 1 ". In normal memory,
Such memory cells are arranged in a matrix at intersections of word lines and bit lines which are orthogonal to each other. To read the data in this memory cell, the potential of the word line is set to H level and M5 and M6 are turned on. At this time,
If M1 and M4 are on (first stable state), bit line BL is charged by M1 to H level, and bit line BR is discharged by M4 to L level. Further, when M2 and M3 are on (second stable state), the bit line BL becomes L level and BR becomes H level. Therefore, the data of the memory cell can be read by detecting the levels of the bit lines BL and BR. If the SRAM using the flip-flop type memory cell composed of such field effect transistors is highly integrated, the following problems occur. That is, SR
In order to highly integrate the AM, the number of cells connected to the bit line must be increased. Therefore, as the integration becomes higher, the parasitic capacitance of the bit line increases. On the other hand, since the field effect transistor has a smaller load driving capability than the bipolar transistor, the bit line having a large parasitic capacitance cannot be charged / discharged at a sufficiently high speed, which causes a problem that the time for reading the data of the memory cell increases. Occurs.

Therefore, the object of the present invention is to
It is an object of the present invention to provide a semiconductor integrated circuit in which the time for reading data from a memory cell does not increase as compared with the conventional art even if the parasitic capacitance of the bit line increases with the high integration of AM.

[0005]

The above object is a semiconductor integrated circuit having a plurality of memory cells, each of the plurality of memory cells having first and second field effect transistors cross-connected to each other. A flip-flop unit, one end of which is connected to a first node of the flip-flop unit and the other end of which is connected to a first bit line; and one end of which is the flip-flop unit. Second
And a transfer gate portion comprising a second switch having the other end connected to the second bit line and a collector connected to the drain of the first field effect transistor, A first bipolar transistor having a base connected to the source of the first field effect transistor, a collector connected to the drain of the second field effect transistor, and a base connected to the source of the second field effect transistor. And a second bipolar transistor that is provided.

[0006]

When a bipolar transistor whose collector and base are respectively connected to the drain and source of the field effect transistor is added to the field effect transistor in the flip-flop section or the transfer gate section, the load driving capability of the field effect transistor is apparently seen. , The grounded-emitter current amplification factor of bipolar transistor (h _FE ≈100) can be increased. Therefore, SRA
Even if the parasitic capacitance of the bit line increases with the high integration of M,
The time for reading the data of the memory cell does not increase as compared with the conventional case. Hereinafter, the present invention will be described in more detail with reference to examples.

[0007]

1 is a diagram showing a first embodiment of the present invention. In the figure, WL is a word line, BL and BR are bit lines, and VC and VE are power supplies. In this example, according to the present invention, the respective gates and drains of the first and second n-channel field effect transistors (M3, M4) are cross-connected to each other, and the first and second field effect transistors (M3, M4) are connected. ) Is connected to the p-channel field effect transistors (M1, M2) as a load, and one end is the first of the flip-flop parts.
A first switch (M5) having the other end connected to the first bit line (BL) and one end connected to the second node of the flip-flop section and the other end connected to the first node (M5). Two
Second switch (M) connected to the bit line (BR) of
6) and a transfer gate section consisting of a collector, the collector is connected to the drain of the first field effect transistor (M3), and the base is connected to the source of the first field effect transistor (M3). Npn-type first bipolar transistor (Q1) connected
And the collector is the second field effect transistor (M
There is provided an npn-type second bipolar transistor (Q2) connected to the drain of 4) and having a base connected to the source of the second field effect transistor (M4). In this memory cell, when M1 is turned on, M4 and Q2 are turned on and M2, M3 and Q1 are turned off, and the memory cell is in the first stable state. When M1 is turned off, M4 and Q2 are turned off, M2, M3 and Q1 are turned on, and the second stable state is established. Therefore, this memory cell stores data "0" or "1" depending on which of the first and second stable states it is in. To read the data in this memory cell, the potential of the word line is set to H level and M5 and M6 are turned on. At this time, if M1 and M4, Q
2 is on (first stable state), bit line BL
Is charged by M1 to H level, and the bit line BR is discharged by M4 and Q2 to L level. Also,
When M2, M3 and Q1 are on (second stable state), the bit line BR is charged by M2 and becomes H level, and the bit line BL is discharged by M3 and Q1 and becomes L level. Here, the point to be noted is that when M4 and Q2 are on, the discharge current flowing in M4 becomes the base current of Q2, so the current that Q2 discharges the bit line (BR) flows in M4. The point is that the grounded-emitter current amplification factor (h _FE ≈100) times the discharge current is increased. Also, M
3, When Q1 is on, the discharge current flowing in M3 becomes the base current of Q1, so Q1 is the bit line (BL).
The current for discharging is increased by h _FE times the discharge current flowing in M3. Thus, the field effect transistors (M3, M4) in the flip-flop section are connected to the bipolar transistor (Q1, Q1) whose collector and base are connected to the drain and source of the field effect transistor respectively.
When Q2 is added, a field effect transistor ((M3,
It is possible to increase the grounded-emitter current amplification factor (h _FE ≈100) times of the bipolar transistor apparently in the load driving capability of M4). Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case.

FIG. 3 is a diagram showing a second embodiment of the present invention. In the figure, WL is a word line, BL and BR are bit lines, and VC and VE are power supplies. In this example, according to the present invention, the first and second field effect transistors (M1,
A flip-flop part configured by cross-connecting M2) to each other, a first end connected to a first node of the flip-flop part, and a second end connected to a first bit line (BL). A transfer gate unit including a switch (M5) and a second switch (M6) having one end connected to the second node of the flip-flop unit and the other end connected to the second bit line (BR). A pn whose collector is connected to the drain of the first field effect transistor (M1) and whose base is connected to the source of the first field effect transistor (M1).
A p-type first bipolar transistor (Q3), a collector connected to the drain of the second field effect transistor (M2), and a base connected to the source of the second field effect transistor (M2) pnp Type second bipolar transistor (Q4) is provided. In this memory cell, when M1 is turned on, Q3 and M4 are turned on and M2 and
Q4 and M3 are turned off and the first stable state is reached. Also,
When M1 turns off, Q3, M4 turn off, M2, Q4, M
3 turns on and enters the second stable state. Therefore, this memory cell stores data "0" or "1" depending on which of the first and second stable states it is in. To read the data in this memory cell, the potential of the word line is set to H level and M5 and M6 are turned on. At this time, if M1, Q3, and M4 are on (first stable state), bit line BL is charged by M1 and Q3 to H level, and bit line BR is discharged by M4 and becomes L level. When M2, Q4, and M3 are on (second stable state), the bit line BR has M2 and Q.
It is charged by 4 and becomes H level, and the bit line BR is M3.
Is discharged and becomes L level. Here, the point to be noted is that when M1 and Q3 are on, the charging current flowing in M1 becomes the base current of Q3, so that the current by which Q3 charges the bit line (BL) flows in M1. This is the point where the grounded emitter current amplification factor (h _FE ≈100) times the charging current is increased. When M2 and Q4 are on, M
Since the charging current flowing in 2 becomes the base current of Q4,
The current that 4 charges the bit line (BR) is increased by h _FE times the discharge current flowing in M2. In this way, the field effect transistors (M1, M2) in the flip-flop section are
When a bipolar transistor (Q3, Q4) whose collector and base are respectively connected to the drain and source of the field effect transistor is added, the load driving capability of the field effect transistor (M1, M2) is apparently observed, and the emitter of the bipolar transistor is apparently added. It can be increased by the ground current amplification factor (h _FE ≈100) times. Therefore, SRA
Even if the parasitic capacitance of the bit line increases with the high integration of M,
The time for reading the data of the memory cell does not increase as compared with the conventional case.

FIG. 4 is a diagram showing a third embodiment of the present invention. In this example, all of Q1, Q2 added in FIG. 1 and Q3, Q4 added in FIG. 3 are added to the field effect transistors (M3, M4, M1, M2) in the flip-flop unit. In this way, the bipolar transistors (Q1 to Q4) whose collector and base are respectively connected to the drain and source of the field effect transistor are connected to the field effect transistors (M1 to M4) in the flip-flop section.
4), the field effect transistors (M1 to M
It is possible to increase the grounded-emitter current amplification factor (h _FE ≈ 100) times of the bipolar transistor apparently in the load driving capability of 4). Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case. In the above-described embodiments, the switch of the transfer gate section is composed of the N-channel field effect transistor, but this switch may be composed of the P-channel field effect transistor, or
The N-channel field effect transistor and the P-channel field effect transistor may be connected in parallel.

FIG. 5 is a diagram showing a fourth embodiment of the present invention. In the figure, FF indicates a flip-flop unit,
Any of the flip-flop units shown in FIGS. 1, 3, and 4 may be applied. This example is different from the above example only in that the switch of the transfer gate section is formed of a P-channel field effect transistor. Therefore, in the present example as well, the above discussion holds as it is, and even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as much as before.

FIG. 6 is a diagram showing a fifth embodiment of the present invention. In the figure, FF indicates a flip-flop unit,
Any of the flip-flop units shown in FIGS. 1, 3, and 4 may be applied. This example is different from the above example only in that the switch of the transfer gate section is configured by connecting an N-channel field effect transistor and a P-channel field effect transistor in parallel. Therefore, in the present example as well, the above discussion holds as it is, and even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as much as before.

FIG. 7 is a diagram showing a sixth embodiment of the present invention. In the figure, FF indicates a flip-flop unit,
Any of the flip-flop units in FIGS. 1 to 4 may be applied. In this example, according to the present invention, a flip-flop unit (F
F), a first switch whose one end is connected to the first node of the flip-flop section and the other end of which is connected to the first bit line (BL), and one end is the first switch of the flip-flop section. 2 and the other end is connected to the second bit line (B
R), a transfer gate section including a second switch and a gate connected to the word line WL in the first (or second) switch.
Field effect transistor M5 (or M6) connected to
And a bipolar transistor Q5 (or Q6) whose collector and base are connected to the drain and source of the field effect transistor, respectively.
As shown in this figure, bipolar transistors (Q5, Q6) whose collector and base are respectively connected to the drain and source of the field effect transistor (M5, M6) in the transfer gate section.
By adding the above, apparently the load driving capability of the field effect transistors (M5, M6) at the time of bit line discharge, the emitter grounded current amplification factor (h _FE ≈10
It can be increased by 0) times. Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case.

FIG. 8 is a diagram showing a seventh embodiment of the present invention. In the figure, FF indicates a flip-flop unit,
Any of the flip-flop units in FIGS. 1 to 4 may be applied. Also in this example, according to the present invention, the first (or second) switch of the transfer gate unit is connected to the gate by the word line W.
A field effect transistor M5 (or M connected to L
6) and a bipolar transistor Q5 (or Q6) whose collector and base are connected to the drain and source of the field effect transistor, respectively. As shown in this figure, field effect transistors (M5, M6) in the transfer gate section are connected to bipolar transistors (Q5, Q6) whose collector and base are connected to the drain and source of the field effect transistor, respectively.
6) is added, the field effect transistor (M5, M
6) Apparently the load driving capability at the time of bit line discharge, the grounded emitter current amplification factor of bipolar transistor (h _FE ≈
100) times larger. Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case.

FIG. 9 is a diagram showing an eighth embodiment of the present invention. In the figure, FF indicates a flip-flop unit,
Any of the flip-flop units in FIGS. 1 to 4 may be applied. Also in this example, according to the present invention, the first (or second) switch of the transfer gate unit is connected to the gate by the word line W.
A field effect transistor M5 (or M connected to L
6) and a bipolar transistor Q5 (or Q6) whose collector and base are connected to the drain and source of the field effect transistor, respectively. As shown in this figure, field effect transistors (M5, M6) in the transfer gate section are connected to bipolar transistors (Q5, Q6) whose collector and base are connected to the drain and source of the field effect transistor, respectively.
6) is added, the field effect transistor (M5, M
6) Apparently the load driving capability when charging the bit line, the grounded emitter current amplification factor of the bipolar transistor (h _FE ≈
100) times larger. Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case.

FIG. 10 is a diagram showing a ninth embodiment of the present invention. In the figure, FF indicates a flip-flop unit, and any of the flip-flop units in FIGS. 1 to 4 may be applied. Also in this example, according to the present invention, the first (or second) switch of the transfer gate portion is constituted by the field effect transistor M5 (or M6) whose gate is connected to the word line WL, and the field effect transistor whose collector and base are respectively the above-mentioned field effect transistors. And a bipolar transistor Q5 (or Q6) connected to the drain and source of the. As shown in this figure, field effect transistors (M5, M6) in the transfer gate section are connected to bipolar transistors (Q5, Q5) whose collector and base are connected to the drain and source of the field effect transistor, respectively.
When Q6) is added, the field effect transistors (M5, M
6) Apparently the load driving capability when charging the bit line, the grounded emitter current amplification factor of the bipolar transistor (h _FE ≈
100) times larger. Therefore, even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as compared with the conventional case. As described above, in the embodiments of FIGS. 7 to 10, the switch of the transfer gate portion is configured by using the N-channel field effect transistor, but it may be configured by using the P-channel field effect transistor.

FIG. 11 is a diagram showing a tenth embodiment of the present invention. In this example, the flip-flop unit of FIG. 1 is used as the flip-flop unit, and the switch of the transfer gate unit is configured by connecting the switch of FIG. 7 and the switch of FIG. 1 in parallel. Therefore, in the present example as well, the above discussion holds as it is, and even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as much as before. It is obvious that the memory cells can be configured by appropriately combining the examples of FIGS. 1 to 10 as in this example.

FIG. 12 is a diagram showing an eleventh embodiment of the present invention. In this example, the flip-flop unit of FIG. 4 is used as the flip-flop unit, and the switch of the transfer gate unit is configured by connecting the switch of FIG. 7 and the switch of FIG. 10 in parallel. Therefore, in the present example as well, the above discussion holds as it is, and even if the parasitic capacitance of the bit line increases with the high integration of the SRAM, the time for reading the data of the memory cell does not increase as much as before.

FIG. 13 is a diagram showing a twelfth embodiment of the present invention. This figure shows the memory cell of FIG. 1 and a read circuit and a write circuit. In this figure, WL1, WL
Reference numeral 2 is a word line, BL1, BR1, BL2 and BR2 are bit lines, and VC, VE and VYY are power supplies. Also, VYI
N1 and VYIN2 are bit line selection signals, DI and DI '.
Is a write signal. The resistors RYL and RYR and the bipolar transistors QYL and QYR are circuits that determine the potential of the bit line. Further, the bipolar transistors QRL and QRR are differential amplifiers, SA is a sense amplifier, OB is an output buffer, and DO is output data. The data read operation of the memory cell and the data write operation to the memory cell will be described below with reference to this drawing.
First, in order to read the data of the cells connected to the word line WL1 and the bit lines BL1 and BR1, the potential of the word line WL1 is set to the H level and the bit line selection signal VYIN1 is driven to the H level. When the potential of the word line WL1 is set to H level, M5 and M6 are turned on. At this time, if M
When 1 and M4 and Q2 are on (first stable state), bit line BL1 is charged by M1 to H level, and bit line BR1 is discharged by M4 and Q2 to L level. Here, the bit line selection signal VYIN
Since 1 is at H level, the differential amplifier composed of QRL and QRR is activated, and this differential amplifier transmits the voltage difference between the bit lines BL1 and BR1 to the sense amplifier (SA). The output buffer (OB) receives the output signal of the sense amplifier and outputs the data stored in the memory cell as DO.

Next, the word line WL1 and the bit lines BL1,
To write data to the cell connected to BR1, the potential of the word line WL1 is set to H level and the bit line selection signal VYIN1 is driven to H level. Further, either DI or DI ′ is driven to the L level depending on the data to be written. When the potential of the word line WL1 is set to H level, M5 and M6 are turned on. Now suppose M1 and M
Consider a case where 4, 4 are turned on (first stable state) and the write signal DI is driven to the L level. DI to L
When set to the level, the current IYL flows through the resistor RYL and IW
Since L flows to the bit line BL1, the bit line BL1 is forcibly driven to the L level. Therefore, M1, M4 and Q2 in the memory cell are switched from on to off, and
2, M3 and Q1 are switched from off to on. Therefore,
The cell transits to the second stable state and the data is rewritten. In this example, since the memory cell of FIG. 1 is used, the above discussion holds as it is, and even if the parasitic capacitance of the bit line increases with the high integration of SRAM, the time for reading the data of the memory cell is Obviously, it does not increase so much.

[0020]

As described above, according to the present invention, even if the number of memory cells connected to the bit line increases and the parasitic capacitance of the bit line increases with the high integration of SRAM, It is possible to prevent the time for reading the data of the memory cell from increasing as compared with the conventional case. FIG. 14 is a diagram showing the effect of the present invention. This figure shows the word line WL in the circuit of FIG.
After 1 is switched to H level, bit lines BL1, B
It shows the dependence of the delay time until R1 is switched on the number of cells connected to the bit line. The figure also shows the delay time when only the memory cell is replaced with the conventional memory cell shown in FIG. 2 in the circuit of FIG. From this figure, it can be seen that the present invention can reduce the delay time by 30% as compared with the conventional case when the number of cells connected to the bit line is 512.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a seventh embodiment of the present invention.

FIG. 9 is a diagram showing an eighth embodiment of the present invention.

FIG. 10 is a diagram showing a ninth embodiment of the present invention.

FIG. 11 is a diagram showing a tenth embodiment of the present invention.

FIG. 12 is a diagram showing an eleventh embodiment of the present invention.

FIG. 13 is a diagram showing a twelfth embodiment of the present invention.

FIG. 14 is a diagram showing an effect of the present invention.

[Explanation of symbols]

WL, WL1, WL2 ... Word line, BL, BR, BL
1, BR1, BL2, BR2 ... Bit lines, M1 to M8
...... Field effect transistors, Q1 to Q8 ...... Bipolar transistors, VC, VE ...... Power supply.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kanaya 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Yoji Ide 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kenichi Ohata, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Takeshi Kusu, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of memory cells, wherein each of the plurality of memory cells comprises a flip-flop portion formed by connecting first and second field effect transistors to each other. , A first switch whose one end is connected to the first node of the flip-flop section and the other end of which is connected to the first bit line, and one end of which is connected to the second node of the flip-flop section , A transfer gate section having a second switch connected to the second bit line at the other end, a collector connected to the drain of the first field effect transistor, and a base connected to the first field effect transistor. A first bipolar transistor connected to the source of the field effect transistor of, and a collector connected to the drain of the second field effect transistor and a base of The semiconductor integrated circuit characterized by comprising further include a second bipolar transistor connected to the source of the second field effect transistor. 2. A semiconductor integrated circuit having a plurality of memory cells, wherein each of the plurality of memory cells has a drain connected to a first node and a gate connected to a second node. A second field effect transistor having a drain connected to the second node and a gate connected to the first node, and a first end connected to the first node and the other end A flip-flop unit having a first load connected to a first power supply, and a second load having one end connected to the second node and the other end connected to the first power supply. A first switch having one end connected to the first node and the other end connected to a first bit line and turned on / off by a signal on a word line; and one end connected to the second node And the other end is connected to the second bit line And a transfer gate section comprising a second switch which is turned on / off by a signal of the word line, a collector is connected to the first node, and a base is connected to the source of the first field effect transistor. A first bipolar transistor connected to the second power source, a collector connected to the second node, a base connected to the source of the second field effect transistor, and an emitter connected to the second node; 2. A semiconductor integrated circuit further comprising a second bipolar transistor connected to the second power source. 3. The first switch and the second switch respectively include a switch field effect transistor whose gate is connected to the word line, and a collector and a base which are respectively connected to the drain and source of the switch field effect transistor. The semiconductor integrated circuit according to claim 1 or 2, wherein the semiconductor integrated circuit is formed of a bipolar transistor connected to the semiconductor device.