JPH0679054B2 - Logic circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a logic circuit, and more particularly to a logic circuit that facilitates an operation test.

[Technical background of the invention]

FIG. 2 is a block diagram showing the function of a general logic circuit 1. In this way, generally, the logic circuit 1 performs a logical operation based on only the input logical state P and outputs the logical state Q as the operation result.

On the other hand, in the case of a logic circuit generally called a sequential circuit, Q is not uniquely determined based on P, and the logic circuit 1
Will also depend on the internal state of. This internal state is
It is determined by the contents of the logical operation performed by the sequential circuit up to the previous time.

The logic circuit 1 forming a sequential circuit whose output also depends on the internal state as described above is usually composed of a register circuit 2 and an arithmetic circuit 3 as shown in FIG. In this example, the register circuit 2 is composed of registers 2a to 2c and operates by receiving a clock input CL, respectively. From each part of the arithmetic circuit 3, the registers 2a ...
Registration signal lines 4a to 4c are output toward 2c, and conversely,
From the registers 2a to 2c, response signal lines 5a to 5c are output to the respective parts of the arithmetic circuit 3. Therefore, if the logic state R of the register circuit 2 is always the constant state R ₁ ,
Always has the same output Q ₁ is obtained for a certain input P _1, since the logic state R is changed one after another, so that the various output Q for a given input P ₁ is obtained.

Usually, in a manufacturing process of a device having such a logic circuit, a functional test of this logic circuit is performed. In this functional test, it is checked whether or not each transistor forming the logic circuit operates normally.

In the logic circuit shown in FIG. 2 (that is, the logic operation is performed only based on the input P and the output Q does not depend on the internal state), the logic states that the input P should take are sequentially input. It suffices to check whether or not the logic state Q output correspondingly matches the expected one. here,
If the number of digits of the logical state P is k (k = 4 in FIG. 2), there are 2 ^k logical states P. Therefore, to check the operation of all transistors, it is sufficient to repeat the test up to 2 ^k times. However, depending on the circuit configuration of the logic circuit 1, it is possible to check the operation of all the transistors without necessarily performing the test 2 ^k times, so the number of repetitions "2 ^k " is the value when it is the largest. is there.

In the logic circuit of FIG. 2, assuming that the response time from the input of one input P ₁ to the output Q ₁ is Δt, the time T ₀ required for the functional test of the logic circuit 1 as shown in FIG.
Becomes T ₀ ≦ 2 ^k Δt (1) The actual number of repetitions of the functional test varies depending on how to select the logic state P used for this functional test, but generally, the larger the circuit configuration of the logic circuit 1 becomes complicated (that is, the larger 2 ^k becomes), the larger the number of repetitions becomes.

On the other hand, the logic circuit (sequential circuit) as shown in FIG.
In the functional test of FIG. 2, unlike the case of FIG. 2, the logic state Q of the output signal is not determined only by the logic state P that the input signal should take. That is, the logic state Q of the output signal depends not only on the logic state P of the input signal but also on the internal state R of the logic circuit (that is, the state of each register 2). Here, the number of digits of the logic state P is k (k = 4 because there are four input terminals of P in FIG. 3), and the number of registers 2 is n.
If (n = 3 in FIG. 3), the logical state P is 2 ^k and the logical state R is 2 ⁿ . As a result, the total test time T ₁ is given by T ₁ ≦ (2 ^k × 2 ⁿ ) Δt (2).

Here, as described above, since it is only necessary to check the operation of the transistors in the logic circuit in the function test, it is not necessary to test all combinations of the logic states P and R. However, in general, in the logic circuit as shown in FIG. 3, the logic state R must be taken into consideration when determining the logic state P to be used in the function test (the consideration of the logic state R is actually Is performed as the contents and input order of the logic state P), and it is difficult to perform an efficient functional test, that is, to obtain a combination of Ps that can check all transistors with a small number of repetitions. . Therefore, the number of logic test repetitions is generally large, and the total test time T ₁ is longer than in the case of FIG.

[Problems of background technology]

As described above, the sequential circuit as shown in FIG. 3 has a drawback that the time required for the functional test becomes very long.

As a method for solving such a drawback, a test method called a scan path method has been proposed.

FIG. 4 shows an example of a logic circuit equipped with a test device for performing this scan path method. Here, the same components as those of the logic circuit shown in FIG. The characteristic of this circuit is that the registration signal lines 4a to 4c are given to the registers 2a to 2c via the selectors 6a to 6c. Then, the scan-in input S _in for transmitting a signal from the outside to the selector 6a, and the selector 6b, 6c,
Response signal lines 5a and 5b from the registers 5a and 5b are given as inputs, respectively. Selectors 6a-6c have control line CTRL
One of the inputs is selected on the basis of the control signal given from the register and given to the registers 2a to 2c. Also register
Response signal line 5c output from 2c is a scan-out output
It is also taken _out as S _out .

During normal operation of such a logic circuit, selectors 6a-6c
By selecting the registration signal lines 4a to 4c, the overall circuit configuration becomes equivalent to the circuit shown in FIG.

On the other hand, during the test, the selectors 6a to 6c select the opposite side. As a result, the registers 2a to 2c have the selectors 6a to
6c is connected in series to form a shift register that operates in the cycle of the clock CL.
2a to 2c can be set with data given externally via the scan-in input S _in .

Here, in general, when the scan path method is used, the operation of sequentially inputting a predetermined type of logic state P is repeated by shifting the scan-in input S _in one step by the registers 2a to 2c. In many cases, it is possible to check all transistors. Therefore, the number of digits of the logic state P is k (in FIG. 4, since there are four input terminals of P, k
= 4), there are 2 ^k logical states P. Therefore, if the number of registers is set to n (n = 3 in Fig. 4), generally the maximum number of iterations required for a functional test is 2 ^k. n.

Also, with this method, the test of the shift register itself must be performed separately, but this is simply that a predetermined data string is input from the scan-in input S _in and sequentially shifted, and this is taken _out from the scan-out output S _out. All you have to do is look it up.

Therefore, the total test time when the scan path method is adopted
T ₂ is usually T ₂ ≦ (2 ^k n + n) Δt (3).

As described above, in the logic circuit shown in FIG. 4, the content of the external register circuit 2 can be set at the time of the function test, so that the maximum value of the number of repetitions of the function test is larger than that of the logic circuit of FIG. Becomes smaller. Then, in general, it becomes possible to obtain a combination of Ps by which the number of repetitions can be checked for all the transistors, and thus it becomes easy to improve the efficiency of the functional test.

However, in recent years, the functions of logic circuits have become more complicated, and along with this, the number n of registers tends to increase. There are many cases where n is a number such as 100 or 1000. Therefore, the total test time of the logic circuit shown in FIG. 4 is considerably long.

[Object of the Invention]

It is therefore an object of the present invention to provide a logic circuit test method and test apparatus that can further reduce the test time.

[Outline of Invention]

A feature of the present invention is that a register circuit that holds an arbitrary logical state R and an arbitrary logical state P are input, the logical state R held in the register circuit at the time of this input is referred to, and the referenced logical state R In a test device for a logic circuit, which includes a calculation circuit that outputs a logic state Q that is uniquely determined based on the input logic state P, a registration signal line that is output from the calculation circuit to the register circuit, and an external circuit. An external signal line for transmitting a signal from the register circuit, first switching means for selecting one of them and giving it to the register circuit, a response signal line output from the register circuit to the arithmetic circuit, and a registration signal line, By providing a second switching means for selecting one of the two and giving it to the arithmetic circuit and switching the first and second switching means, the arithmetic circuit can be separated from the register circuit and separately tested. To lies in that to be able to shorten the test time.

Embodiments of the Invention The present invention will be described below based on illustrated embodiments. First
The figure shows an example of a logic circuit equipped with a test apparatus according to the present invention. Here, the same components as those of the logic circuit shown in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted (for convenience of description, the number n of registers is two). This circuit has a first selector 7a, 7b and a second selector 8a, 8b. The first selectors 7a and 7b are equivalent to the selectors 6a and 6b in the circuit of FIG. 4, and the description thereof will be omitted. The second selectors 8a and 8b receive the registration signal lines 4a and 4b from the arithmetic circuit 3 and the response signal lines 5a and 5b from the registers 2a and 2b as inputs, and select one of them as an arithmetic circuit. Give to 3. First selector 7a, 7
b performs the selection operation based on the control signal supplied from the control line CTRL1 and the second selectors 8a and 8b perform the selection operation based on the control signal supplied from the control line CTRL2.

Next, the operation of this circuit will be described. Now, when the control line CTRL1 is "0", the first selectors 7a, 7b register signal lines 4a, 4b.
Select, and when “1”, scan-in input S _{in '} Response signal line
5a is selected, and the second selectors 8a and 8b are control lines C
The registration signal lines 4a and 4b are selected when TRL2 is "0", and the response signal lines 5a and 5b are selected when TRL2 is "1". For this purpose, each selector may be configured by a combination of logic gates as shown in FIG. 5, for example.

First, during normal operation of this logic circuit, set CTRL1 to “0”, CTR
Set L2 to “1”. As a result, the logic circuit shown in FIG. 1 becomes equivalent to the logic circuit shown in FIG. 3, and it can be understood that the logic circuit operates normally when the clock CL is applied.

Next, a test is performed. In this case, the test of the arithmetic circuit 3 itself and the test of the register circuit 2 itself are performed separately. To test the arithmetic circuit 3 itself, set CTRL1 to "φ"(Don't Care Condition of "0" or "1").
Set CTRL2 to “0”. As a result, the registration signal lines 4a and 4b from the arithmetic circuit 3 are directly returned to the arithmetic circuit 3 via the second selectors 8a and 8b. That is, the arithmetic circuit 3 performs an arithmetic operation by referring to the internal logical state S instead of referring to the logical state R held in the register circuit 2. Therefore, in the arithmetic circuit 3 of the logic circuit according to this embodiment, the internal logic state S is uniquely determined only by the input P at that time, and the input P and the register 2a in the functional test performed up to the previous time are performed. 2b It is not fixed in relation to the state. Therefore, the logic state Q of the output signal is uniquely determined based on only the logic state P of the input signal at that time. Therefore, in the arithmetic circuit 3, the logic state P
The number of possible states (that is, the maximum value of the number of repetitions required for the functional test of the arithmetic circuit 3) is k in the number of digits of the logical state P.
(In FIG. 1, since there are four P input terminals, k = 4)
2 ^k , which is the same as in the case of the logic circuit shown in FIG.
As described above, in the present embodiment, when considering the combination of the logic states P so that the operation check of all the transistors in the arithmetic circuit 3 can be performed with a small number of repetitions, the value of P or the register input in the previous test is examined. Since it is not necessary to consider the states of 2a and 2b, it is possible to obtain such a combination of logical states P. In addition, when the internal state S is determined, the second selectors 8a and 8b intervene,
Although a certain delay time occurs in the arithmetic circuit 3, the arithmetic circuit 3
Since the total operation time is very short, the influence can be eliminated by appropriately setting the time of the repeating cycle of the test. Also, the clock input CL is not required because the register is not used during this test.

Next, when testing the register circuit 2 itself, CTRL1 is set to "1" and CTRL2 is set to "φ". This allows register 2a
And the register 2b are connected in series to configure a shift register. Therefore, if the clock input CL is given, data is given from the outside through the scan-in input S _in , and this is taken _out from the scan-out output S _out and examined, the register circuit 2
You can do your own test.

Therefore, the total test time T ₃ in the circuit of this embodiment is T ₃ ≦ (2 ^k + n) Δt (4).

Here, 2 ^k · Δt represents the time required to test the arithmetic circuit 3 itself, and n · Δt represents the time required to test the register circuit 2 itself. Comparing equation (4) with equations (2) and (3), when the number n of registers increases, the test method according to the present invention can significantly reduce the maximum time required for the functional test. I understand that

Then, in general, it becomes possible to obtain a combination of Ps by which the number of repetitions can be checked for all the transistors, and thus it becomes easy to improve the efficiency of the functional test.

〔The invention's effect〕

As described above, according to the present invention, in a logic circuit including a register circuit and an arithmetic circuit, both are separated and tested separately, so that a combination of Ps that allows checking of all transistors with a small number of repetitions is obtained. This makes it easier to improve the efficiency of the functional test. Therefore, according to the present invention, the test time can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a logic circuit provided with a test apparatus according to the present invention, FIG. 2 is a block diagram showing the function of a general logic circuit, and FIG. 3 is a conventional circuit diagram having a register circuit and an arithmetic circuit. FIG. 4 is a circuit diagram of a general logic circuit, FIG. 4 is a circuit diagram of a conventional logic circuit having a test function by a scan path method, and FIG. 5 is a circuit diagram showing an example of a selector used in a test apparatus according to the present invention. is there. 1 ... Logic circuit, 2 ... Register circuit, 2a-2c ... Register,
3 ... Arithmetic circuit, 4a-4c ... Registration signal line, 5a-5c ... Response signal line, 6a-6c ... Selector, 7a, 7b ... First selector, 8a, 8b
… Second selector, CL… Clock input, S _in … Scan in input, S _out … Scan out output, CTRL, CTRL1, CTR
L2 ... control line.

Claims (2)

[Claims] 1. A register circuit for holding an arbitrary logical state R and an arbitrary logical state P are input, and at the time of this input, the logical state R held in the register circuit is referred to, and the referred logical state R is referred to. A logical circuit that outputs a logical state Q that is uniquely determined based on the input logical state P and a registration signal line that is output from the arithmetic circuit toward the register circuit. First switching means for selecting one of an external signal line for transmitting a signal from the outside and giving it to the register circuit, a response signal line output from the register circuit to the arithmetic circuit, and the registration signal A second switching means for selecting one of the lines and giving it to the arithmetic circuit, and a logic circuit. 2. A first switching means and a second switching means are each composed of n selectors corresponding to a register circuit composed of n registers, and the first switching means is composed of n selectors.
7. The shift register is formed as a whole by connecting the n registers in series by n selectors that constitute the switching means of FIG.
The logic circuit according to the item.