JPH0677494A - Nonvolatile semiconductor memory element - Google Patents

Abstract

PURPOSE:To increase the speed of the title element in a readout operation and to enhance the reliability of a gate oxide film. CONSTITUTION:A gate oxide film 8 between a floating gate electrode 4 for a memory element and a substrate 1 is formed to be thin in at last a partial region near a source region 2 and to be thicker than the thin region in a partial region excluding the thin region or in the whole region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory, and more particularly to a flash (collective erase type) E ² PROM.
Regarding the structure of the memory device.

[0002]

^2. Description of the Related Art FIG. 10 is a sectional view of a memory element of a conventional flash E ² PROM. Data writing is performed by applying a high voltage to the control gate electrode 5 and the drain region 3 and setting the source region 2 to the GND level. That is, between the drain region 3 and the substrate 1, a voltage sufficient to cause avalanche breakdown at the junction of the drain region 3 is applied, and at the same time, a high voltage is applied to the control gate electrode 5 as well. Of the hot carriers generated by the breakdown, only hot electrons are selectively formed in the thin gate oxide film 8 between the floating gate electrode 4 and the drain region 3.
Then, it is injected into the floating gate electrode 4 by passing through, and the substantial threshold voltage is increased to write data. To erase data, the control gate electrode 5 is at the GND level and the drain region 3 is open or G
This is performed by setting the ND level and applying a high voltage to the source region 2. That is, when a high voltage is applied to the source region 2, the electrons in the floating gate electrode 4 tunnel through the thin gate oxide film 8 between the source region 2 and the floating gate electrode 4 and are emitted to the source region 2.
The substantial threshold voltage returns to the initial state and data is erased.

[0003]

Conventional flash E ²
In the case of a PROM, since the gate oxide film thickness between the floating gate electrode and the substrate is smaller than the gate oxide film thickness between the control gate electrode and the floating gate electrode, the floating gate electrode-substrate capacitance control gate electrode-floating gate electrode Since the ratio of the capacitance to the capacitance is large, when a voltage is applied to the control gate electrode at the time of reading, the voltage applied to the floating gate electrode becomes low, and the current capacity of the memory element is reduced. Therefore, the speed of the memory element is delayed during reading.

Further, since a thin gate oxide film between the floating gate electrode and the substrate is formed over a wide area of the entire channel portion, reliability has deteriorated due to defects in the gate oxide film.

Therefore, in order to solve such a problem, the present invention aims to improve the read speed and the reliability of the gate oxide film.

[0006]

According to the present invention, a floating gate electrode and a control gate electrode are provided, and a writing operation for injecting electrons into the floating gate electrode is performed by hot electrons generated at the end of a drain region.
In a non-volatile semiconductor memory device that performs an erase operation for emitting electrons from the floating gate electrode in a tunnel of a source region, a gate oxide film between the floating gate electrode and the substrate of the non-volatile semiconductor memory device is at least one of the vicinity of the source region. It is characterized in that it is formed thin in the partial region and thicker than the thin region in a part or all of the region except the thin region.

[0007]

According to the above configuration of the present invention, the gate oxide film between the floating gate electrode of the memory element and the substrate is
The thin film is formed in at least a part of the region near the source region, and is formed thick in a part or all of the region except the thin region. Decreases, and when a voltage is applied to the control gate electrode during reading, the voltage applied to the floating gate electrode increases. Since the current flowing in the memory element is proportional to the capacitance between the floating gate electrode and the substrate and the square of the voltage of the floating gate electrode, the current flowing in the memory element eventually increases and the speed at the time of reading the memory element improves. It will be possible. In addition, the area of the thin gate oxide film between the floating gate electrode and the substrate is smaller than the area of the thin gate oxide film between the floating gate electrode and the substrate of the conventional memory device, so that the reliability of the gate oxide film can be improved. Is.

[0008]

1 is a sectional view of a first embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 1 is a sectional view taken along the line AA ′ in FIG. 7. 1 is a substrate, 2 is a source region, 3 is a drain region, 4
Is a floating gate electrode, 5 is a control gate electrode, 6 and 7 are insulating oxide films, and 8 and 9 are gate oxide films. As shown in FIG. 1, the gate oxide film 8 between the floating gate electrode 4 of the memory element and the substrate 1 is formed thin on the source region side and thick on the drain side. This is Figure 7
In, the portion surrounded by the dotted line is shown as a thin gate oxide film region. Therefore, since the space between the floating gate electrode 4 and the substrate 1 is widened on the drain side by this structure, the capacitance between the floating gate electrode 4 and the substrate 1 is reduced, and when a voltage is applied to the control gate electrode during reading, the floating gate electrode The voltage applied to the electrodes increases, and the current flowing through the memory element during reading increases. As a result, the speed of the memory device is improved.

2 to 6 are views showing the first embodiment of the present invention in the order of manufacturing steps. The manufacturing process will be described with reference to FIGS. First, the substrate 1 provided with the insulating oxide film 6
A gate oxide film 8 on top, for example 250 Å gate oxide film 8
Is generated (FIG. 2). Next, the gate oxide film 8 in the dotted line portion shown in FIG. 7 is etched using a resist or the like (FIG. 3). For example, a 100 Å gate oxide film 8 is formed on top of this (FIG. 4). Further, next, a polysilicon 10 to be a floating gate electrode, a next thick gate oxide film 9, for example, a gate oxide film 9 of 350 Å, and a polysilicon 11 to be a control gate electrode are sequentially formed (FIG. 5). Then, except for a part of the polysilicon 10 and 11 to be the floating gate electrode and the control gate electrode and the gate oxide films 8 and 9 thereunder, ions are implanted on the substrate 1 and the drain region 3 is formed.
By forming the source region 2 (FIG. 6) and covering the insulating oxide film 7 on the source region 2, the memory element shown in FIG. 1 can be formed.

Next, a plan view of the second embodiment of the present invention is shown in FIG. In this case, the gate oxide film between the floating gate electrode 4 of the memory element and the substrate is formed thin in only a part of the region near the source region 2 shown by the dotted line and thick in all other regions.

FIG. 9 is a plan view of the third embodiment of the present invention. In this case, the gate oxide film between the floating gate electrode 4 of the memory element and the substrate is thinned in the regions near the source region 2 and the drain region 3 indicated by the dotted lines,
All regions other than this are formed thick.

In any case, since the distance between the floating gate electrode and the substrate is widened, the same effect as the first embodiment can be obtained.

In this embodiment, the embodiment in which the control gate electrode is made of polysilicon has been shown, but the same effect can be obtained even if another material such as polycide is used.

[0014]

As described above, according to the present invention, the gate oxide film between the floating gate electrode and the substrate is thin in at least a part of the region near the source region, and some or all of the gate oxide film except the thin region is formed. By thickening the area,
Since the potential of the floating gate electrode is increased, the speed of reading the memory element can be improved. Moreover, since the potential of the floating gate electrode also increases during writing, the electron injection efficiency is increased and the writing characteristics can be improved. In addition, there is an effect of preventing an erroneous erasing operation (a loss of electrons from the floating gate electrode to the drain region) during a read operation.

Further, since the area of the thin gate oxide film is reduced, the reliability of the gate oxide film in the memory device is improved,
Also, it has become possible to improve the data retention characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

FIG. 6 is a cross-sectional view showing a manufacturing process of the memory element according to the first embodiment of the present invention.

FIG. 7 is a plan view showing the first embodiment of the present invention.

FIG. 8 is a plan view showing a second embodiment of the present invention.

FIG. 9 is a plan view showing a third embodiment of the present invention.

FIG. 10 is a sectional view of a conventional memory device.

[Explanation of symbols]

 1 substrate 2 source region 3 drain region 4 floating gate electrode 5 control gate electrode 6, 7 insulating oxide film 8, 9 gate oxide film 10, 11 polysilicon

Claims (1)

[Claims] 1. An erasing operation comprising a floating gate electrode and a control gate electrode, wherein a writing operation of injecting electrons into the floating gate electrode is performed by hot electrons generated at an end of a drain region, and electrons are emitted from the floating gate electrode. In a non-volatile semiconductor memory device that performs a tunnel in the source region, the gate oxide film between the floating gate electrode and the substrate of the non-volatile semiconductor memory device is thin in at least a part of the region near the source region, and the thin region is excluded. A non-volatile semiconductor memory device, characterized in that a part or all of the region is formed thicker than the thin region.