JPH0676471A - Data reproducing system - Google Patents

Abstract

PURPOSE:To execute a decoding processing by synchronizing a video signal with an audio signal. CONSTITUTION:Multiplexed data which is multiplexed by variable-length- compressing video data and fixed-length-compressing audio data is reproduced in a data reproducing system 10 where a buffer memory means 30 for storing autio data after demultiplexing is provided. A read timing from the buffer memory means 30 for audio data is made to delay for the signal processing time difference required for decoding video data and audio data. Thus, both audio data and video data can be outputted while they are synchronized with each other even if decoding and analog conversion processing time for video data is shorter than decoding and analog conversion processing time for audio data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing system suitable for application to a laser disk reproducing system or the like.

[0002]

2. Description of the Related Art As a method for recording data on a laser disk, there is known a so-called MPEG-2 method in which video data (first information) is variable-length coded and compressed and recorded.

Similarly, as a method of recording audio data (second information), there is known an ATRAC method which is a kind of fixed length compression method adopted in a mini disk or the like.

In this way, a recording method has been proposed in which a video signal is compressed according to the MPEG-2 system, an audio signal is compressed according to the ATRAC system, and multiplexed and recorded as bit stream data (packet system). There is.

[0005]

When such a recording method is used, one of the variable length compression is performed while the other is the fixed length compression process, so that the decoding processing time for decoding the data is reduced. Be different. Since the recorded video data and audio data are often mutually related information, the timings of the decoded video signal and the decoded audio signal must match.

Therefore, in such a data reproducing system, it is necessary to perform special signal processing for adjusting at least the time relationship between the two.

The present invention can be applied to such a case. Data of at least two systems having different decoding processing times are processed in good timing and can be decoded in a state in which the time axis is aligned. It proposes a playback system.

[0008]

In order to solve the above-mentioned problems, according to the present invention, the first information is variable-length compressed and the second information is fixed-length compressed to generate multiplexed data. In the data reproducing system for reproducing, buffer memory means for storing the second information after demultiplexing is provided, and the buffer memory is equal to the signal processing time difference required for demodulating the first information and the second information. It is characterized in that the read timing from the means is delayed.

[0009]

As shown in FIGS. 1 and 2, the system controller 25 is supplied with the video frame signal g output from the video decoder 20. In the example of FIG. 1, the data decoding processing time Dv in the video decoder 20 is almost 1
Since it takes a frame time and the data decoding processing time Da in the audio decoder 21 is about 1/3 frame time, the buffer memory means 30 is provided at a read timing capable of absorbing the decoding processing time difference (Dv-Da). A timing signal h is generated in the system controller 25 to allow the audio data from the.

By doing so, the timing signal h
When audio data having a short signal processing time is read with reference to, the decoding processing timing of video data and the decoding processing timing of audio data can be completely synchronized (matched).

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an example of a data reproducing system according to the present invention is applied to a disk reproducing apparatus using a compact disk (CD) will be described in detail with reference to the drawings.

FIG. 1 is a system diagram showing an example of a data reproducing system 10 according to the present invention, in which a compact disc 11 is multiplexed with video data and audio data in a signal form as described above. It is recorded as bit stream data (packet method).

This multiplexed bit stream data reproduced by the optical pickup device 12 including an amplifier is demodulated by a demodulator 13, and this is subjected to error detection and error correction processing in an error correction circuit (ECC circuit) 14. . When the demodulated bitstream data has an error, an error flag indicating an error state of the data is added to the bitstream data.

The bit stream data demodulated and subjected to the error correction processing is temporarily stored in the memory means 15 functioning as a buffer memory. As the memory means 15, a ring buffer or the like is used.

The demultiplexer 16 decodes the data content of the multiplexed bitstream data a (FIG. 2A) read from the memory means 15 to obtain video data, audio data, synchronization data, system data, etc. Each is separated. Synchronous data is data used for data decoding and the like, and system data is data used for controlling the entire system.

The demultiplexer 16 outputs audio data b (FIG. 2B) including an error flag and video data c (C in FIG. 2), and the video data c is supplied to the video decoder 20. The video decoder 20 is a processing circuit including a video buffer memory, a decoder and a D / A converter, and outputs an analog video signal (D in the figure) subjected to the data decoding process and the D / A conversion process.

The audio data is further output from the demultiplexer 16 as a buffer output e (E in the figure). This buffer output e is once supplied to the audio decoder 21 via the buffer memory means 30 for audio data. To be done.

The audio decoder 21 is provided with decoders 21A, 21B, ... 21N (N = n) corresponding to the number of channels n, each of which performs decoding processing of audio data and its D / A conversion processing. , N channels of analog audio signals f (F in the figure) are output.

The buffer memory means 30 is for outputting an audio signal in synchronization with a video signal.
The frame signal g (G in the figure) for the video signal generated in the video decoder 20 is supplied to the system controller 25, and the read timing signal h (H in the figure) generated after a predetermined time T elapses from the frame signal g. Is generated.

In this example, the data decoding processing time Dv in the video decoder 20 takes about 1 frame, and the data decoding processing time Da in the audio decoder 21 is about 1/3 frame (specifically, about 11. Since it takes 6 msec), if the audio data is read from the buffer memory means 30 after the decoding processing time difference (Dv-Da) has elapsed after the video frame signal was output, the audio signal should be output in synchronization with the video signal. You can Therefore, the above-mentioned predetermined time T is the decoding processing time difference (D
v-Da).

In this way, the read mode of the buffer memory means 30 is controlled by the read timing signal h output with a delay of a predetermined time with respect to the video frame signal. The buffer memory means 30 outputs a detection signal i indicating the buffer memory state as shown in FIG. 2I. When this detection signal i is obtained, it means that the memory area of the buffer memory means 30 is full, and at that time, the write mode of the buffer memory means 30 is prohibited.

FIG. 3 shows a concrete example of the audio data buffer memory means 30. The configuration and processing operation will be described in detail with reference to the timing charts of FIGS. 4 and 5.

The audio data b sent from the demultiplexer 16 has a parallel structure of 9 bits in which 1 bit of an error flag is added to 8 bits of pure audio data. This audio data b is supplied to the D-type latch circuit 32 via the terminal 31 shown in FIG. 3 and is output from the system controller 25 as the write request signal j.
It is latched at the output timing (FIG. 4B).

The write request signal j is output at an appropriate timing when data can be written. The write request signal j is also supplied to the timing controller 34, and when the audio data b is latched, the write start pulse 1 (FIG. 4D) is sent to the write address counter 35, which outputs the write address WA (FIG. 4E). It
The write address counter 35 is reset in the initial state and performs a count-up operation during the counter operation.

At the same time, the select signal p is supplied to the address selector 36 so that the write address counter 35 side is selected in this example. As a result, the write address WA is added to the buffer memory 33, and the latched audio data k (FIG. 4C) is stored in the buffer memory 33. This write operation is repeated each time the write request signal j arrives.

A detection circuit 38 provided in association with the timing controller 34 detects an overflow or underflow in the buffer memory 33.
Therefore, the write address of the write address counter 35 and the read address of the read address counter 37 are supplied to the timing controller 34, and the overflow or underflow of the buffer memory 33 is detected by monitoring the values.

The signal i which has detected the overflow or underflow is supplied to the system controller 25 as described above and used as a control signal for generating a write request signal for the buffer memory 33.

Next, the read mode will be described with reference to FIG.

When the detection signal i is at a high level, that is, when a predetermined amount of data has been accumulated in the buffer memory 33 and the predetermined time T has elapsed from the frame signal g described above, the read timing signal h is changed to the system controller 25. It is already output from.

Upon receiving the read timing signal h, the read start pulse m from the timing controller 34.
(FIGS. 5A and 5B) are output, and the read address counter 37 is operated by this and a predetermined read address RA (FIG.
C) is generated, the address selector 36 is controlled, and the selected read address RA is supplied to the buffer memory 33 (FIGS. 5D and 5E).

As a result, when the predetermined time T elapses, the reading of the audio data stored at the predetermined address is started, and the read audio data q is latched. Since the audio data q is time-division multiplexed for n channels, the latch circuit 4 corresponding to that channel is used.
Audio data corresponding to 0A, 40B, ... 40N are distributed and latched. Therefore, the latch pulses La, Lb, shown in FIGS.
Latch circuit 4 in which data sequentially corresponds to Lc and Ld
0A, 40B, ... 40N (Fig. 5K-
N). FIG. 5 shows a case where 4-channel audio data is latched for simplification of description.

When n channels of audio data are latched, a conversion timing pulse r (FIG. 5O) is output from the timing controller 34, and pure 8-bit audio data among the latched audio data is simultaneously output. It is output and supplied to the parallel / serial conversion circuits 41A, 41B, ... 41N, where it is converted into serial data. Although only the output of the parallel / serial conversion circuit 41A is shown in FIG. 5P, the processing operation is the same in other conversion circuits.

Latch circuits 40A, 40B, ... 40N
In addition to pure 8-bit data, 1-bit data indicating an error flag is D-type latch circuits 42A, 42B ,.
.. is supplied to 42N and latched. This latch operation is also performed simultaneously for the n channels.

The serial-converted pure audio data and the error flag correspond to the corresponding audio decoder 2.
21N are supplied to 1A, 21B, ..., 21N to perform the decoding processing and the D / A conversion processing as described in FIG. 1, and the analog audio signals for n channels are output.

Audio decoders 21A, 21B, ...
The reason why the error flag is supplied to 21N is that the decoding process is not performed when this error flag is supplied.

In the timing controller 34, the process of latching the next audio data read from the buffer memory 33 is continuously performed while the data is being transferred to the parallel / serial conversion circuits 41A, 41B, ... 41N. Audio decoder 21A,
In 21B, ..., 21N, decoding processing and serial conversion processing of audio data are continuously performed, and a continuous analog audio signal is obtained at the output.

When the data decoding processing time in the video decoder 20 is Dv, the data decoding processing time in the audio decoder 21 is Da, the data rate of the audio decoder 21 is Ra (bps), and the number of audio channels is n, the above description is given. The capacity Cb of the buffer memory 33 is Cb = (Dv-Da) * Ra * n.

Dv = 1/30 (sec), Da = 11.6
(Msec) and Ra = 292 kbps, Cb = 50692 (bits). Considering the 1-bit error flag, Cb = 57029 (bits).

When using a type of the buffer memory 33 in which the write operation and the read operation proceed at the same time, the operation timing is controlled so that the write operation and the read operation are alternately performed.

[0040]

As described above, according to the present invention, when reproducing the multiplexed data in which the first information is variable length compressed and the second information is fixed length compressed and the multiplexed data is reproduced,
In order to delay the signal processing timing of the second information having a short signal processing time by the signal processing time difference required to decode the second information and the second information, the read timing of the buffer memory means for storing the second information is set. It was designed to be delayed.

According to this, the read timing of the second information can be synchronized with the read timing of the first information with a relatively simple structure. Therefore, the present invention is extremely suitable for application to a data reproducing system such as a compact disc which simultaneously reproduces two or more pieces of information having different recording modes.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a data reproducing system.

FIG. 2 is a waveform diagram for explaining the operation.

FIG. 3 is a system diagram showing an example of audio data buffer memory means.

FIG. 4 is a waveform diagram for explaining the operation.

FIG. 5 is a waveform diagram for explaining the operation.

[Explanation of symbols]

 10 data reproduction system 11 compact disc 16 demultiplexer 20 video decoder 21 audio decoder 25 system controller 30 buffer memory means 33 buffer memory 34 timing controller 40A-40N latch circuit 41A-40N parallel-serial conversion circuit

Claims (5)

[Claims] 1. A data reproducing system for reproducing multiplexed data in which first information is variable length compressed and second information is fixed length compressed to reproduce multiplexed data, wherein the second information after demultiplexing. And a buffer memory means for storing the data is provided, and the read timing from the buffer memory means is delayed by a signal processing time difference required for decoding the first information and the second information. system. 2. The first information is video data, and the second information is video data.
2. The data reproducing system according to claim 1, wherein audio data is used as the information. 3. The data reproducing system according to claim 1, wherein n channels of audio data are multiplexed. 4. The buffer memory means includes a buffer memory for writing the audio data, a latch means for latching the audio data read from the buffer memory for each channel, and an audio for each channel from the latch means. It has parallel / serial conversion means for converting data into serial data, an audio decoder for decoding serial audio data from the parallel / serial conversion means, and a timing controller for controlling the respective means, and decodes the video data. Is a timing signal that enables the audio data from the buffer memory to be read at a read timing that can absorb the time difference between the processing time required for decoding the audio data and the processing time required for decoding the audio data. The data reproducing system according to claim 1, wherein the data reproducing system is supplied to a timing controller. 5. The decoding processing time of the video data is Dv
(Msec), the decoding processing time of the audio data is Da
(Msec), the data rate of the audio decoder is Ra
(Bps), where n is the number of channels of audio data, the capacity Cb of the buffer memory for the audio data is selected as Cb = (Dv−Da) × Ra × n (bits). Item 4. The data reproduction system according to item 4.