JPH0670161A - Image forming device - Google Patents

Abstract

PURPOSE:To correct the shading at a high speed by calculating the shading correction value by an arithmetic means based on the shading correction coefficient stored in a memory means. CONSTITUTION:A digital copying machine is provided with a scanner part, a laser printer part, a multistage paper feeding unit, and a sorter. A shading correcting circuit is provided with a black memory 1 and a subtractor circuit 3. A correction value memory 2 previously stores the correction coefficient corresponding to each picture element. Thus a multiplier circuit 4 multiplies the stored data by the input data subtracted from the black memory data. As a result, the shading correction is attained. Under such conditions, a high speed operation is required to the circuit 4 and therefore an internal circuit is preferably required to perform the pipeline processing. That is, the shading correcting circuit calculates the shading correction value based on the stored shading correction coefficient. Thus the high speed shading correction is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus including a shading correction circuit.

[0002]

2. Description of the Related Art It is considered that a block diagram of a general scanner circuit is shown in FIG. 11, a diagram for explaining a shading calculation formula is shown in FIG. FIG. 13 is a block diagram of the shading circuit.
, Respectively.

In FIG. 11, 11 is a CCD, 12 is an AD converter, 13 is a shading circuit, 14 is an MTF correction circuit, and 15 is an image processing circuit.

In FIG. 13, the lookup table (L
UT) 19 is the black level data stored in the black memory 16 by the subtraction circuit 18 from the white level data stored in the white memory 17 based on the previously read reference white sheet and the data at that time. The data obtained by subtracting is used as the address information of the random access memory (RAM), and the corrected data corresponding to this address is stored as the RAM data to output the shading correction. Is going.

[0005]

According to this general method, assuming that the data of the white level is 8 bits and the input data subtracted from the black level is 8 bits, the total address of the RAM is 16 bits. Become a bit.

If the corrected output is 8 bits, a large capacity RAM of 64k x 8 bits is required as RAM, and at the same time CC
D High-speed access equivalent to or faster than the operating speed
Requires RAM. For example, to read 400 DPI, A4 size in 0.7 seconds, the CCD operates at about 21MHz.
RAM requires about 40 n sec access time.

As described above, a general shading circuit is
The use of LUTs requires expensive, high-speed, large-capacity RAM.

It is an object of the present invention to provide an image forming apparatus including an inexpensive high speed scanner shading correction circuit.

[0009]

According to the present invention, there is provided a scanner unit for optically scanning a document, a memory unit for storing a shading correction coefficient corresponding to each pixel in the scanning direction of the scanner unit, and the memory. And a shading correction circuit having a calculation means for calculating a correction value relating to shading based on the correction coefficient stored in the means.

[0010]

In the shading correction circuit, the arithmetic means calculates the correction value related to the shading based on the correction coefficient related to the shading stored in the memory means.
The Bull transform block can be replaced with an arithmetic means, and shading correction can be performed at high speed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an image forming apparatus having a shading circuit according to the present invention will be described with reference to the drawings.

FIG. 9 is a cross-sectional view showing the overall construction of a digital copying machine which is an embodiment of an image forming apparatus capable of forming an image on both sides, which is equipped with a shading circuit according to the present invention.

As shown in FIG. 9, a digital copying machine 30 is provided.
The scanner unit 31, the laser printer unit 32, the multi-stage paper feeding unit 33, and the sorter 34 are provided.

The scanner unit 31 includes a document placing table 35 made of transparent glass and a double-sided automatic document feeder (RDF) 36.
And a scanner unit 40.

The multi-stage paper feeding unit 33 includes the first cassette 5
It has the 1st, 2nd cassette 52, the 3rd cassette 53, and the 4th cassette 55 which can be added by selection.

In the multi-stage sheet feeding unit 33, the sheets are fed out one by one from the sheets stored in the cassettes of the respective stages and are conveyed toward the laser printer section 32.

The RDF 36 sets a plurality of originals at one time, automatically feeds the originals one by one to the scanner unit 40, and scans one side or both sides of the original according to the operator's selection. It is configured to be read by the unit 40.

The scanner unit 40 includes a lamp reflector assembly 41 for exposing a document, a plurality of reflection mirrors 43 for guiding a reflected light image from the document to a photoelectric conversion element (CCD) 42, and a reflected light image from the document. It includes a lens 44 for forming an image on the CCD 42.

When scanning a document placed on the document placing table 35, the scanner section 31 is configured to read the document image while the scanner unit 40 moves along the lower surface of the document placing table 35. When the RDF 36 is used, the document image is read while the document is conveyed while the scanner unit 40 is stopped at a predetermined position below the RDF 36.

The image data obtained by reading the original image with the scanner unit 40 is sent to the image processing unit and subjected to various processing, and then temporarily stored in the memory of the image processing unit, and in response to the output instruction. The image data in the memory is supplied to the laser printer section 32 to form an image on the paper.

The laser printer unit 32 includes a manual document tray 45, a laser writing unit 46, and an electrophotographic process unit 47 for forming an image.

The laser writing unit 46 is a semiconductor laser which emits laser light corresponding to image data from the above-mentioned memory, and a polygon mirror which deflects the laser light at a constant angular velocity.
It has an f-θ lens and the like for correcting the laser light deflected at a constant angular velocity so as to be deflected at a constant velocity on the photosensitive drum 48 of the electrophotographic process section 47.

In the electrophotographic process section 47, a charging device, a developing device, a transfer device, a peeling device, a cleaning device, a static eliminator, and a fixing device 49 are arranged around the photosensitive drum 48 according to a known manner. ing.

A conveying path 50 is provided on the downstream side of the fixing device 49 in the conveying direction of the sheet on which the image is to be formed. The conveying path 50 is connected to the sorter 34 and a multi-stage sheet feeding unit. It is branched to a conveyance path 58 leading to 33.

The conveying path 58 is branched in the multi-stage sheet feeding unit 33, and the reversing conveying path 50 is formed as a conveying path after branching.
a and a double-sided / composite transport path 50b are provided.

The reverse conveyance path 50a is a conveyance path for reversing the front and back sides of a sheet in a double-sided copy mode for copying both sides of a document.

The double-sided / composite conveying path 50b is a double-sided copy mode.
In the single-sided synthetic copy mode, the sheet is conveyed from the reverse conveyance path 50a to the image forming position of the photosensitive drum 48, or the image of different originals or the toner of different colors is formed on one side of the sheet to perform the synthetic copy. A conveyance path for conveying the sheet to the image forming apparatus of the photosensitive drum 48 without reversing the sheet.

The multi-stage sheet feeding unit 33 includes a common conveyance path 56, and the common conveyance path 56 includes the first cassette 51 and the second cassette 51.
The sheets from the cassette 52 and the third cassette 53 are carried out toward the electrophotographic process section 47.

The common conveyance path 56 is the electrophotographic process section 47.
On the way to the transport path, it joins the transport path 59 from the fourth cassette 55 and leads to the transport path 60.

The conveying path 60 is a confluence point 62 of the double-sided / composite conveying path 50b and the conveying path 61 from the manual document tray 45.
And the photoconductor drum 48 of the electrophotographic process unit 47
And a transfer device, and a confluence point 62 of these three conveying paths is provided at a position close to the image forming position.

Therefore, in the laser writing unit 46 and the electrophotographic process section 47, the image data read from the above-mentioned memory is stored in the laser writing unit 46.
The laser beam is scanned by the laser to form an electrostatic latent image on the surface of the photosensitive drum 48, and the toner image visualized by the toner is the toner image of the sheet conveyed from the multi-stage sheet feeding unit 33. It is electrostatically transferred and fixed on the surface. The sheet on which the image is thus formed is sent from the fixing device 49 to the sorter 34 via the carrying paths 50 and 57, or is carried to the reverse carrying path 50a via the carrying paths 50 and 58.

Next, the configuration and function of the image processing unit and each control system included in the copying machine 30 will be described.

FIG. 10 is a block diagram of the image processing unit and each control system included in the copying machine 30 of FIG.

The image processing unit included in the copying machine 30 is a memory 73 including an image data input section 70, an image processing section 71, an image data output section 72, a RAM (random access memory) and the like. And an image processing central processing unit (CPU) 74.

The image data input section 70 is a CCD section 70a,
It includes a histogram processing unit 70b and an error diffusion processing unit 70c.

The image data input unit 70 is the CCD 4 shown in FIG.
The image data of the original document read from No. 2 is binarized and converted, and while the histogram is taken as a binary digital amount, the image data is processed by the error diffusion method and stored in the memory 7
3 is configured to be stored once.

That is, in the CCD section 70a, after the analog electric signal corresponding to each pixel density of the image data is A / D converted, MTF correction, black and white correction or gamma correction is performed, and 256 gradations (8 (Bit) digital signal is output to the histogram processing unit 70b.

In the histogram processing section 70b, the digital signal output from the CCD section 70a is added for each pixel density of 256 gradations to obtain density information (histogram data), and if necessary, the obtained histogram. The data is sent to the image processing CPU 74, and is also sent to the error diffusion processing unit 70c as pixel data.

The error diffusion processing unit 70c uses the error diffusion method, which is a kind of pseudo halftone processing, that is, the method of reflecting the binarization error in the binarization judgment of the adjacent pixels.
The 8-bit / pixel digital signal output from the unit 70a is converted into 1-bit (binary), and a redistribution operation for faithfully reproducing the local area density in the original is performed.

The image processing unit 71 includes multi-valued processing units 71a and 71b, a synthesis processing unit 71c, a density conversion processing unit 71d, a scaling processing unit 71e, an image processing unit 71f, an error diffusion processing unit 71g and a compression processing unit 71h. Contains.

The image processing section 71 is a processing section for finally converting the input image data into the image data desired by the operator, and the finally converted output image data is stored in the memory 73. It is configured to be processed by this processing unit until it is stored as a data. However, each of the above-mentioned processing units included in the image processing unit 71 functions as necessary and may not function.

That is, in the multilevel halftoning processing units 71a and 71b, the data binarized by the error diffusion processing unit 70c is converted again into 256 gradations.

In the synthesizing section 71c, a logical operation for each pixel, that is, a logical sum, a logical product, or an exclusive logical sum is selectively performed. The data which is the object of this calculation is the bit data from the pixel data and the pattern generator (PG) stored in the memory 73.

In the density conversion processing unit 71d, the relationship between the input density and the output density is arbitrarily set for the 256 gradation data signal based on a predetermined gradation conversion table.

In the scaling processing unit 71e, pixel data (density value) for the scaled target pixel is obtained by performing interpolation processing with known data that is input according to the instructed scaling ratio. The main scanning is scaled after the sub scanning is scaled.

In the image processing unit 71f, various image processings are performed on the input pixel data, and information collection such as feature extraction can be performed on the data sequence.

The error diffusion processing unit 71g performs the same processing as the error diffusion processing unit 70c of the image data input unit 70.

In the compression processing section 71h, the binary data is compressed by the encoding called run length. Also, image data
Regarding the compression of data, the compression works in the final processing loop when the final output image data is completed.

The image data output unit 72 includes a restoration unit 72a, a multi-value quantization processing unit 72b, an error diffusion processing unit 72c, and a laser output unit 72d.

The image data output unit 72 restores the image data stored in the memory 73 in a compressed state and restores the original 2
It is configured so that it is converted into 56 gradations again, error diffusion of 4-valued data that is a smoother halftone expression than 2-valued data is performed, and the data is transferred to the laser output unit 72d. There is.

Immediately, in the decompression unit 72a, the compression processing unit 71h.
The image data compressed by is restored.

In the multi-value quantization processing section 72b, the image processing section 71
Processing similar to that of the multi-value quantization processing units 71a and 71b is performed. In the error diffusion processing unit 72c, the image data processing unit 70
Processing similar to that of the error diffusion processing unit 70c is performed.

In the laser output section 72d, based on the control signal from the printer control CPU 79, the digital pixel data is output.
Data is converted into a laser on / off signal, and the laser is turned on / off.

The image data input unit 70 and the image data
The data handled by the data output unit 72 is basically stored in the memory 73 in the form of binary data in order to reduce the capacity of the memory 73, but deterioration of the image data is taken into consideration. It is also possible to process in the form of 4-valued data.

FIG. 1 is a block diagram of a shading correction circuit used in an embodiment of the image forming apparatus of the present invention, FIG. 2 is a detailed functional explanatory diagram of the circuit of FIG. 1, and FIGS. 3 to 7 are respective modes. FIG. 4 is a schematic flowchart showing the operating state corresponding to each mode of FIGS. 3 to 7.

The black memory 1 and the subtraction circuit 3 in FIG. 1 are the same as those in FIG. The correction value memory 2 of FIG. 1 stores (stores) the correction coefficient corresponding to each pixel in advance. The data storage procedure will be described with reference to FIGS.

The shading correction can be performed by operating the multiplying circuit 4 on the above-stored data and the input data subtracted by the black memory data. Since high speed operation is required in the multiplication circuit 4, it is preferable to perform pipeline processing as an internal circuit.

Therefore, in the general circuit, the LUT and the subtraction circuit configuration of the two memories and the RAM can be replaced with the two memories, the subtraction circuit and the multiplication circuit configuration in the embodiment of the present invention. The hardware can be further simplified by forming the gate array except for the memory.

FIG. 2 is an expanded view for explaining the basic function based on the block diagram of FIG. 1, and FIG. 3 is a view for explaining the operation procedure for each function mode of FIG.

The switch (SW) 5 of the black memory 1 in FIG. 2 stores the input data as black level data in the black memory 1 (contact a is ON), and when the shading operation is performed during the actual festival. This is a changeover switch when the black data is output to subtract the black level data from the data (contact b is on).

The switch (SW) 6 reads the reference white original and stores it as white level data in the correction value memory 2 (contact b is ON), and the actual shading operation (contact a is ON).
Is a switch for switching between.

The switch (SW) 7 stores the white level data in the correction value memory 2 (contact a is ON), transfers the white level data to the CPU, or the CPU stores the correction coefficient in the correction value memory. This is a changeover switch when writing (contact b is on).

The switch (SW) 8 outputs the data of the correction value memory 2 to the CPU or when the white level data is written in the correction memory 2 (a contact is ON) and when the shading is actually operated. This switch is used to output data to the multiplication circuit (contact b is on).

The subtraction circuit 3 outputs Z when the inputs are X and Y.
Computes Z = Y-X. When the input of the multiplication circuit 4 is V, U, the output W is W = V x U.

Next, the actual operation will be described with reference to FIGS.

First, the operation of storing the shading black data in the black memory 1 is performed. In FIG. 3, switch 5
The contact a of is closed and the input data DBn is stored in the black memory 1. Of course, the CCD power supply is turned off and the black level is input. Although not shown in the figure, in order to stabilize the memory data, it is possible to repeatedly read data for several lives and store the average data in the black memory 1 as a black level. . In this way, the black level data is stored in the black memory 1.

Next, the operation of reading the white reference original data for shading correction and temporarily storing it in the correction value memory 2 will be described.

In FIG. 4, the switch 5 is the b contact, the switch 6 is the b contact, the switch 7 is the a contact, and the switch 8 is the a contact.
Connect to the contact side. The CCD original is a white reference original with 100% white density, and the CCD light source is turned on to stabilize the light intensity sufficiently. Then, in this state, the input data D _Wn is black-corrected by the subtraction circuit, and the result is stored in the correction value memory 2 as a white level.

The black level voltage is D _Bn and the white level voltage is D Wn
Then, the white level voltage stored in the correction value memory 2 becomes D
It is represented by _Wn -D _B n.

This completes the storage of the white level in the correction value memory 2. Then turn off the CCD light source.

Next, the operation for calculating the correction value is performed.

As shown in FIG. 5, the white level data stored in the correction value memory 2 is transferred to the CPU with the switch 7 as the b contact and the switch 8 as the a contact. In the figure, CP
U is omitted because it is known. Next, the data sent to the CPU is stored in the white work RAM and the next correction coefficient is calculated based on this data.

If the coefficient is α, αn = 255 / (D _Wn-
D _Bn ). Here, 255 of the numerator is assumed to be when the CCD data is 8 bits (255), but it may be arbitrary depending on the number of bits of the CCD data. α is usually a numerical value of 1 or more. Any significant digit may be used, but it affects accuracy. In this embodiment, the integer part is 2 bits, and the fractional part or less is 6 bits, ie, 8 bits in total. This is the end of the correction value calculation by the CPU.

Next, the correction value is stored in the correction memory 2 according to FIG. The switches 7 and 8 are in the same state as in FIG. 5, but the signal flow is in the reverse direction from the CPU to the correction value memory 2. Although not shown, hardware is used to reverse the direction.
The correction value is stored in the correction value memory 2 by transferring the data. As described above, the data is stored in the black memory 1 and the correction value memory 2.
Since each of the data has been completed, the actual operation is performed next.

In FIG. 7, the switch 5 is connected to the b contact, the switch 6 is connected to the a contact, and the black memory 1 is connected to the input of the subtraction circuit 3 and the correction value memory 2 is also connected to the multiplication circuit 4 side. The light source of the CCD lights up and when it is in a sufficiently stable state, scanning of the original document starts. That is, the image de the input unit - inputs the data D _n. The output signal of the subtraction circuit 3 becomes D _n −D _Bn .
At the output of the multiplication circuit 4, (D _n -D _Bn ) x (α _n ) = (D _n
-D _Bn ) x 255 / (D _Wn -D _Bn ) is output and the shading correction operates.

The operation in each mode has been described above with reference to the figure showing the function of the hardware.

Next, the above operation will be described for each step, that is, for each mode with reference to the flowchart of FIG.

In the figure, the black level is read. That is, set the switch (SW) 5 to the a contact, and set C
The CCD black level voltage DBn is stored in the black memory 1 while the CD light source is OFF (8-1). Next, the white level is read. That is, set the switches (SW) 5 and 6 to the b contact and the switches (SW) 7 and 8 to the a contact, turn on the optical lamp and turn on the CCD light source, and set the voltage D _Wn to the correction value memory 2
After that, the CCD power is turned off (8-2). Then, the white level data is transferred to the CPU. That is, the switch 7 is set to the b contact and the switch 8 is set to the a contact, and the data of the correction value memory 2 is transferred to the CPU (8-3). Further, with the switch 7 set to the b contact and the switch 8 set to the a contact, the CPU calculates the correction value and stores the calculation result in the correction value memory 2 (8-4). With the above, preparation for shading is completed, and reading of an actual document is started. Step 8-
As shown in 5, switch 5 to contact b and switch 6 to contact a.
At the contact, set the switch 8 to the contact b, input the actual image data to the input section, perform the shading operation, and CCD.
After the light source is turned on and stable, the original reading of the original starts. At the end of scanning the original, the light source is turned off and the shading operation is completed (8-6).

The description of the embodiment has been completed above, but the following is omitted because it is known as hardware.

Although each hard block in the embodiment is not shown, it is assumed that a predetermined control is performed under the control of the CPU. Also, when performing shading,
Signal clocks and main scan sync signals are omitted.

Further, although the detailed structure of the memory is not described in the present embodiment, it is possible to use not only the S-RAM but also the D-RAM memory or the FIFO memory. Effective in simplifying management.

A FIFO memory having a D-RAM structure can be realized at the lowest cost.

[0083] The correction value data of the present embodiment - data are Using this exponential notation method, (e.g., 2 ⁰ +2 ^-1 +2 ^-2 = 1.7
5) A hardware multiplication circuit can be easily realized by a data shifter and an adder.

[0084]

The shading correction circuit replaces the table conversion block with the arithmetic means because the arithmetic means calculates the shading correction value based on the shading correction coefficient stored in the memory means. Therefore, the shading correction can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a shading correction circuit used in an embodiment of an image forming apparatus of the present invention.

FIG. 2 is a detailed explanatory diagram of the circuit of FIG.

FIG. 3 is a diagram showing a first circuit of a shading correction circuit.

FIG. 4 is a diagram showing a second circuit of the shading correction circuit.

FIG. 5 is a diagram showing a third circuit of the shading correction circuit.

FIG. 6 is a diagram showing a fourth circuit of the shading correction circuit.

FIG. 7 is a diagram showing a fifth circuit of the shading correction circuit.

FIG. 8 is a schematic flowchart illustrating the operation of each circuit of FIGS. 3 to 7.

FIG. 9 is a sectional view showing the overall configuration of an embodiment of the image forming apparatus of the present invention.

10 is a block diagram of an image processing unit and each control system included in the embodiment of FIG.

FIG. 11 is a block diagram of a general scanner circuit.

FIG. 12 is a diagram for explaining a formula for calculating the shading of the circuit of FIG. 11;

FIG. 13 is a block diagram of a general shading circuit.

[Explanation of symbols]

 1 black memory 2 correction value memory 3 subtraction circuit 4 multiplication circuit 5, 6, 7, 8 switch 30 digital copying machine 70 image data input unit 71 image processing unit 72 image data output unit 73 memory 74 image processing CPU

Claims (1)

[Claims] 1. A scanner unit for optically scanning a document,
A memory unit that stores a correction coefficient related to shading corresponding to each pixel in the scanning direction of the scanner unit, and a calculation unit that calculates a correction value related to shading based on the correction coefficient stored in the memory unit. An image forming apparatus including a ding correction circuit.