JPH0667775A - Interface circuit - Google Patents

Abstract

PURPOSE:To switch the logical amplitude of a signal by switching a mode and to reduce a noise by moving the difference of logical amplitude between a high level and a low level variable, and enabling a reference voltage to be adjusted at a reception circuit. CONSTITUTION:The constant current circuit 1A of a transmission circuit SE is comprised of two transistors (T121, T122). Both transistors T121, T122 are turned on when it is desired to increase the difference of logical amplitude, and only the transistor on one side is turned on when it is not desired. The reference voltage generation circuit 5A of the reception circuit RE is also used by switching between increasing/decreasing of the difference of reference voltage by turning on both transistors T281, T282 or only the transistor on one side according to the increasing or decreasing. Thereby, it is possible to perform transmission with small logical amplitude in the transmission of short distance and with large logical amplitude in the transmission of long distance and to reduce the noise when the logical amplitude is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit which operates at high speed and can be connected to a conventional device and has low power supply noise.

[0002]

2. Description of the Related Art FIG. 11 shows an example of a conventional transmission / reception circuit of an ECL interface. FIG. 12 is a diagram showing H level (high level “1” logic) and L level (low level “0” logic) of the interface signal of FIG. 11. The operation principle of the conventional interface circuit will be described with reference to FIGS. 11 and 12.

The transmitting circuit SE of FIG. 11 is composed of resistors R ₁₁ and R
₁₃ , a current switching circuit (current switch) including the transistors T ₁₁ and T ₁₃ and the constant current circuit 1, and a transistor T _{14 of the} emitter follower circuit. In addition,
The constant current circuit 1 includes a transistor T ₁₂ and a resistor R ₁₂ , and the current switching circuit 2 includes a constant current circuit 1 and resistors R ₁₁ and R 12.
₁₂ , transistors T ₁₁ , T _{12 and the} like. The output buffer 3 is composed of the current switching circuit 2 and the transistor T ₁₄ . In the constant current circuit 1, a constant current of i _CCS is flowing, and one of the transistors D ₁₁ and T ₁₃ is fed by the voltage of the data D ₁ and its inverted data D ₂ which are input to the bases of the transistors T ₁₁ and T _13. Turns on.
A current flows through the resistor connected to the collector through the transistor that is turned on. This current is i _CCS and is constant. Now, assuming that the data D ₁ has a potential sufficiently higher than the data D ₂ , the transistor T ₁₃ is turned on and the current i _CCS flows through the resistor R ₁₃ . On the other hand, the transistor T ₁₁
Is OFF, no current flows through the resistor R ₁₁ , and the potential is V _CC . On the transmission line L, -0.8 V (H level) level-shifted by the transistor T ₁₄ is output. This is the H level shown in FIG. On the contrary, if the data D ₁ has a potential sufficiently lower than the data D ₂ , the transistor T ₁₁
Is turned on, and a current of i _CCS flows through the resistor R ₁₁ . In this case, the voltage drops by R ₁₁ · i _CSS , and the transmission line L
Further level-shifted, -1.6 V (L level) is generated. This is the L level in FIG.

In the constant current circuit 1, a constant voltage is applied between V _{CS and} V _EE , and the current flowing through the resistor R ₁₂ is {(V _CC -V
_EE ) −V _BE } / R ₁₂ is constant. Here, V _BE is the base-emitter voltage of the transistor T ₁₂ .

The receiving circuit RE includes a transistor T ₂₁ ,
An input buffer 4 composed of T ₂₂ , T ₂₃ , resistors R ₂₂ , R ₂₃ , R ₂₄ , transistors T ₂₈ , T ₂₉ , a resistor R ₂₅ ,
The reference voltage generating circuit 5 is composed of R ₂₆ and R ₂₇ .

In the receiving circuit RE, the signal is terminated to a voltage V _TT by a terminating resistor R ₂₁ of 50Ω (matching the characteristic impedance of the transmission line L). The H level and L level signals shown in FIG. 12 are input to the base of the transistor T ₂₁ .
The intermediate potential V _BB is applied to the base of the opposing transistor T ₂₃ . Resistors R ₂₂ , R ₂₄ , transistor T ₂₁ ,
The input buffer 4 composed of T ₂₃ and T ₂₂ and R ₂₃ forming a constant current source operates as a current switching circuit (current switch), and switches the reference voltage V _BB depending on whether the input signal exceeds the reference voltage V _BB . Reference numeral 5 is an example of a reference voltage generating circuit, which reduces the voltage drop of the resistor R ₂₅ to the transistor T _29.
Then, the reference voltage V _BB of intermediate potential is generated by level-shifting through the emitter follower.

[0007]

The ECL interface shown in FIGS. 11 and 12 is widely used as a general-purpose high-speed electrical interface. However, the amplitude of the signal is about 0.8 V, and a high-speed current of 16 mA flows in the transmission line L of 50Ω. Further, this high-speed current change of 16 mA is transmitted from the transmitting side through the transmission line L, flows through the terminating resistor R ₂₁ on the receiving side, and flows into the V _TT voltage supply layer. Therefore, high-speed and high-density multiple I / Os can be achieved with high-density interconnection and bare chip mounting technology.
In a system that operates at the same time, noise generated in the power supply is a big problem.

The object of the present invention is to achieve 0.8V even with a short distance interconnection in the conventional ECL interface.
In addition to solving the problem that a power supply noise was generated greatly when transmitting and receiving a (16 mA) signal, I / O and interconnections with a reduced logic amplitude and a reduced signal current, as necessary. It is to provide an interface circuit.

[0009]

An interface circuit according to the present invention is configured such that a difference in logical amplitude between a high level and a low level is variable in a transmission circuit, and a reference voltage of a reception circuit is adjustable. Is.

Further, a means for controlling the current of the current switching circuit of the output buffer using the ECL logic is used as a structure for making the difference in the logical amplitude of the transmission circuit variable.

Further, as a structure for adjusting the reference voltage of the receiving circuit, a plurality of constant current sources are provided and a current obtained by selecting a predetermined number of constant current sources is used.

[0012]

In the present invention, in the case of short-distance interconnection, the signal from the transmitting circuit is transmitted with a small difference in logical amplitude between the low level and the high level, and the receiving circuit uses the reference voltage. Change it accordingly and judge low level and high level.

Further, according to the present invention, by controlling the current of the current switching circuit of the output buffer using the ECL logic of the transmission circuit, the difference in logic amplitude between the low level and the high level can be adjusted.

Further, according to the present invention, a predetermined current is obtained by selecting the number of constant current sources of the receiving circuit, and a predetermined reference voltage is obtained by using this to discriminate between low level and high level. To do.

The main feature of the present invention is that the interface condition, that is, the logical amplitude of the signal can be switched by switching the mode, and that the signal can be transmitted / received to / from the conventional ECL interface. The conventional technology is that the logic amplitude of the device can be changed, a logic with a small amplitude can be used between the same elements, and the reverse reception is possible even for the ECL interface of the conventional system. different.

[0016]

【Example】

<Embodiment 1> FIG. 1 is a diagram for explaining a first embodiment of the present invention, in which 1A is a constant current circuit capable of varying current, 1-1
Is a logic amplitude control terminal for controlling a constant current value, 5A is a reference voltage (V _BB ) generating circuit whose voltage level can be varied, and 5-1 is a reference control terminal for controlling a reference voltage level. In FIG. 1, the frames corresponding to the current switching circuit 2, the output buffer 3 and the input buffer 4 shown in FIG. 11 are omitted.

The operating principle of the first embodiment of the present invention will be described with reference to FIG. In the constant current circuit 1A, the voltage V _CS is applied to the transistor T by the logic amplitude control terminal 1-1.
_When applied to the bases of ₁₂₁ and T ₁₂₂ , the current i ₁ flows through both the transistor T ₁₂₁ and the transistor T _122, and the current at that time is designed as (1/2) i _CSS . That is, i ₁ = i _CSS . In this case, the logic amplitude of the signal is the collector load resistor R ₁₁ of the current switch.
Product R ₁₁ · i _CSS between the resistance value of the current and the resistor R ₁₁ flowing
Becomes Designed as R ₁₁ · i _CSS = 0.8V in this condition, to realize the ECL interface. On the other hand, if only the transistor T ₁₂₁ is connected to the voltage V _CS by the logic amplitude control terminal 1-1, the current is (1/2) i _CSS = i
_It becomes ₁ , which is half the current compared to the previous connection state. At this time, for stabilization, it is desirable to connect the base of the other transistor T _{122 to} the voltage V _EE . The current i ₁ is (1 /
2) With i _CSS , the logical amplitude is halved, and R ₁₁ ·
(1/2) i _CSS = 0.4V. In this way, the logical amplitude of the transmission circuit SE can be halved.

In this embodiment, the transistors T ₁₂₁ , T
_It was equipped with two of ₁₂₂ , and the current of only (1/2) i _CSS was sent to each, but it is equipped with K transistors (1 / K)
With i _CSS , it is easily conceivable that the logical amplitude can be reduced to 1 / K. Similarly, in the reference voltage generation circuit 5A of the reception circuit RE, the transistors _T281 , T are used as current sources.
₂₈₂ and two resistors R ₂₆ and R ₂₈ are provided, and both transistors T are connected by the reference control terminal 5-1.
_{It is} possible to control the case where the voltage V _CS is supplied to ₂₈₁ , T ₂₈₂ and the case where the voltage V _CS is supplied to one of them. Therefore, the current can be halved, and if the current flowing through the resistor R ₂₅ is i _CSR , then R ₂₅ · i _CSR = 0.4V, R ₂₅ · (1/2) i _CSS
= 0.2V, ECL reference voltage -1.2V, small amplitude logic (amplitude 0.4V)
The reference voltage of -1 V can be supplied to each reference terminal.

FIGS. 2A and 2B show respective voltages (H and L) and reference voltages V _BB and V _BB 'in mode 1 (ECL interface) and mode 2 (small amplitude interface). As described above, it is obvious that the reference voltages V _BB and V _BB ′ can also be controlled by providing the constant current circuit 1A with k transistors. <Embodiment 2> FIG. 3 is a diagram for explaining the second embodiment of the present invention, in which the logical amplitude on the transmitting side is halved.
Mode 1 (EC
L level), both resistors R ₁₄ and R ₁₂ have voltage V
Connect to _EE . On the other hand, in mode 2 (small amplitude level), only one of the resistors R ₁₂ or R ₁₄ is connected to the voltage V _EE ,
Cut the current in half. As a result, the value of the current i ₁ can be halved, and the logic amplitude can be reduced as in the first embodiment. <Third Embodiment> FIG. 4 is a diagram for explaining a third embodiment of the present invention. In this embodiment, a resistor R is used as the constant current circuit 1C.
₁₂₁ and R ₁₄₁ are connected in series, and this resistor R ₁₄₁ is electrically inserted and removed. Mode 1 (ECL
(Level), the logic amplitude control terminals 1-1 control the voltage V _EE to be connected to the resistor R ₁₂₁ . On the other hand, in mode 2 (small amplitude level), the resistor R ₁₄₁ is connected to the voltage V _EE so that the current i ₁ becomes 1/2. As a result, a logical amplitude of 1/2 is realized as in the first embodiment. <Fourth Embodiment> FIG. 5 is a diagram for explaining a fourth embodiment of the present invention. In the present embodiment, the base voltage of the transistor T ₁₂ is switched as the constant current circuit 1D. V _CS-1 is, for example, V _EE +1.6 V, V _CS-2 is V _EE +
It is set to 1.2 V (more accurately, logical amplitude + V _BE ). When the base of the transistor T ₁₂ is set to V _CS- 1 by controlling the logic amplitude control terminal 1-1, the current i ₁ is (V _CS-1 −V _BE ) / R ₁₂ = 0.8V / R ₁₂ And V
When connected to _CS-2 (V _CS-2 over _{V BE) / R 12 = 0.4V} /
It becomes R ₁₂ . As a result, the current i ₁ can be halved,
The resistance amplitude can be halved. <Fifth Embodiment> FIG. 6 is a diagram for explaining a fifth embodiment of the present invention. In this embodiment, the load resistors _R111 and _R112 are switched. In FIG. 6, the current i ₁ is constant and the load resistors R ₁₁₁ and R ₁₁₂ that determine the logic amplitude are determined.
Is controlled by the logical amplitude control terminal 1-1. <Embodiment 6> FIG. 7 is a diagram for explaining a sixth embodiment of the present invention, in which the configuration of the reference voltage generating circuit 5A of FIG. 1 is switched between two resistors R ₂₆ and R ₂₈ . It is the figure which made the reference voltage generation circuit 5B. The reference control terminal 5-1 determines the current i ₂ flowing through the resistor R ₂₈ . Designed as R ₂₅ · i ₂ = 0.4V, V
_BB = -1.2V is obtained (mode 1). On the other hand, mode 2
In (small amplitude logic), the voltage V _EE is connected to either one of the resistors R _{26 and} R ₂₈ , the current i ₂ is halved, and R ₂₅
(½) i ₂ = 0.2V is set and V _BB ′ = −1.0V is obtained. <Embodiment 7> FIG. 8 is a diagram for explaining a seventh embodiment of the present invention. In this embodiment, two resistors R ₂₆₁ and R _{281 are used.}
By using a resistor so that the resistor R ₂₈₁ can be electrically inserted and removed.
This is a reference voltage generation circuit 5C. Mode 1 (EC
The current i ₂ is controlled by connecting the voltage V _EE to the resistor R ₂₆₁ in the L level) and connecting the voltage V _EE to the resistor R ₂₈₁ in the mode 2 (small amplitude level). The subsequent operation is similar to that of the sixth embodiment. <Embodiment 8> FIG. 9 is a diagram for explaining an eighth embodiment of the present invention, which uses a reference voltage generating circuit 5D in which two load resistors R ₂₅₁ and R ₂₅₂ are switched. . Reference control terminal 5 - 1 by a mode 1 (ECL levels) is connected with a voltage V _CC in only the load resistor R _252, connecting the voltage V _CC to the mode 2, (small amplitude level) load resistors R ₂₅₁ and R ₂₅₂ To do. As a result, the load resistor can be changed and the voltage V _BB can be changed under the constant current i ₂ . In addition, the load resistor R ₂₅₁ ,
The method of connecting R ₂₅₂ in series and connecting to the voltage V _CC in the middle can be easily analogized. In addition, the voltage V _{CS is set} to V _CS-1 , V _CS-2
Then, it is obvious that the current i ₂ can be controlled as in the fourth embodiment. Further, it is obvious that the present invention can be applied to an interface that secures a logic level margin, with a small amplitude when used for balanced transmission (differential logic) and a large amplitude when used for unbalanced transmission (single-phase logic).

Assuming that the logical amplitude is V ₁ , the current flowing from the 50Ω termination resistor to the power supply layer (printed circuit board or the like) having the voltage V _TT is i ₁ = V _1/50 . If the logical amplitude is ½, the current that flows will also be ½ i _l . When the impedance of the power source layer and Z, if the amplitude of the noise of the ECL number of highway operating simultaneously as m, whereas V noise = m · i _l · Z, in the case of small amplitude, V noise = m · ( 1/2) i _l · Z. In other words, the noise level of the power supply layer has a logical amplitude of 1
If it is / k, it is known that it becomes 1 / k, and there is an advantage that higher density can be realized. Further, there is an advantage that it can interface with the ECL for transmission by switching the mode.

FIG. 10 is an explanatory diagram of an electronic circuit board 6 on which an LSI 7 having an interface circuit according to the present invention is mounted.
The signal in the electronic circuit board 6 uses mode 2, that is, a small amplitude, to reduce the noise in the power supply layer. Further, for the outside, a mode 1 (ECL level) that allows connection with a commercially available device or another system is used. Such a system can be adopted in the system, which is advantageous in terms of noise in the power supply layer.

[0022]

As described in detail above, according to the present invention, the difference in logical amplitude between the high level and the low level is variable in the transmitting circuit, and the reference voltage of the receiving circuit is adjustable. , The logical amplitude of the signal can be switched by switching the mode, and noise can be reduced.

Further, in the present invention, since the means for controlling the current of the current switching circuit of the output buffer using the ECL logic is provided as a structure for varying the difference in logical amplitude of the transmitting circuit, the logic on the transmitting side is provided. Amplitude can be switched easily and reliably.

Furthermore, the present invention further has a plurality of constant current sources as a structure for adjusting the reference voltage of the receiving circuit, and a required reference is obtained by using the current obtained by a predetermined number of constant current sources. Since the voltage is obtained, the reference voltage on the receiving side can be obtained easily and reliably.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a logical amplitude obtained by the present invention.

FIG. 3 is a circuit diagram of a main part showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a main part showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a main part showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of an essential part showing a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part showing a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram of a main part showing a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram of an essential part showing an eighth embodiment of the present invention.

FIG. 10 is a diagram for explaining an example of use of the present invention.

FIG. 11 is a diagram showing a conventional interface circuit.

FIG. 12 is a diagram for explaining a conventionally used logic amplitude.

[Explanation of symbols]

1 Constant current circuit 1-1 Logic amplitude control terminal 2 Current switching circuit 3 Output buffer 4 Input buffer 5 Reference voltage generation circuit 5-1 Reference control terminal R Resistor T transistor V _CC voltage V _TT voltage V _EE voltage SE Transmission circuit RE Receiver circuit

Claims (3)

[Claims] 1. A binary signal consisting of a high level and a low level transmits a signal from a transmission circuit to a reception circuit, and compares the voltage of the signal received by the reception circuit with a reference voltage to determine whether it is a high level or a low level. In the digital interface circuit for discriminating between the two, the interface circuit is configured such that the difference between the high-level and the low-level logic amplitude is variable, and the reference voltage of the receiver circuit is adjustable. . 2. The interface according to claim 1, wherein a means for controlling a current of a current switching circuit of an output buffer using ECL logic is used as a structure for varying a difference in logical amplitude of a transmission circuit. circuit. 3. A structure for adjusting a reference voltage of a receiving circuit, comprising a plurality of constant current sources, wherein a current obtained by selecting a predetermined number of constant current sources is used. The interface circuit according to item 1.