JPH0666946B2 - High definition television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of invention C Conventional technology D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Example (Fig. 1) G ₁ field Description of inner interpolation section (Figs. 2 and 3) Description of G ₂ 4 inter-field interpolation section (Figs. 2 and 4) Description of G ₃ motion amount detection section (Fig. 5) G ₄ double speed conversion section (FIGS. 6 and 7) G ₅ Description of motion correction H Effect of the invention A Industrial field of application The present invention provides a 4-field unit screen that is band-compressed by sub-Nyquist sampling and interlaced with each other. The present invention relates to a high-definition television receiver using a television signal that is sequentially transmitted, that is, a so-called MUSE type television signal.

B Outline of the Invention The present invention provides a high-definition television receiver that uses a so-called MUSE-type television signal, in which the vertical and horizontal frequencies are doubled and the still image portion and the moving image portion are different. The image quality is improved by performing motion adaptive interpolation processing.

C Conventional Technology A high-definition television is, for example, capable of displaying 1125 lines / 60 fields, an interlace ratio of 2: 1 and an aspect ratio of 5: 3. / 60 field, interlace ratio 2: 1,
It has about four times as much information as the aspect ratio 4: 3). Therefore, while it is said that conventional televisions do not detect interference at a visual distance of 7H (H is the screen height) or more, high-definition television must detect interference at a visual distance of 3H or more. Has been done.

D Problems to be Solved by the Invention However, high-definition television still detects various disturbances such as raster disturbance, line flicker, and large-area flicker (60Hz) at a viewing distance of 3H or less, although the degree is low. To be done. In particular, large-area flicker becomes a problem as the screen becomes larger and the brightness becomes higher.

FIG. 11 shows the scanning line structure of a high-definition television. The solid line shows the scanning lines in the odd field and the broken line shows the scanning lines in the even field. Further, FIG. 12 shows the scanning line viewed in the time direction. Fig. 13 shows the high-definition television signal (the one with little movement) displayed on the two-dimensional (vertical-time) frequency plane, which is 562.5cph, 30Hz.
There is a folding component around the point of. This component is not normally perceived at a visual distance of 3H or more, but is perceived as an interfering component at a visual distance of 3H or less.

In FIG. 13, “◯” indicates a direct turnaround point.

By the way, satellite broadcasting is currently performed in the 12 GHz band and has a transmission band of 27 MHz per channel. On the other hand, a normal high definition television signal has a signal band of 20 MHz. If the FM modulation method with a constant carrier power suitable for analog transmission is used, the transmission band needs to be about three times as large as the base band or more. Therefore, a normal high-definition television signal requires two or more channels of satellite broadcasting. Therefore, a kind of band compression system called the so-called MUSE (Multiple Sub-Nyquist Sampling Encoding) system has been developed. For example, a normal high-definition television signal having a band of 20 MHz is used as a television signal of about 8 MHz, and satellite broadcasting 1 channel It became possible to transmit in.

This MUSE type television signal is formed as follows. First, high-definition television signals (R, G,
A luminance signal Y, a wideband color signal C _W , and a narrowband color signal C _N are obtained from the B primary color signal) (shown in FIGS. 14A, 14B, and 14C). here,
The signals Y, C _W and C _N are obtained from the R, G and B primary color signals by the conversion matrix of the following equation.

Next, the color signals C _W and C _N are time-axis-compressed to 1/4 and time-axis multiplexed line-sequentially in the horizontal blanking period of the luminance signal Y.
Obtain the I signal (illustrated in Figure 14D).

Next, this TCI signal is sampled at a clock of 64 MHz (the sampling points are indicated by "□" in FIG. 15).

Next, sub-Nyquist sampling, which makes a cycle of four fields, is performed with a clock of 16 MHz, and the signal band is less than 8 MHz.
The E TCI signal, that is, the above-mentioned MUSE type television signal is formed. In Figure 15, "1", "2",
The sampling points indicated by "3" and "4" are the sampling points of the first field, the second field, the third field, and the fourth field, respectively, and they have a dot interlacing relationship with each other.

Incidentally, it is expected that in a television receiver using such a MUSE-type television signal, different interpolation processing will be performed for the still image portion and the moving image portion, and image display by interlaced scanning will be performed. .

The present invention is intended to satisfactorily prevent various interferences as described above in a high-definition television receiver using such a MUSE type television signal.

E Means for Solving Problems (FIG. 1) In order to solve the above problems, the present invention converts a received MUSE type television signal into a television signal whose vertical and horizontal frequencies are each doubled. Double speed conversion means (9),
(12) and (15) are provided, and an image is displayed by the converted signal from this. Further, the double speed converting means has an inter-field interpolating means (12) and an inter-field interpolating means (9), and the output of the means (14) for detecting the movement of the image is an inter-four-field interpolating means (12). And field interpolation means (9)
To control. Then, in the still image portion, double speed conversion is performed via the inter-field interpolation means (12), and in the moving image portion, double speed conversion is performed via the intra-field interpolation means (9).

Since the image is displayed by the signal converted by the F-action double speed conversion means, an image having vertical and horizontal frequencies twice each, that is, an image from which interference such as raster interference, line flicker, and large area flicker is removed is displayed. To be done. In the still image part,
Since the double speed conversion is performed via the inter-field interpolation means,
Sufficient resolution can be obtained. On the other hand, in the moving image portion, double speed conversion is performed through the intra-field interpolating means, so that an image without deterioration such as two-line interference is displayed.

G Example An example of the present invention will be described below with reference to FIG.

In the figure, (1) is an antenna, (2) is an FM receiver, a 12 GHz band satellite broadcast signal is supplied to this FM receiver (2), and from this FM receiver (2) MU mentioned above
An SE television signal S _MV can be obtained. This signal S _MV
Is converted into digital data by the A / D converter (3) and then supplied to the field delay circuit (4). The output of the delay circuit (4) is supplied to the field delay circuit (5), the output of the delay circuit (5) is supplied to the field delay circuit (6), and further the field delay circuit (6). Is supplied to the field delay circuit (7). The field delay circuits (4) to (7) are composed of, for example, field memories. As mentioned above, the signal S
_MV is a signal that makes a cycle of four fields from the first field to the fourth field. For example, when the signal of the first field is supplied as the input of the delay circuit (4), the delay circuits (4), (5), ( As the outputs of 6) and (7), signals of the fourth field, the third field, the second field, and the first field are obtained, respectively.

Further, the signal S _MV converted into digital data by the A / D converter (3) is supplied to the sync separation and clock recovery circuit (8), and from this circuit (8), a clock for A / D conversion,
Other system clocks (64MHz, 128MHz, etc.) are generated and supplied to each part of the circuit.

G ₁ Explanation of Interpolator in Field (FIGS. 2 and 3) Further, (9) is an interpolator in field which mainly generates a signal forming a scanning line of a moving image portion. The signal S _MV (current field signal) from the A / D converter (3) is supplied to the interpolation section (9). Then, in the interpolation section (9), the interpolation pixel is determined based on the pixel transmitted in the current field. In this case, one of the transmitted pixels
On the other hand, a total of 7 pixels of 3 points on the same line and 4 points on the adjacent line are interpolated.

Here, FIG. 2A shows the pixels transmitted by the signal S _MV , and the pixels indicated by “1”, “2”, “3” and “4” are respectively the first field, the second field, Pixels transmitted in the third and fourth fields,
Pixels in the "x" part are not transmitted. In addition, this second
FIG. A corresponds to FIG.

Therefore, in the first frame of the signal S _MV , the interpolation unit (9) interpolates pixels as shown in FIG. 2B. In the same figure, the portion indicated by “◯” is the interpolated pixel. And in this case, the pixels of the lines 1, 3, 5, ... Compose scanning lines of the normal field, but 2, 4, 6,
The pixels of the line (arrow) of ... constitute the scanning line of the interpolation field.

It should be noted that the same interpolation is performed when the second frame, the third frame, and the fourth frame are present.

Here, FIG. 2C shows an example of interpolation in the case of displaying an image with normal vertical and horizontal frequencies.

FIG. 3 shows a specific circuit of the interpolation section (9).
The signal S _MV is supplied to the dot line delay line (91), and from this delay line (91), the transmitted predetermined pixel a ₀ and pixels a _{1 to} a ₆ in the vicinity thereof (for example, within 5 lines) are transmitted. It is output in parallel. The seven pixels a _{0 to} a ₆ output from the delay line (91) are supplied to the weighting adders (92 ₁ ) to (92 ₇ ) and the 7 points are output from these adders (92 ₁ ) to (92 ₇ ). Interpolation pixels b _{1 to} b ₇ (second
“B” is obtained in FIG. The interpolation pixels b _{1 to} b ₇ and the predetermined pixel a ₀ (“1” in FIG. 2B) are output shift registers (93 ₁ ) corresponding to the scanning lines of the normal field and the scanning lines of the interpolation field, respectively. And (93 ₂ ) loaded. And these shift registers (93 ₁ ) and (93 ₂ )
A clock of 64MHz is supplied to, and the loaded pixels are output. Therefore, since the above operation is sequentially repeated, the shift registers (93 ₁ ) and (93 ₂ )
From these, the signal A ₁ of the scanning line of the normal field and the signal A ₂ of the scanning line of the interpolation field are obtained in parallel, respectively.

The signals A ₁ and A ₂ obtained from the interpolation section (9) are supplied to the adder (11) via the multiplier (10).

G ₂ 4 Inter-field Interpolator Description (FIGS. 2 and 4) Further, (12) is a 4-field interpolator that mainly generates a signal forming a scanning line of a stationary portion. The interpolator (12) includes a signal S _MV (current field signal) from the A / D converter (3) and an output signal S from the delay circuit (4).
_MV1 (a signal one field before), an output signal S _MV2 (a signal two fields before) of the delay circuit (5), and an output signal S _MV3 (a signal three fields before) of the delay circuit (6) are supplied.
In the interpolation section (12), the interpolation pixel is determined in consideration of the pixels previously transmitted in the three fields. In this case, four pixels are interpolated for one of the transmitted pixels.

Here, in the odd-numbered frame, the interpolation section (12) interpolates pixels as shown in FIG. 2D. In the same figure, the portion indicated by “◯” is the interpolated pixel. And in this case,
Pixels on the 1,3,5, ... lines form scanning lines in the regular field, while lines (2,6,6, ...) form scanning lines in the interpolating field. Will be things.

It should be noted that even in the case of even fields, the same interpolation is performed.

Here, FIG. 2E shows an example of interpolation in the case of displaying an image with normal vertical and horizontal frequencies. Also at this time, the interpolation pixel “◯” is determined based on the pixels in the four fields.

FIG. 4 shows a specific configuration of the interpolation section (12).
The signals S _MV , S _MV1 , S _MV2 and S _MV3 are supplied to the dot line delay lines (121 ₁ ), (121 ₂ ), (121 ₃ ) and (121 ₄ ), respectively. From these delay lines (121 ₁ ), (121 ₂ ), (121 ₃ ) and (121 ₄ ), the predetermined pixels c ₁₀ , c ₂₀ , c ₃₀ , c ₄₀ transmitted in the respective fields and the vicinity thereof Pixels c _{11 to} c ₁₃ , c _{21 to} c
₂₃ , c _{31 to} c ₃₃ and c _{41 to} c ₄₃ are output in parallel. Pixels c ₁₀ to c ₄₃ outputted from the delay line (121 ₁₎ - (121 ₄₎ is supplied to the weighting adder (121 ₁₎ to (122 _4), adders (121 ₁₎ to (122 ₄₎ As a result, four interpolated pixels d _{1 to} d ₄ (“◯” in FIG. 2D) are obtained. The interpolated pixels d _{1 to} d ₄ and the predetermined pixels c _{10 to} c ₄₀ (“1” to “4” in FIG. 2D) are output corresponding to the scanning line of the normal field and the scanning line of the interpolation field, respectively. For shift registers (123 ₁ ) and (123 ₂ ). Then, a 64 MHz clock is supplied to these shift registers (123 ₁ ) and (123 ₂ ) and the loaded pixels are output. Therefore,
Since the above-described operation is sequentially repeated, the signal B ₁ of the scanning line of the normal field and the signal B _{2 of the} interpolation scanning line are obtained in parallel from the shift registers (123 ₁ ) and (123 ₂ ), respectively.

The signals B ₁ and B ₂ obtained from the interpolation section (12) are supplied to the adder (11) via the multiplier (13).

G ₃ Description of Motion Amount Detection Unit (FIG. 5) Further, (14) is a motion amount detection unit for detecting the motion of an image. The motion amount detecting section (14) includes an A / D converter (3)
From the signal S _MV (signal of the current field), the output signal S _MV2 of the delay circuit (5) (the signal 2 fields before) and the output signal S _MV4 of the delay circuit (7) (the signal 4 fields before)
Is supplied. The motion amount detecting section (14) detects the degree of motion of each pixel (before interpolation) from the signals S _MV , S _MV2 , and S _MV4 , and outputs this as a motion amount K (0 ≦ K ≦ 1). . K = 0 in a completely stationary part, K = in a completely moving part
It is assumed to be 1. Further, at the boundary between the moving part and the stationary part, K is set to an intermediate value between 0 and 1 so that this boundary is not noticeable. The motion amount detecting section (14) is configured, for example, as shown in FIG.

Signals S _MV and S _MV4 are combined into synthesizers (141 ₁ ) and (141 ₂ ), respectively.
Is supplied to. In addition, these synthesizers (141 ₁ ) and (14
The signals S _MV2 are respectively supplied to 1 ₂ ). Further, the combined signal of the signals S _MV and S _MV2 obtained from the combiner (141 ₁ ) is
It is supplied to a subtractor (143 ₁ ) through a two-dimensional spatial low pass filter (142 ₁ ). Further, the signal S _MV2 is supplied to the subtractor (143 ₁ ) through the two-dimensional spatial low pass filter (142 ₂ ). Then, the difference signal from the subtractor (143 ₁ ) is converted into an absolute value by the absolute value circuit (144 ₁ ) and supplied to the maximum value selection circuit (145). The synthesizer (141 ₂ )
The resultant composite signal of the signals S _MV2 and S _MV4 is supplied to the subtractor (143 ₂ ) through the two-dimensional low pass filter (142 ₃ ). In addition, the subtractor (143 ₂ ) includes a combiner (14
1 ₁₎ signals through a two-dimensional low-pass filter (142 ₁₎ of the resulting composite signal from is supplied. Then, the difference signal from the subtractor (143 ₂ ) is converted into an absolute value by the absolute value circuit (144 ₂ ) and supplied to the maximum value selection circuit (145). The output of the maximum value selection circuit (145) is supplied to the field delay circuit (146). This field delay circuit (14
From 6), the amount of movement K in the previous field is obtained, which is multiplied by a constant coefficient between 0 and 1 (for example, 0.5 to 0.7) by the multiplier (147), and then the maximum value selection circuit (14
5) supplied to. Then, the one selected by the maximum value selection circuit (145) is output as the movement amount K.

In FIG. 5, the reason that the combining circuits (141 ₁ ) and (141 ₂ ) combine the signals is to smooth the boundary between the stationary part and the moving part. In addition, the low-pass filter (14
2 ₁ ), (142 ₂ ), and (142 ₃ ) are used for smoothing the spatial distribution of the motion amount and for matching the shifts of pixels (sampling points) in each field.

The motion amount K output from the motion amount detector (14) is supplied to the multipliers (10) and (13). And the multiplier (10)
In, the signals A ₁ and A ₂ are multiplied by K, and the signals KA ₁ and KA ₂ are output. On the other hand, in the multiplier (13), the signals B ₁ and B ₂ are multiplied by (1-K), and the signals (1-K) B ₁ and (1-
K) B ₂ is output.

Further, in the adder (11), the signals KA ₁ and KA ₂ and the signal (1-
K) B ₁ and (1-K) B ₂ are added respectively, and the signal C ₁ = KA
₁ and (1-K) B ₁ and _{C 2 = KA 2 + (1} -K) B 2 is obtained.

These signals C ₁ and C ₂ are supplied to the double speed conversion unit (15).
Here, at K = 0 (complete stationary part), C ₁ = B ₁ , C ₂ = B ₂
Therefore, the signal from the interpolation unit (12) is sent to the double speed conversion unit (15).
B ₁ and B ₂ are supplied. On the other hand, when K = 1 (complete movement part), C ₁ = A ₁ and C ₂ = A ₂ , and the signals A ₁ and A ₂ from the interpolation part (9) are supplied to the double speed conversion part (15). It Then, when K is an intermediate value of 0 to ₁ , the signals A ₁ , A ₂ from the interpolation unit (9),
The signals B ₁ and B ₂ from the interpolation section (13) are weighted and added according to K and supplied to the double speed conversion section (15).

G ₄ Description of double speed conversion unit (FIGS. 6 and 7) Further, in the double speed conversion unit (15), two series of parallel signals, that is, the signal C ₁ of the regular scanning line and the signal C _{2 of the} interpolation scanning line are used. But,
It is converted into a double speed signal with a horizontal frequency doubled (67.4 kHz). The double speed conversion unit (15) is configured, for example, as shown in FIG.

The signal C ₁ is sent to the field memory (152a) and the line memory (152c) via the A side and B side of the changeover switch (151 ₁ ).
Is supplied as write data. On the other hand, the signal C ₂ is
Through the A-side and B-side of the changeover switch (151 ₂₎ is supplied to the field memory (152 b) and (152d) as write data.

Also, a 64-MHz clock CLK synchronized with signals C ₁ and C _2.
W, via the A-side and B-side of the changeover switch (151 ₃₎ field memory (152a), (152 b) and a field memory (152c), supplied as a write clock (152d). Also, 128M that has twice the frequency of the clock CLK _W
Hz clock CLK _R the field via the A-side and B-side of the changeover switch (151 ₄₎ Memory (152c), (152d) and the field memory (152a), is supplied as a read clock (152 b).

In addition, field memories (152a), (152b), (152c)
The signals read from (152d) and (152d) are supplied to the fixed terminals on the a side, b side, c side and d side of the changeover switch (153), respectively.

Further, the changeover switches (151 ₁ ), (151 ₂ ), (151 ₃ ) and (151 ₄ ) are controlled in conjunction with each other, and as shown in FIG.
It is switched to the A side and the B side every one vertical period (1V). Further, the change-over switch (153) is sequentially changed over to the a-side through the d-side every 1/2 V at the timing shown in FIG. 7B.

With the above configuration, at 1V in which the changeover switches (151 ₁ ) to (151 ₄ ) are connected to the A side, one field of the signals C ₁ and C ₂ is normally stored in the field memories (152a) and (152b), respectively. Written at high speed (64MHz). In the first half of 1V, one field of the signal C ₁ is read from the field memory (152c) at double speed (128MHz), and in the second half of the 1V, one field of the signal C _{2 is} doubled from the field memory (152d). Is read by. Also, changeover switches (151 ₁ ) to (15
In 1V 1 ₄₎ is connected to the B side, likewise, the field memory (152c) and (writing normal speed signals C ₁ and C ₂ to 152d) is performed, a field memory (152a)
And (152b), the signals C ₁ and C ₂ are read at double speed. Therefore, from the change-over switch (153), the double speed signal S _2MV (shown in FIG. _7G ) whose vertical and horizontal frequencies are each doubled is obtained. 7C, D, E and F are field memories (152a), (152b), (152c) and (152), respectively.
The state of d) is shown.

Also, the signal S _2MV obtained from the double speed conversion unit (15) is D /
After being converted into an analog signal by the A converter (16Y), it is supplied to the matrix circuit (17). The signal S _MV is the luminance signal Y.
TCI in which the color signals C _W and C _N are multiplexed during the horizontal blanking period of
Since it is a signal, the double speed signal S _2MV is also a TCI signal.

The double speed signal S _2MV is supplied to the color demodulation circuit (18),
A red color difference signal RY and a blue color difference signal BY are obtained from this color demodulation circuit (18). Then, the respective color difference signals RY
And BY are supplied to the matrix circuit (17) via the D / A converters (16R) and (16B).

Therefore, from the matrix circuit (17), the red, green and blue primary color signals R ₂ , G ₂ and B whose vertical and horizontal frequencies are respectively doubled.
₂ is obtained and supplied to the color picture tube (20) via the amplifiers (19R), (19G) and (19B), respectively.

The sync separation / clock recovery circuit (8) generates a horizontal sync signal P _2H having a frequency (67,4 kHz) that is twice the normal frequency, and this is supplied to the horizontal deflection circuit (21H).
Then, a deflection signal is supplied from the horizontal deflection circuit (21H) to the deflection coil (22) of the picture tube (20), and horizontal deflection scanning is performed at a normal double speed. Further, the circuit (8) generates a vertical synchronizing signal P _2V having a frequency (120 Hz) that is twice the normal frequency, and this is supplied to the vertical deflection circuit (21V). From this vertical deflection circuit (21V), the picture tube (2
A deflection signal is supplied to the deflection coil (22) of 0), and vertical deflection scanning is performed at a normal double speed.

As described above, the picture tube (20) is supplied with the primary color signals R ₂ , G ₂ , and B ₂ whose vertical and horizontal frequencies are each doubled, and the vertical and horizontal deflection scans are respectively performed at double speed. Therefore, on the screen of the picture tube (20), as shown in FIGS. 8 and 9, an image display having double the vertical and horizontal frequencies is displayed.
In FIG. 8, the solid lines show the scanning lines in the odd field and the broken lines show the scanning lines in the even field.

In this case, in the still image portion (K is close to 0), the signals B ₁ and B ₂ mainly from the inter-field interpolation unit (12) are supplied to the double speed conversion unit (15), so that the displayed image is displayed. Is mainly due to the signals B ₁ and B ₂ . On the other hand, in the moving image portion (K is close to 1), since the signals A ₁ and A ₂ mainly from the intra-field interpolation unit (9) are supplied to the double speed conversion unit (15), the displayed image is mainly the signal A. _{It depends on 1} , A ₂ .

Thus, according to this example, the vertical and horizontal frequencies are 2
Since the double image display is performed, an image without raster interference, line flicker, and large area flicker is displayed. 10th
The figure shows the double speed signal (the one with less movement) in this example.
It is displayed in the dimensional (vertical-time) frequency plane, but the components that cause raster interference, line flicker, and large area flicker (see the broken line illustration) are removed.

Further, according to this example, in the still image portion, the image mainly based on the signals B ₁ and B ₂ from the inter-field interpolating unit (12) is displayed, so that an image with sufficient resolution can be obtained. On the other hand, in the moving image portion, an image mainly based on the signals A ₁ and A ₂ from the intra-field interpolation unit (9) is displayed.
An image without deterioration such as two-line interference due to time difference is displayed.

G ₅ Description of Motion Correction By the way, as described above, according to the processing adapted to the motion of the image, there is a problem when the entire screen moves in one direction. Such a state appears when the camera pans slowly. At this time, the human visual system moves the viewpoint in accordance with the movement of the scene, and thus has almost the same resolution as when the screen is stationary. . However, since the motion amount detection unit (14) determines that it is a moving part,
An image is mainly displayed by the signals A ₁ and A ₂ from the intra-field interpolation unit (9), and the resolution is lowered. Since the resolution of the visual system also decreases in normal moving parts, the decrease in screen resolution is not noticeable, but in this case, the resolution of the visual system remains the same as when the screen is stationary, so the screen It gives an impression that is blurred.

Therefore, in this example, such a defect is also prevented.

In FIG. 1, (23) is a motion vector decoder, and the signal S _MV is supplied from the A / D converter (3) to this decoder (23). Although not described above, during the vertical blanking period of this signal S _MV , the motion amount M (two components of horizontal and vertical) of the entire screen is digitally coded and multiplexed. The decoder (23) detects this motion amount M, and the delay circuits (4) to (7) are detected by this motion amount M.
Read address is controlled (write address is constant). That is, the pixel position of each field is shifted and output according to the movement amount M, and the corresponding pixels are overlapped.

Therefore, when the entire screen moves slowly in one direction, the motion amount detection unit (14) determines that it is a stationary portion, and mainly displays the image by the signals B ₁ and B ₂ from the inter-field interpolation unit (12). Therefore, it is possible to prevent the above-mentioned blurring.

In addition to the above-described embodiment, a configuration using a two-beam type picture tube may be considered. In this case, in the double speed conversion unit (15) shown in FIG. 6, the writing is performed in the same manner, but the signals of the same field are read out twice consecutively from the field memories (152a) to (152d). . 7H to 7K show the states of the field memories (152a) to (152d), respectively. Then, although not shown, a first changeover switch for switching the read outputs of the field memories (152a) and (152c) for each 1V and a second switch for switching the read outputs of the field memories (152b) and (152d) for each 1V. A switch is provided to obtain signals S ₁ and S ₂ as shown in FIGS. 7L and 7M, respectively. The signals S ₁ and S ₂ control the first and second beams, respectively.
Scan lines 1-563 and 563-1125 by the first and second beams
Are simultaneously formed (see FIGS. 8 and 9). Therefore, in this case, the vertical and horizontal frequencies are each doubled to 1
Non-interlaced display in which 1 to 1125 scan lines are displayed in the field is performed. Also in this case, since the vertical and horizontal frequencies are doubled, it is possible to obtain the same effects as those of the example of FIG.

Effect of the Invention According to the present invention described above, since the vertical and horizontal frequencies are each doubled, it is possible to obtain a high quality image free from raster interference, line flicker and large area flicker. Moreover, since the still image portion is double-speed converted through the inter-field interpolating means, an image with sufficient resolution is displayed, and the moving image portion is double-speed converted through the intra-field interpolating means. An image without deterioration such as line interference is displayed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining interpolation, FIG. 3 is a block diagram of an intra-field interpolation unit, and FIG. 4 is a block diagram of the inter-field interpolator, FIG. 5 is a block diagram of the motion amount detector, and FIG. 6 is a block diagram of the double speed converter.
FIG. 7 is a time chart for explaining it, and FIGS.
FIG. 10 is a diagram for explaining one embodiment, FIGS. 11 to 13 are diagrams for explaining a conventional example, and FIGS. 14 and 15 are diagrams for explaining a MUSE type television signal. is there. (2) is an FM receiver, (4) to (7) are field delay circuits, (9) is an intra-field interpolator, (10) and (13) are multipliers, (12) is an inter-field interpolator, (14) is a motion amount detecting section, (15) is a double speed converting section, (20) is a color picture tube, (21H) is a horizontal deflection circuit, and (21V) is a vertical deflection circuit.

Front page continuation (72) Inventor Yutaka Morii 2-2-1 Shinnan, Shibuya-ku, Tokyo Broadcasting Center of Japan Broadcasting Corporation (72) In-ichi Yamamoto 2-2-1 Shinnan, Shibuya-ku, Tokyo Inside the Broadcasting Corporation Broadcasting Center (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Technology Laboratory

Claims (1)

[Claims] 1. Means for receiving a television signal in which a screen in 4-field units, which is band-compressed by sub-Nyquist sampling and is dot-interlaced with each other, is sequentially transmitted, and an interpolation scanning line signal is normalized from the received television signal. Interpolating means obtained with the scanning line signal of
Double scan conversion means for obtaining a television signal having a vertical and horizontal frequency twice each by using the normal scanning line signal and the interpolated scanning line signal output from the interpolation means, and the movement of the image from the television signal. A motion detecting means for detecting is provided, an inter-field interpolating means and an inter-field interpolating means are provided as the interpolating means, and an inter-field interpolating means is provided near the pixel signal indicated by the television signal of the current field. First delay means for detecting a pixel signal, second delay means for detecting a pixel signal in the vicinity of a pixel signal shown by a television signal one field before, and pixel shown by a television signal two fields before Third detecting a pixel signal in the vicinity of the signal
Delaying means, a fourth delaying means for detecting a pixel signal in the vicinity of a pixel signal indicated by a television signal three fields before, and an interpolation pixel by weighting and adding outputs of the delaying means in different weighting states. A first adder that obtains a signal, an output pixel signal of each delay unit, and an output pixel signal of the plurality of adder units are used to output the pixel order of the regular scanning line and the pixel order of the interpolation scanning line. And the second
And a shift register for detecting the pixel signal in the vicinity of the pixel signal represented by the television signal of the current field, and the output of the fifth delay means as the inter-field interpolating means. Pixel order of regular scanning lines using a plurality of adding means for weighting and adding in different weighting states to obtain an interpolated pixel signal, and output pixel signals of the delay means and output pixel signals of the plurality of adding means And a third and a fourth shift register for outputting in the pixel order of the interpolation scanning line, and when the motion detecting circuit detects the motion of the image, the output of the intra-field interpolating means is taken as the output of the interpolating means. , When the motion of the image is not detected, the output of the inter-field interpolating means is used as the output of the interpolating means, and the television signal is stored as the double scan converting means. And storing the output of the interpolating means in the storing means by simultaneously performing the normal scanning line signal and the interpolating scanning line signal output by the interpolating means at a predetermined clock frequency. From the storage means is double scanned and converted from the output of the storage means by alternately reading the regular scanning line signal and the interpolating scanning line signal at a frequency twice the predetermined write clock frequency. A high-definition television receiver characterized by being adapted to obtain a television signal.