JPH0664553B2 - Stack control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a configuration of a stack control circuit that temporarily stores invalidation addresses of a cache memory, and prevents the same invalidation address from being stacked in multiple layers. For the purpose of reducing the number of cache memories and improving the efficiency of cache memory invalidation processing, the present invention temporarily stores an address for invalidating a cache memory provided between a central processing unit and a main storage device in a plurality of stacks. A stack control circuit for temporarily storing, and the invalidation address currently stored in the stack is compared with the invalidation address newly stored in the input stage of the stack control circuit, and the invalidation address is matched. An address comparison / determination means for sending the invalidation address to the stack is provided only when the stack is not used.

[Industrial application field]

The present invention relates to the configuration of a stack control circuit that temporarily stores an invalidation address of a cache memory.

[Problems to be Solved by Prior Art and Invention]

The cache memory is a relatively low-capacity high-speed memory that is provided between the main memory and the processor via the system bus to improve the operating speed of the computer. Usually, a part of a program or data stored in the main memory is temporarily held in the cache memory, and data is transferred between the cache memory and the processor to increase the speed.

The cache memory is composed of a tag unit that stores an address divided into a plurality of entries and a data unit that stores data. Each entry of the tag unit has a bit indicating an address, a parity bit for error checking, and It is composed of valid bits of the entry or a valid bit indicating the validity. Therefore, the entry is invalidated by resetting the valid bit of the entry corresponding to the main memory to, for example, "0". On the other hand, a stack control circuit is provided separately from the cache memory to sequentially and temporarily store the addresses of the entries to be invalidated in the cache memory. The stack control circuit is composed of a plurality of serial or parallel stacks for storing each invalidation address.

In such a configuration, the memory area of the main memory already registered in the cache memory may be rewritten by the processor or another master device connected to the system bus. In this case, the contents of the cache memory and the main memory cannot be matched. Therefore, for example, when another master device writes to the main memory, the contents of the entry of the cache memory corresponding to the address of the main memory must be invalidated. I won't. In such invalidation processing, when writing to the main memory by another master device, the addresses are sequentially stored in the above-mentioned stack and the idle time of access from the processor (the unused time of the cache memory) is used to This is done by sending that address to the cache memory as an invalidation address. The invalidated address is expelled from the stack and becomes a memory space for the next invalidated address.

FIG. 4 shows an example of the configuration of a conventional stack control circuit, in which a plurality of stacks ST _{0 to} ST _n are arranged in parallel.
The invalidation addresses are sequentially stored (stacked) in the stacks ST ₀ to ST _n via the address line 1 from other master devices. At the time of invalidation processing, the oldest stacked address is sent to the tag portion of the cache memory by the switching means 2 that switches the stack output.

However, in this case, the stack will stack all the addresses that are already stored and the address that is being newly stacked, whether they are the same or different, so hold multiple identical addresses in multiple layers. In this case, the entry may be invalidated again at the same address. For example, depending on the data part of the cache memory, there is a configuration in which four types of data are stored in an entry of one address. Therefore, when the same address has different data, the same entry is invalidated again. Is. To deal with this, there is a problem that the number of stacks must be increased in order to hold more addresses.

An object of the present invention is to reduce the number of stacks in a stack control circuit and prevent stacking of the same address in a stack to improve the efficiency of cache memory invalidation processing.

[Means and Actions for Solving Problems]

FIG. 1 is a basic configuration diagram of the present invention. As shown in the figure,
Address comparison / determination means 11 is provided at the input stage of the stack control circuit.
The new invalidation address is first input to the address comparison / determination means 11 to make a comparison determination with the address already stacked at the present time so that the same address is not stacked and only different addresses are stacked. Constitute. That is, from the stacks ST _{0 to} ST _{n, the} address currently stacked by itself is sent to the comparison / determination means 11, and the address comparison / determination means 11 makes a comparison / determination result. Address is sent to the existing stack.

By thus adding the address comparison / judgment means 11 to the input stage of the stack control circuit, it is possible to prevent the same address to be invalidated from being stacked in a multiple manner, which makes it possible to reduce the number of stacks and, consequently, efficient invalidation. The chemical treatment can be carried out. Incidentally, the switching means 12 is, as described above, for sending out as the invalidation address to the tag portion of the cache memory in order from the oldest stacked address during the invalidation processing.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the stack control circuit according to the present invention. In the figure, 21 is an address latch circuit, 2
2 is an address comparison / determination circuit, 23 is a first stack counter, 24 is a stack input control circuit, 25 is a stack,
Reference numeral 26 is a second stack counter, and 27 is a stack output control circuit. In such a configuration, the address A ₁ from the processor as the access source or another master device is once latched in the address latch circuit 21. On the other hand, the address-stack ST ₀ ~ST ₃ is respectively input to the address comparison determination circuit 22 compares the address A ₂ output from the address latch circuit 21, the memory write signal sent from the CPU (SET) Create a stack input enable signal (E). First stack counter 2
Reference numeral 3 denotes a quaternary counter which counts by the enable signal E, and cyclically outputs a count value C ₁ indicating a stack in the order of 3 → 0 → 1 → 2 → 3 → 0 →. The count value C ₁ is output to the address comparison / determination circuit 22 and the stack input control circuit 24.

The stack input control circuit 24 includes the address latch circuit 21.
The address A ₂ from the enable signal E from the address comparison determination circuit 22, the count value C ₁ is input from the stack counter 23, the address A ₂ to the stack which is selected by the count value C ₁ by enable signal E
Is output. The stack 25 is a stack input control circuit 24
The address A ₃ is stacked on the stack designated by. On the other hand, the second stack counter 26 counts by the invalidation signal IV sent during the idle time of the CPU 4
It is a binary counter and the counter value is 3 → 0 → 1 → 2 → 3 →
A count value C ₂ indicating a stack is cyclically output as 0 → ... The stack output control circuit 27 uses the address A _{4 of} the stack designated by the second stack counter 26 as the tag portion (not shown) of the cache memory.
And outputs it as an invalidation address A ₅ .

FIG. 3 is a circuit diagram of an embodiment of the address comparison / determination circuit 22 shown in FIG. In the figure, 31a to 38 are AND gates and 39 to 43 are OR gates. Among these, AN
The inputs of the D gates 31b, 32b, 33b and 34b are inverted and input, and the output of the NOR gate 44 is the AND gate 3
8 is input to one side. The count value "0" indicating the stack number is input to one input of the AND gate 35, and the count value "1" indicating the stack number is input to the OR gate 43.
And "2", and the count value "3" indicating the stack number is input to one input of the AND gate 37. These count values (C0, C1, C2, C3) correspond to the count value C ₁ output from the first stack counter 23. The output of the AND gate 38 is the enable signal E input to the stack input control circuit 24. In this case, the memory write signal SET is input to the other input of the AND gate 38. Therefore, when both of these input signals are at the high level "H", the enable signal E is obtained.

The operation of this circuit is as follows. For example, the count value output from the first stack counter 23 is the stack
When indicating the ST _{0 "0",} since the address of the stack ST ₀ is valid and the address A ₂ and stack ST ₀ are compared. In this case, since C0 = “H” and C1, C2, C3 = “L”, the outputs of the AND gates 35 to 37 are low level “L”. If the addresses A ₂ and the address of the stack ST ₀ do not match, the outputs of the AND gates 31 a and 31 b both become “L”, and the output of the OR gate 39 therefore becomes “L”. Therefore, the output of the NOR gate 44 becomes "H", and the enable signal E becomes "H" only when the memory write signal SET is "1". Further, when the count value indicates a stack ST ₂ of "2", the stack ST _0, ST _1, since the address of the ST ₂ is enabled to compare these with the address A _2. In this case, C2 = "H" and C0, C1, C3 are "L", so A
The output of the ND gate 37 becomes "L". Therefore, if there is a mismatch in the comparison of the address A ₂ and the address of the stack ST ₀ , the comparison of A ₂ and ST ₁ , and the comparison of A ₂ and ST ₂ , each becomes “L”. Therefore, all of them become "L", and the enable signal becomes "H" only when the memory write signal SET is "H".

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the same invalidation address from being stacked in multiple stacks by adding the comparison / determination means for comparing the addresses to the stack control circuit that stacks the invalidation addresses of the cache memory. Therefore, the number of stacks can be reduced, and efficient invalidation processing can be performed.

[Brief description of drawings]

 FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a detailed block diagram of one embodiment of FIG. 1, FIG. 3 is a detailed diagram of an address comparison judgment circuit of FIG. 2, and FIG. 4 is a conventional configuration diagram. Is. (Explanation of Codes) 11 ... Address Comparison / Determination Means, 12 ... Switching Means, 21 ... Address Latch Circuit, 22 ... Address Comparison Judgment Circuit, 23 ... First Stack Counter, 24 ... Stack Input Control Circuit, 25 ... Stack, 26 ... Second stack counter, 27 ... Stack output control circuit.

Claims (1)

[Claims] 1. A stack control circuit for temporarily storing, in a plurality of stacks (25), an address for invalidating a cache memory provided between a central processing unit and a main storage unit. Address comparison for determining the invalidation address currently stored in the stack and the invalidation address newly stored in the input stage of the stack, and transmitting the invalidation address to the stack only when the invalidation address does not match. Judgment circuit (22) and stack counter (23) for counting to specify the stack
And a stack control circuit, wherein the stack, the address comparison circuit, and the stack counter are connected in parallel to an input address.