JPH066382A - Packet communication device and communication system - Google Patents

Abstract

PURPOSE:To prevent an image and a speech from deteriorating in quality by providing a variable frequency dividing circuit, varying the frequency division ratio according to a carry signal, and controlling the timing of the input and output of media with the output frequency. CONSTITUTION:Packet data which are sent out to a packet network 26 are inputted to receiving station packet buffers 20 and 21 and stored. Pieces of flag information sent out of an overflow flag generating circuit 19 and an underflow generating circuit 22 attached to the buffers 20 and 21 are ORed by OR circuits 17 and 18. Their OR outputs are inputted to an up/down counter 16 to accumulate errors of clock frequencies of a receiving circuit and transmitting circuits through the function of the counter 16, and the frequency division ratio of the variable frequency dividing circuit 15 is controlled with its carry signal. Further, the timing of the input and output of the respective media is controlled with the output frequency of a circuit 13, and then the image and speech can be transferred even by using the packet network of an independent synchronization system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet communication device capable of transferring temporally continuous media such as voice and video without degrading quality on an independent synchronous packet network such as LAN. And a communication method.

[0002]

2. Description of the Related Art Conventionally, FDDI-II (Fiber Distributed Data Inte) standardized by ANSI in the United States is used.
rface-II) has been put to practical use. This is a communication system that transfers temporally continuous media such as voice and video on a LAN, and is a service for both packet switching and circuit switching.
The screws are realized by hybrid transmission. FDDI
-II is, for example, “FDDI P
hisical Layer Protocol (PHY-2) ”Working Draf
t Proposed American National Standard, AS
C X3T9.5 Rev.3.1 (1990). FDDI
-II synchronization system is characterized in that each station transmits and receives data to and from the link-by-link by using independent clocks (independent synchronization system), and at the same time, 8 KHz which is the basis of circuit switching service. Regarding the cycle clock, the point is that the master station is defined and all other stations are synchronized depending on the clock of the master station (dependent synchronization method). On the contrary,
Originally defined as a network for data F
The DDI-I communication system is still used not only in the United States but also in other countries. The feature of the FDDI-I synchronization system is that only the independent synchronization system is adopted between the stations.

FIG. 2 shows FDDI-II and FDDI-.
It is explanatory drawing of the synchronization system of I. In FIG. 2, F1 is a master station clock frequency, F2, F3, F4.
Is a clock frequency of the slave station, and 1 is a link synchronized with the clock of the master station. All slave stations are slaved to this clock for synchronization (dependent synchronization method). Also, 2, 3, 4, 5 are
It is a link that is synchronized with an independent clock for each station, and each station transmits and receives data to and from the link-by-link by using an independent clock (independent synchronization method). FDDI-I, which is the original network, uses only the independent synchronization method between each station for data
Data transfer, and only links 2, 3, 4, and 5 are provided. On the other hand, the FDDI-II has two different synchronization methods on the same ring, that is, independent synchronization and subordinate synchronization, and the link 1 is provided in addition to the links 2, 3, 4, and 5. In FDDI-I, the video and audio encoding clocks of the transmitting station are asynchronous with the receiving station clock, so normal data transfer is impossible.

[0004]

As described above, in the FDDI-I which is still used by itself, the audio is encoded by an individual clock in each station and is asynchronous with this clock. Network by the transmission line clock of
Data on the clock. In the receiving station that receives the transmitted data, the data is reproduced by point-to-point independent synchronization, but a subordinate synchronization mechanism is not provided. As a result, the clock on the transmitting side and the clock on the receiving side of video and audio encoding are asynchronous,
Normal data transfer becomes impossible. As a result, the video and audio data on the receiving side is lost or overflows, resulting in deterioration of quality due to the loss of data.
Further, in a state where communication is simultaneously performed between a plurality of stations on the network, a plurality of transmission clocks are dealt with by a single reception clock, resulting in deterioration of quality as described above. . FIG. 3 is a diagram showing a communication model of an FDDI-I transmission / reception station. In FIG. 3, FDDI is a network and COD is a transmitting side station.
Encoder, XT-BUF is a transmission side buffer, R
X-BUF is a receiving side buffer, and DEC is a receiving side station decoder. The data transmitted by the encoding clocks F1 and F2 of the plurality of transmission stations are received by the reception station via the network FDDI. In the reception station, the encoder DEC operates at the clock F3. Each packet received in the reception station is latched by the clock F3 via the reception buffer RX-BUF, and after gain adjustment,
They are added and decoded by the decoder DEC. In this case, since the transmission side clocks F1 and F2 and the reception side clock F3 are asynchronous, the video and audio data are lost or overflowed. For example, when the transmitting side has a clock for transmitting 10 / ms packets, while the receiving side has a clock for receiving 9 / ms packets, only one packet is lost per 1 ms, and the transmitting side has 9 / ms packets. When the receiving side is a 10 / ms packet in ms packets, only one packet will overflow in 1 ms. An object of the present invention is to solve such a conventional problem and to transfer video and audio without degrading quality even when using an independent synchronous packet network such as FDDI-I. It is to provide a possible packet communication device and communication method.

[0005]

In order to achieve the above object, the packet communication apparatus of the present invention comprises: (a) a network of independent synchronization and a plurality of terminals connected to the network in terms of time. In a packet communication device for performing bidirectional packet communication using continuous media, a plurality of packet buffers for accumulating packets from a plurality of terminals for each receiving terminal, and a data buffer for each packet buffer.
Means for monitoring the buffer and underflow, first OR means for ORing the overflow signals from the monitor means for each packet buffer, and the underflow signal from the monitor means for each packet buffer Second OR means for taking the logical OR of the above, an up / down counter for making the outputs from the first and second OR circuits an up signal and a down signal, and a carry from the up / down counter.
It is characterized by having a variable frequency dividing circuit for changing the frequency dividing ratio according to a signal and a control means for controlling the input and output timing of each medium according to the output frequency of the variable frequency dividing circuit. Also, (b) a decoding circuit is provided for each output of the plurality of packet buffers, and after decoding packets from a plurality of points by the decoding circuit,
It is also characterized in that each decoded data is input to the media output circuit and the output timing of each media of the media output circuit is controlled by the output frequency of the variable frequency dividing circuit. Further, (c) the control means is characterized in that only the output timing of each medium is controlled by the output frequency of the variable frequency dividing circuit. (D) By maintaining the input timings in a synchronized multiple relationship in advance for a plurality of media, the frequency division ratio of the variable frequency divider circuit is controlled for media with a short control cycle, and It is also characterized in that the variable frequency divider circuit is used to maintain the synchronization relationship between the transmission side and the reception side for a medium having a long control cycle. Further, (e) the plurality of media are also characterized by temporally continuous audio signals or video signals. next,
The packet communication method of the present invention is (f) a packet communication method for performing bidirectional packet communication using an independent synchronous network and a temporally continuous medium between a plurality of terminals connected to the network. In the above, in each of the plurality of packet buffers for accumulating the packets from the plurality of terminals for each receiving terminal, the data overflow, underflow, and delay limit are monitored, and each is detected. Is set, and the decoding operation of the decoding circuit for decoding the output of each packet buffer is controlled by turning on / off the full flag, the empty flag, and the delay flag. Further, when the (f) overflow is monitored and the overflow is detected, the data accumulated in the packet buffer is read at a speed K times the normal read speed,
The decoding circuit is also characterized by thinning out and inputting every K samples. (H) When the underflow is monitored and the underflow is detected, the final data stored in the decoding circuit is repeated, or the data immediately before the underflow is detected and the data immediately after the underflow is detected. It is also characterized in that the reception data interpolates the data in the underflow period. Further, the operation of the decoding circuit is controlled by turning on / off the (re) full flag, empty flag and delay flag, and the frequency division ratio of the variable frequency dividing circuit is changed by the carry signal from the up / down counter. It is also characterized in that the processing for controlling the input and output timing according to the output frequency of the circuit is also used.

[0006]

In the present invention, on the premise of the point-to-point independent synchronization system, the monitor means, the up / down counter, the variable frequency dividing circuit, and the input / output timing control means are provided in each receiving station. That is, the overflow and the underflow monitor means provided for each packet buffer take the logical sum of them when the overflow is detected, and take the logical sum of them when the underflow is detected, Input both OR outputs as up signal or down signal of up / down counter,
The input or output timing of each medium is controlled by changing the frequency division ratio of the variable frequency dividing circuit according to the carry signal from the up / down counter. As a result, when the packet reception speed is high, the frequency division ratio of the frequency division circuit is reduced to accelerate the decoding process, and when the packet reception speed is low, the frequency division circuit is increased to perform the decoding process. Since it can be slowed down, unless there is an extremely early or late delay, quality deterioration such as dropout or overflow will occur even when an independent synchronous network is used to transfer temporally continuous media such as video and audio. It can be done without it happening. Further, as another embodiment, the overflow, underflow, and delay limits are monitored for each packet buffer, and when they are detected, a full flag, an empty flag, and a delay flag are set, and those flags are set. By controlling the decoding operation of the decoding circuit by turning it on and off, data transfer can be performed without degrading the quality.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram in each station showing an embodiment of the present invention. In FIG. 1, reference numeral 11 is a media input circuit for inputting media sent from the transmitting side, and 12
Is an encoding circuit for encoding the receiving medium, 13 is a packet generating circuit for generating a packet with the encoded data,
Reference numeral 14 is a frequency oscillating circuit, 15 is a variable frequency dividing circuit, 16 is an up-down counter, 17 and 18 are OR circuits for ORing monitor detection signals, and 19 and 22 are overflow circuits.
And a flag generation circuit for generating a flag by monitoring the underflow, 20 and 21 are packet buffers for accumulating received packets, 23 and 24 are decoding circuits, 25 is a media output circuit for outputting media, and 26 is FDDI-
It is a packet network such as I. First, on the transmitting side, the input signal is digitized by the media input circuit 11. In this case, the sampling frequency of the AD converter required for digitization is determined by the output of the variable frequency dividing circuit 15. The digitized data is encoded into a predetermined bit rate by the encoding circuit 12. Next, the encoded data is input to the packet generation circuit 13 for transfer to the packet network 26. In the packet generation circuit 13, the data for each sample generated by the encoding circuit 12 is used as fixed or variable packet data.
Convert to data. The above is the operation of the transmitting station. In FIG. 1, the operation on the receiving side will be described using the configuration of the same station due to the relationship of the drawings.

The packet data sent to the packet network 26 is input to the packet buffers 20 and 21 of the receiving station by the network address.
The packet buffers 20 and 21 are provided with a plurality of buffers so that data can be received from a plurality of points at the same time. In the packet buffers 20 and 21, due to the difference in clock frequency between the transmitting side and the receiving side,
Data loss or overflow as described above may occur. For this purpose, an overflow flag generation circuit 19 for detecting overflow and an underflow flag generation circuit 22 for detection of missing are provided. In order to ensure the media quality on the receiving side, the audio in the packet buffers 20 and 21 must be
Buffalo and underflow should be reduced as much as possible. Therefore, in this embodiment, in the case of overflow, the decoding process and the like are speeded up so that
In addition, in the case of underflow, the decoding process and the like are slowed down to reduce the underflow. The flag information output from the overflow flag generation circuit 19 and the underflow flag generation circuit 22 associated with the plurality of packet buffers 20 and 21 are
OR circuit 1 for each overflow and underflow
A logical sum is obtained at 7 and 18, and this is input as an up signal and a down signal of the up / down counter 16. The up / down counter 16 has a function of accumulating an error between clock frequencies of the receiving circuit and the plurality of transmitting circuits,
The frequency division ratio of the variable frequency dividing circuit 15 is controlled by the carry signal of the up / down counter 16.

The control method of the variable frequency dividing circuit 15 is such that the packet buffer 2 on the receiving side is controlled by a carry signal to the up side.
Since it can be seen that 0 and 21 are overflowing on average, by increasing the frequency division ratio of the read clock of the output circuit on the receiving side and increasing the frequency of reading data,
Suppress the frequency of overflow. On the contrary, by the carry signal to the down side, the packet buffer 2 on the receiving side
Since it can be seen that underflows 0 and 21 occur on average, the frequency of underflow is reduced by lowering the frequency division ratio of the read clock on the receiving side to reduce the data read frequency. Suppress. By this control, the clock frequencies of the media output circuit 25 on the reception side and the input circuit 11 obtained by dividing the output signal of the frequency transmission circuit 14 are changed, and the transmission side and the reception side are equivalently synchronized. Become. The output data from the plurality of packet buffers 20 and 21 are input to the respective decoding circuits 23 and 24 and then output to the media output circuit 25.

FIG. 4 is a block diagram showing the main part of the receiving side synchronization control circuit showing the first embodiment of the present invention. In FIG. 4, R
X-BUF is a receiving side packet buffer, OR is an OR circuit, EF is an empty (empty) flag, FF is a full (overflow) flag, COD is an encoding circuit, and DEC is a decoding circuit. First, a plurality (here, three) of reception side packet buffers RX-BUF are configured by FIFOs, and each FIFO is configured.
Empty flag EF and overflow flag FF from
It is used as the input of the input OR circuit. The outputs of these two OR circuits are respectively used as an up input and a down input of an M-bit up / down counter, and a carry signal (up or down) from the up / down counter is changed to change the frequency division ratio of the frequency divider circuit. Signal. Here, the up signal from the up / down counter means that the receiving side is statistically empty, that is, operating faster than the transmitting side, and thus the decoder DE
Input to the -1 side of the frequency divider circuit so as to reduce the operation of C,
Control to increase the division ratio. On the contrary, the down signal from the up / down counter means that the receiving side is statistically full, that is, operates slower than the transmitting side, so that the down signal causes the operation of the decoder DEC to increase. , Is input to the +1 side of the frequency dividing circuit to control the frequency dividing ratio to be small. For example, if the frequency divider circuit is 10
By dividing 0MHz by 1/10, 10MHz
If the empty flag is set when the output is
Since it is input to the -1 side of the frequency divider circuit to increase the frequency division ratio,
While the frequency is divided into 1/11 and output at 9.09 MHz, when the full flag is set, it is input to the +1 side of the frequency dividing circuit to reduce the frequency division ratio, so the frequency is divided into 1/9. 1
Output at 1MHz.

In FIG. 4, the frequency division circuit changes the preset frequency division ratio N to N + 1 or N-1 by an up signal or a down signal. The frequency changed by this frequency dividing circuit is the encoder COD and the decoder DEC.
The stations connected to the network operate at the same frequency on average. Figure 5
FIG. 9 is a configuration diagram showing a modified example of the synchronization control circuit of FIG. 4.
The difference from FIG. 4 is that the output of the variable frequency divider is applied only to the decoder DEC, and the encoder COD operates at a constant frequency. In the case of FIG. 4, since the frequencies of the transmission side and the reception side of all the stations in the system change, there is a possibility that it will not be possible to be pulled to a specific frequency due to the influence of the delay characteristics of the network. Therefore, in FIG. 5, only the frequency on the receiving side is variable in order to avoid such a phenomenon. The synchronous control circuit of FIG. 5 is the same as that of FIG. 4 except that the controlled object is only the decoding circuit DEC. In addition, in FIG. 4 and FIG. 5, when a plurality of media such as audio and video are input, it is possible to maintain a control cycle by keeping the input timings of the plurality of media to be transferred in a pre-synchronized integer multiple relationship. By controlling the frequency division ratio for a medium having a short period, the synchronization relationship between the transmitting side and the receiving side for a medium having a long control cycle can be maintained. For example, when transferring two media, audio and video, it is basically necessary to provide a separate sync control circuit, but by keeping the relationship of 1 for audio and 2 for video, common synchronization control is possible. It can be done with a circuit.

FIG. 6, FIG. 7 and FIG. 8 are explanatory views of the decoding process showing the second embodiment of the present invention. That is, FIG.
Shows the flag configuration in the receiving side packet buffer, FIG. 7 shows an example of thinning output, and FIG. 8 shows an example of replacement and interpolation output. First, second
In this embodiment, as shown in FIG. 6, three types of flags, a full flag (FF), a delay flag (DF), and an empty flag (EF) are provided in the reception packet buffer corresponding to the channel. Here, the full flag FF indicates the limit point of data retention in the received packet buffer, the delay flag DF indicates the point corresponding to the maximum delay of the network, and the empty flag E.
F indicates the limit of missing data in the received packet buffer. The operation of the decoder connected to the receiving side packet buffer is controlled by turning on / off the three flags, the full flag FF, the delay flag DF, and the empty flag EF.

(A) When FF = ON and DF = ON In this case, the data retention in the buffer exceeds the limit, and the decoder controls the clock as described in FIG. At the same time, K double speed reading is performed in order to quickly absorb the data in the buffer. Here, K is a positive integer. (B) When FF = OFF and DF = ON The data in the reception buffer exists between the full flag FF and the delay flag DF, and therefore only exceeds the limit point of data retention. , The decoder side continues reading as usual. (C) When EF = ON and DF = OFF In this case, since the data in the reception buffer has already disappeared, after the reading on the decoder side is disabled, as shown in FIG. The clock is controlled and the received data is replaced or interpolated. The replacement and interpolation will be described in detail with reference to FIG. (D) When EF = OFF and DF = OFF The data in the reception buffer exists between the delay flag DF and the empty flag EF. Therefore, the limit point of data retention is not exceeded, and the empty The data in the buffer is at the ideal speed, since it is not. In this case, reading is continued as usual.

FIG. 7 is an explanatory diagram showing a reading method when the state in the buffer in FIG. 6 is (a). Figure 7
Then, in the case of (a), the method of reading at K double speed is K = 2.
Is shown as. Output S of reception buffer RX-BUF
1 to S9 are thinned out, and only odd-numbered data is input to the decoder. That is, S1, S3, S5, S7,
Only S9 is sampled and input to the decoder. As shown in FIG. 7, the data in the buffer exceeded the FF point and exceeded the limit of retention, but due to this K-speed operation,
The data is reduced to the point of the delay flag DF. Figure 8
FIG. 9 is a diagram showing the contents of replacement and interpolation processing when the state in the buffer in FIG. 6 is (c). Here, after receiving the data of S4 belonging to the packet (N-1),
The case where the reception buffer becomes empty and a packet (N) is received after 4 sample data is shown. The contents of processing in this case include a method of replacing the missing portion with the final sample S4 of the decoder, and interpolating the missing portion with white noise (white noise) W1 to W4 having power equal to the packet (N-1). There is a method. The normal state diagram of FIG. 8 shows the case where packets (N-1) and (N) are continuously input. The figure at the time of delayed arrival is the state of (c) above, XX
Since there is a blank space during XX, in the case of voice, the voice is interrupted to the receiver. In order to avoid this, as shown in the figure of the final sample replacement, the blank portion until delayed input is replaced with the final sample S4 of the decoder. In addition, as shown in the white noise interpolation diagram, the packet (N-
The missing portion is interpolated by the white noise W1 to W4 having power equal to that of 1). This allows the recipient to hear the same noise as the final voice without feeling any interruption in the voice.
There is no strange feeling.

FIG. 9 is a block diagram of a voice CODEC showing a third embodiment of the present invention. In the example of FIG. 9, input / output for a voice signal and a network interface are shown. In FIG. 9, 90 is an interface unit for connecting a network such as FDDI-I, 20 is a receiving buffer, 91 is a buffer control unit, 92 is a signal processor (DSP), 93 is an AD converter or DA converter, 94 is a timing control circuit, 95 is a microphone /
An analog interface unit connected to the speaker. The voice data from the microphone is input to the AD converter 93 via the analog interface 95, and then to the signal processor 92 which performs encoding processing. The voice data from the signal processor 92 is input to the FIFO 20 which performs packetization, and then the network.
The data is output to the network via the interface unit 90. On the other hand, the data received from the network is input to the FIFO 20 corresponding to each channel via the network interface unit 90. At this point, the FIFO
When the flag information in 20 is reflected in the buffer control unit 91, it is input to the signal processor 92 and the timing circuit 94 that controls the timing of the AD and DA converters 93. The reception data input from each FIFO 20 to the signal processor 92 is subjected to decoding processing according to the contents of the buffer control unit 91.
And the result is output to the DA converter 93. Next, the processing inside the signal processor 92 will be described with reference to FIGS.

FIG. 10 is a flowchart showing an input control method of the signal processor in FIG. First,
After the power is turned on (step 101), when the vacant flag is received N times consecutively (step 102), it is determined that there is no reception data, and the input is stopped (step 103). After that, the delay flag D in the reception buffer
By detecting F = ON (step 104), the input to the signal processor DSP is started again (step 105). This is because a delay corresponding to the position of the delay flag is inserted on average in the buffer to absorb the delay fluctuation of the network. When inputting data to the signal processor DSP, an empty flag is set to N.
It is continued until it receives continuously. When the empty flag is continuously received N times, the input to the signal processor DSP is stopped for the first time.

FIG. 11 is a processing flowchart in the case of replacement with the processing contents relating to the empty flag. When the empty flag is detected (step 111), the decoder outputs the final sample at that time (step 112). As a result, as shown in the final sample replacement in FIG. 8, the signal replaced with the final sample is output in the blank period, and in the case of voice, the final sample can be continuously heard in the ear of the receiver. And the sense of incongruity disappears. If the empty flag is not detected, the data is read from the FIFO (step 113) and the signal processor performs the decoding process. FIG. 12 is a processing flowchart in the case of interpolation with the processing contents regarding the empty flag. First, when a packet is received (step 121), the signal processor DSP at that point calculates an average power P (step 122). If the empty flag is detected during the reception of the next packet (step 123), the signal processor generates white noise of mean = 0 and variance = P until the next packet is received (step 124). As a result, as shown by the white noise interpolation in FIG. 8, white noise is interpolated and output in the blank period, so that the white noise can be heard in the ear of the receiver. That is, if there is a space in the middle, the sound volume will be distorted, but the white noise will be inserted there, and the discomfort will disappear. If the empty flag is not detected (step 123), the process of reading the data from the FIFO is continued as usual.

[0018]

As described above, according to the present invention,
Even if an independent synchronous packet network such as FDDI-I originally designed for data communication is used, the quality of continuous media such as video and audio is not deteriorated, and the partner station is maintained.
Can be transferred to the application. Further, as an application of the present invention, it is possible to hold a conference between a plurality of stations by the broadcast function of the LAN.

[0019]

[Brief description of drawings]

FIG. 1 is an overall block diagram of a packet communication device showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a conventional FDDI-I and FDDI-II synchronization method.

FIG. 3 is a diagram showing a conventional FDDI-I communication model.

FIG. 4 is a block diagram of a main part of the synchronization control device showing the first embodiment of the present invention.

5 is a block diagram of a main part of a synchronization control device showing a modified example of FIG.

FIG. 6 is a diagram showing a flag configuration in a reception buffer in the synchronization control method according to the second embodiment of the present invention.

FIG. 7 is a diagram showing an example of thinned-out output in the synchronization control method of the second embodiment.

FIG. 8 is a diagram showing an example of replacement and interpolation output of the synchronization control method of the second embodiment.

FIG. 9 is a diagram showing the structure of a voice CODEC showing a third embodiment of the present invention.

FIG. 10 is a flowchart showing an input control method of the signal processor of the present invention.

FIG. 11 is a flowchart showing the processing at the time of replacement in FIG.

12 is a flow chart showing the processing contents at the time of interpolation in FIG.
It is a chart.

[Explanation of symbols]

1 Dependent Synchronous Link by Clock Frequency of Master Station 2, 3, 4, 5 Independent Synchronous Link by Clock Frequency of Each Station 11 Media Input Circuit 12 Encoding Circuit 13 Packet Generation Circuit 14 Frequency Transmission Circuit 15 Variable Divider Circuit 16 up-down counter 17,18 OR circuit 20,21 packet buffer 19,22 flag generation circuit 23,24 decoding circuit 25 media output circuit 26 packet network 90 network interface section 91 buffer control section 92 signal processing Processor (DSP) 93 AD / DA converter 94 Timing circuit 95 Analog interface unit

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 12/42

Claims (9)

[Claims] 1. A packet communication apparatus for performing bidirectional packet communication between a network of independent synchronization and a plurality of terminals connected to the network by using a temporally continuous medium. A plurality of packet buffers for respectively accumulating packets from a plurality of terminals, a means for monitoring the data overflow and underflow for each packet buffer, and an monitor from each monitor means for each packet buffer. First OR means for ORing the buffer flow signals, and second OR means for ORing the underflow signals from the monitor means for each packet buffer,
An up-down counter that uses the output from the first and second OR means as an up signal and a down signal, and a variable frequency dividing circuit that changes a frequency division ratio according to a carry signal from the up-down counter, A packet communication device comprising: a control unit that controls the input and output timings of each medium according to the output frequency of the variable frequency dividing circuit. 2. The packet communication device according to claim 1, wherein a decoding circuit is provided for each output of the plurality of packet buffers, and the decoding circuit decodes packets from a plurality of points respectively. A packet communication device, wherein each decoded data is input to a media output circuit, and output timing of each media of the media output circuit is controlled by an output frequency of a variable frequency dividing circuit. 3. The packet communication device according to claim 1, wherein the control means controls only the output timing of each medium according to the output frequency of the variable frequency dividing circuit. 4. The packet communication device according to claim 1, wherein the input timings of the plurality of media are kept in a pre-synchronized integer multiple relationship, whereby variable frequency division is performed for media having a short control cycle. A packet communication device characterized in that a frequency division ratio of a circuit is controlled and a common variable frequency division circuit is used to maintain a synchronization relationship between a transmission side and a reception side for a medium having a long control cycle. 5. The packet communication device according to claim 1, wherein the plurality of media are temporally continuous audio signals or video signals. 6. A packet communication method for performing bidirectional packet communication between a network of independent synchronization and a plurality of terminals connected to the network using a temporally continuous medium, wherein each receiving terminal For each of a plurality of packet buffers that store packets from a plurality of terminals for each, monitoring the data overflow, underflow, and delay limit, a full flag indicating that each has been detected, a free space A packet communication method comprising: setting a flag and a delay flag, and controlling the decoding operation of a decoding circuit for decoding the output of each packet buffer by turning on and off the full flag, the empty flag and the delay flag. 7. The packet communication method according to claim 6, wherein when the overflow is monitored and an overflow is detected, the data accumulated in the packet buffer is read at a normal read speed. A packet communication method characterized by reading at a speed of K times and thinning out and inputting to the decoding circuit every K samples. 8. The packet communication method according to claim 6, wherein when the underflow is detected and the underflow is detected, the final data stored in the decoding circuit is repeated or the underflow is performed. A packet communication method characterized in that the data immediately before the detection and the reception data immediately after the underflow are interpolated with the data in the underflow period. 9. The packet communication method according to claim 6, wherein the up / down counter according to claim 1, together with a process for controlling the operation of the decoding circuit by turning on / off the full flag, the empty flag and the delay flag. The packet communication method is characterized in that the frequency division ratio of the variable frequency dividing circuit is changed by a carry signal from the device and the processing for controlling the input and output timings according to the output frequency of the variable frequency dividing circuit is also used.