JPH066265A - Equalizer - Google Patents

Abstract

PURPOSE:To provide an equalizer in which an excellent equalizing characteristic can be obtained even in the case there is a timing offset in a sampling clock. CONSTITUTION:This device is constituted of a sampling means 1 which operates the sampling of a signal inputted from an input terminal 5 by the sampling clocks whose phases are different, and prepares plural reception signal sequences, a sequence selecting means 2 which selects and outputs the designated section of the preliminarily designated reception signal sequence, an equalizing means 3 which equalizes the signal inputted from the sequence selecting means 2, outputs an equalization error, and outputs a judgement signal from an output terminal 6, and a control means 4 which searches an SN obtained by dividing the sum of squares of the reception signal at the time of designating and equalizing the certain section of each reception signal sequence by the sum of squares of the equalization error of the same section, and controls each means so that the entire sections of the reception signal sequence in which the SN of the reception signal sequence can be the maximum can be designated and equalized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer, and more particularly,
The present invention relates to an equalizer that suppresses deterioration of transmission characteristics due to intersymbol interference in digital communication.

[0002]

2. Description of the Related Art In digital communication, there is an equalizer as a technique for suppressing deterioration of transmission characteristics due to intersymbol interference.

As one of effective equalizers, maximum likelihood system estimation (M
aximum Likelihood Sequence Estimation (MLSE) is known. This equalizer calculates the likelihood corresponding to a possible signal sequence, and selects the signal sequence having the largest value in signal determination. As the signal sequence gets longer, the number of all possible signal sequences grows exponentially.

Therefore, in order to reduce the number of sequences and suppress the amount of calculation, there is known a Viterbi equalizer for performing state estimation by a Viterbi algorithm.

A conventional receiver including an equalizer will be described. FIG. 5 shows the configuration of a conventional receiver. This receiver includes an input terminal 51, an A / D converter 52, a memory 53, an equalizer 5
4 and two output terminals 55 and 56.

When the received signal is input from the input terminal 51, the A / D converter 52 samples the received signal and converts it into a digital signal. Here, the received signal sample value includes a modulated wave having a symbol period T, and the sampling period is T. The received signal sample value is stored in the memory 53.
Is temporarily stored in the equalizer 54, and after the burst synchronization and the clock synchronization are established, the equalizer 54 extracted from the memory 53
Will be input. The equalizer 54 equalizes the received signal and makes a signal decision, and outputs the decision signal from the output terminal 55.
The equalization error is output from the output terminal 56. The equalization error output from the output terminal 56 is the difference between the received signal sample value and the received signal estimated value when the MLSE is used for the equalizer 54.

The burst structure of the transmission signal will be described below. The signal input from the memory 53 to the equalizer 54 is transmitted in a burst configuration as shown in FIG. 6, and a known signal called a training signal is followed by a data signal. The equalizer 54 performs initialization using this training signal, equalizes the received signal in the data signal section, and performs signal determination.

[0008]

However, in the above-described sampling clock and equalization characteristics of the prior art, there is a problem that the characteristics of the equalizer deteriorate due to the offset of the timing of the sampling clock. FIG. 7 shows the sampling state of the received signal. However, this figure shows a signal waveform without waveform distortion and noise. In the figure, T represents the sampling period, and the alternate long and short dash line represents the threshold value for signal determination. When the timing offset of the sampling clock is 0, it corresponds to sampling 1 in the figure, and when the timing offset is T / 2, it corresponds to sampling 2 in the figure.

In the above sampling clock and equalization characteristics, when the timing offset is 0, the level of the received signal sampling value is always constant, but when the timing offset becomes about T / 2, the level becomes extremely small. There are cases. In the presence of noise, the characteristic of the equalizer deteriorates when the level of the received signal sampling value decreases, so that the characteristic of the equalizer deteriorates due to the timing offset of the sampling clock.

As described above, in the structure of the receiver including the conventional equalizer, since the sampling period matches the symbol period, there is a drawback that the equalization characteristic is significantly deteriorated by the timing offset of the sampling clock. .

The present invention has been made in view of the above points, and an object of the present invention is to provide an equalizer capable of obtaining excellent equalization characteristics even when a sampling clock has a timing offset.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention.

The equalizer of the present invention comprises a sampling means 1 for sampling a signal inputted from the input terminal 5 with sampling clocks having mutually different phases, and a sampling means 1 for generating a plurality of received signal sequences, and a previously designated received signal sequence. , Which selects and outputs the designated section, and the equalizer 3 which equalizes the signal input from the series selecting unit 2 to output an equalization error and outputs a determination signal from the output terminal 6. When,
The SN ratio obtained by dividing the sum of squares of the received signal when equalization is performed by designating a certain section of each received signal sequence by the sum of the squares of equalization errors in the same section is calculated. And a control unit 4 for controlling so as to specify and equalize all sections of the maximum received signal sequence.

[0014]

The present invention prepares a plurality of received signal sequences sampled by sampling clocks having different phases, and divides the sum of squares of received signals in a certain section by the sum of squares of equalization error in the same section. Is calculated and controlled so as to equalize the received signal sequence having the maximum SN ratio value, thereby estimating the optimum sampling point of the received signal even when the sampling clock has a timing offset.

[0015]

FIG. 2 shows the structure of a receiver according to an embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted.

The receiver shown in the figure has an input terminal 5 and an A / D.
Converters 11, 12, 13, memories 14, 15, 16, selector 20, equalizer 30, control circuit 40 and output terminal 6
It is composed of

When a received signal is input from the input terminal 5,
The A / D converters 11, 12, and 13 sample the received signals by sampling blocks having different phases, convert them into digital signals, and receive signal sequences S1, S2, S3.
Is generated and further input to the memories 14, 15 and 16.

The memory 14 temporarily stores the received signal series S1, the memory 15 temporarily stores the received signal series S2, and the memory 16 temporarily stores the received signal series S3. Memories 14, 15, 16
The received signal sequences S1, S2, S3 stored in the memory 1 are stored in the memory 1 after the burst synchronization and the clock signal are established.
Taken from 4-16. At this time, the memory 11, 1
Received signal sequences S1, S2, S that are outputs from
One out of three is selected and output. After all, memory 1
As for the outputs of 4, 15, and 16, the designated section of the designated received signal sequence is output.

The equalizer 30 receives the output of the selector 20 as an input, equalizes the received signal and outputs a determination signal from the output terminal 6, while inputting an equalization error to the control circuit 40.

The control circuit 40 controls the memories 14, 15, 16 and the selector 20 using the equalization error and the output of the selector 20.

The operation of the control circuit 40 will be described below. FIG. 3 is a diagram for explaining the operation of the control circuit according to the embodiment of the present invention.

First, the control circuit 40 determines that the received signal sequence S
The memories 14 to 16 and the selector 20 are controlled so as to output the received signal sequence corresponding to one training signal section. From time t ₀ to time t ₁ , the equalizer 30 receives the received signal sequence corresponding to the training signal section of the received signal sequence S1.

During this time, the control circuit 40 outputs from the equalizer 30.
The received equalization error and the output of the selector 20 are used to
Received signal in the training signal section of the signal sequence S1
SN ratio obtained by dividing the sum of squares of the number by the sum of squares of the equalization error
It Similarly, time t₁From time t₂Between the received signal system
Training signal section of column S2, time t₂From time t ₃
Between the training signal section of the received signal sequence S3
So that the corresponding received signal sequence becomes the output of the selector 20.
Control. Then, it corresponds to the received signal series S2, S3.
Calculate the SN ratio. The better the SN ratio, the better the equalization characteristics.
Therefore, time t₃Signal system with maximum SN ratio in
Determine the sequence and equalize the entire section of the received signal sequence.
Control.

When the difference between the sums of squares of the received signals is not significant in each received signal series, a simple method of selecting the received signal series having the smallest sum of squares of the equalization error can be considered.

In the above embodiment, the designated section is the training signal section, and the SN in this section is set.
Although the ratio is obtained, it may be a part of the data signal section or the training signal section.

FIG. 4 is a graph of a simulation result showing the effect of the present invention, in which a computer simulation is performed in order to confirm the effect. In the figure,
The vertical axis represents the bit error rate, and the horizontal axis represents the timing offset.

The modulation method is QPSK with a roll-off rate of 0.5.
Applying the RLS algorithm to modulation and channel estimation,
The forgetting factor λ was 0.8. The transmission line model is the delay time
A 1T two-wave static model, in which the preceding wave and the delayed wave are at the same level.
Phase difference is 0 and E_b/ N ₀= 8 dB. White circle mark
Shows the result of the simulation with the conventional configuration.
The circles indicate the results of the simulation according to the configuration of the present invention.
Indicates. As can be seen from the figure, when the present invention is applied
Shows that deterioration is suppressed except near the timing offset value 0.
It is obtained. Especially when the offset is ± T / 2
The fruit is big.

As is clear from the result of FIG. 4, the deterioration due to the timing offset can be suppressed as compared with the conventional technique.

[0029]

As described above, according to the present invention, the sum of squares of the received signal in a certain section is equal to the equalization error of the same section, which is equal to
Since the optimum sampling point of the received signal is estimated by using the control device that obtains the SN ratio divided by the sum and controls so that the SN ratio is maximized, equalization is performed even when the sampling clock has a timing offset. The vessel works well.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a receiver according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the control circuit according to the embodiment of the present invention.

FIG. 4 is a graph of simulation results showing the effect of the present invention.

FIG. 5 is a block diagram of a receiver including a conventional equalizer.

FIG. 6 is a configuration diagram of a burst signal.

FIG. 7 is a diagram showing a sampling state of a received signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sampling means 2 Sequence selection means 3 Equalization means 4 Control means 5 Input terminal 6 Output terminal 11 A / D converter 12 A / D converter 13 A / D converter 14 Memory 15 Memory 16 Memory 20 Selector 30 Equalizer 40 Control Circuit 51 Input Terminal 52 A / D Converter 53 Memory 54 Equalizer 55 Output Terminal 56 Output Terminal

Claims (1)

[Claims] 1. Sampling means for sampling a reception signal with sampling clocks having mutually different phases to generate a plurality of reception signal sequences, and sequence selection for selecting and outputting a designated section of a reception signal sequence designated in advance. Means, an equalization means for equalizing the signal input from the sequence selection means and outputting a determination signal and an equalization error, and a received signal when equalizing is performed by designating a certain section of each received signal sequence The sum of squares of is divided by the sum of squares of equalization errors in the same section to obtain an SN ratio, and all sections of the received signal series having the maximum SN ratio of the received signal series are designated and equalized. An equalizer comprising: control means for controlling.