JPH066207A - Metal semiconductor field-effect transistor logic circuit - Google Patents

Abstract

PURPOSE: To obtain an MESFET circuit having low power loss, low output and high level by providing a means for limiting the value of the 'high' voltage level of a signal generated at the output of a circuit without largely affecting to the response speed of the signal. CONSTITUTION: A super buffer logic(SBL) circuit 50 is composed of a depletion MESFET (DMESFET) T1, an enhancement MESFETs (EMESFET) T2 to T6, and an output node D connected to a load circuit 52. During the SBL circuit is 50, T1 and T2 function as pull-up load devices, T3 functions as a source (voltage) follower pull-up transistor, T5 and T6 function as switching (driver) devices, and T4 functions as a feedback device used to control the maximum amplitude of a 'high' output succeeded in the output node D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to an integrated logic circuit realized by compound semiconductor technology such as gallium arsenide (GaAs).

[0002]

It has been found that circuits implemented in compound semiconductor technology such as gallium arsenide can operate much faster than circuits implemented in silicon technology. This is because GaAs has electron mobility several times faster than silicon, and its electron drift velocity is also faster than silicon. High electron mobilities and drift velocities reduce power loss and allow for faster information transfer. Gallium arsenide technology can be used in the manufacture of transistors known as metal semiconductor field effect transistors (MESFETs). Circuits utilizing MESFETs are described below, for example. 1. U.S. Pat. No. 4,663,543, inventor switch, name "voltage level shift depletion mode FET logic". U.S. Pat. No. 4,716,311; Inventor Davenport et al., Entitled "Direct-Coupled FET Logic with Spar Buffer Output Stage." U.S. Pat. No. 4,724,342, Inventor Sato et al., "Push-pull DCFL drive circuit" 4. US Pat. No. 4,844,563, inventor Macmillan et al., Entitled "Semiconductor integrated circuit compatible with composite standard logic signal"

However, known circuits using MESFETs have some disadvantages and problems, which are best explained with reference to the prior art circuits shown in FIGS.

Referring now to FIG. 1, US Pat. No. 46
FIG. 4 of the 63543 specification is reproduced. However, in FIG. 1, an error is added to the reference code in the drawing of the same patent, and an additional code is added for ease of explanation. In FIG. 1, n
Channel depletion type MESFET (DMESF
ET) Input inverting stage composed of Q1a, Q1b, Q3, and depletion type MESFET (DMESFET) Q2
An output stage consisting of a and Q2b is shown. Each MESF
The ET has a source electrode, a drain electrode, a conductive path between the source electrode and the drain electrode, and a gate electrode.
The conductive path of Q1a (which functions as an input switching (driver) transistor) is connected between the terminal 101 and the ground potential. A conductive path of Q1b (which functions as a load transistor) is connected between the terminal 101 and the power terminal 103, and the power terminal 103 is applied with a potential of V _DD volt which is assumed to be 1.5V, for example. The conductive path of Q3 (which functions as a variable load resistor) is the power terminal 10
3 and the gate of Q1b. The terminal 101 is
Q2b, which functions as the output node of the input inversion stage and functions as the pull-up voltage (source) follower transistor
Connected to the gate. The conductive path of Q2b is connected between the power terminal 103 and the output terminal 105. The conductive path of Q2a (which functions as a switching (driver) pull-down transistor) is connected between the output terminal 105 and the ground potential. The gates of Q1a and Q2a are commonly connected to an input terminal 107 to which an input signal is applied.

When the input signals applied to the gates of Q1a and Q2a are "high" or "1", Q1a and Q2a are turned on and the output signal of the output terminal 105 is "low" or "0". It's close to the ground potential. However, as explained below, all transistors in this circuit conduct when the input is "1". As a result, undesirably high power losses occur. The current passes through Q3 and Q1b, and Q1a
Flows to the ground through the conductive path of. Q3, Q1b, Q1a
Are rated to produce a "low" voltage at terminal 101. The "low" voltage at this terminal 101 is Q2
Q2b is applied to the DESFET
And has a negative threshold voltage (V _TD ) assumed to be equal to −0.5V. Therefore, Q2b conducts when Q2a turns on. As a result, significant power dissipation occurs during steady state operation. Since Q2b acts as a source follower, Q2a neutralizes the conduction of Q2b,
In order to pull down output terminal 105 near ground potential, it must be relatively large (ie, have a relatively small impedance). Furthermore, output terminal 1
The "0" s that occur at 05 cannot be connected directly to the gates of other DMESFETs to turn them off. Therefore, the output level of the output terminal 105 must be shifted downward to turn off the other DMESFETs. This level shifting requires an additional (negative) operating voltage. Some of the problems with the circuit of Figure 1 are:
As shown in FIG. 2 of this specification corresponding to FIG. 1b of US Pat. No. 4,724,342, transistors Q1a, Q
2a and Q2b are enhanced MESFETs (E
It can be solved by replacing it with MESFET).

Referring now to FIG. 2, transistor Q
Prior art circuits are shown including 7a, Q7b, Q8a, Q8b. Transistors Q7a, Q8a, Q8b
Is an enhancement type MESFET (EMESFE
T) and Q7b is a DMESFET. In the following description, it is assumed that the EMESFET has a threshold voltage (V _T ) of about 0.15V. Therefore EME
SFET has a gate-source voltage (VGS) of V _T.
It does not conduct unless it is larger than (that is, 0.15 V). It is assumed that when Q7a and Q8a turn on, Q7a turns on and pulls down the voltage at terminal 101 to within 0.15V of ground potential and the voltage at output terminal 105 is at or near ground potential. The gate-source voltage of Q8b is then less than 0.15V. Therefore,
In FIG. 2, when Q7a and Q8a are turned on, Q8b is non-conductive. As a result, the power loss is reduced and Q8a
And many constraints on the design of Q8b are relaxed. Further, the use of the EMESFET of FIG. 2 eliminates the need to shift the output level of this circuit and the need to supply a negative voltage.

However, the "high" output that occurs in the circuit of FIG. 2 as well as the circuit of FIG. 1 is the output of that circuit (output terminal 10).
5) has a tendency to overdrive the MESFET connected to. Referring to FIG. 2, when the input applied to input terminal 107 is "low", thus turning off transistors Q7a and Q8a, the DMESFET
Q7b drives the gate of Q8b to V _DD volts, which causes the output voltage of the source of Q8b to go from V _DD to Q _DD.
Note that it is approximately equal to 8b minus the V _T volt. Assuming V _DD = 1.5V and V _T = 0.15V, the voltage at output terminal 105 is at or near 1.35V with little or no load on output terminal 105. The ability to drive the output high is even more pronounced in the circuit of FIG. When Q1a and Q2a are turned off, DMESFETs Q3, Q1b and Q2b are
The voltage at the output terminal can be driven near V _DD volts.

When an output signal close to V _DD volts occurs at output terminal 105, such an output signal is generated at output terminal 10
Since it overdrives the load circuit connected to 5,
The problem occurs. This can best be explained with reference to FIG. In FIG. 3, the output terminal 105 is MESFET.
It is connected to the gate of TL and the source electrode of this TL is returned to the ground potential. The MESFET TL has an output terminal 10
5 represents the input of any one of a number of different stages that can be connected. For ease of explanation, MESFETTL
Enhancement-type n-channel MESFET (EMES
FET). As shown in FIG.
The gate of the FET (eg TL) has its MESFE
It is accompanied by a Schottky diode (DA or DB, shown in phantom in FIG. 3), with a polarity that conducts normal current from the gate to the source or drain of T. Each of these Schottky diodes has a forward voltage drop (Vf) and voltage-current characteristic of the type shown in FIG.

Referring now to FIG. 4, when the anode-cathode voltage in volts (X-axis) exceeds the value V _F , the diode current in milliamps (Y-axis).
There is shown a graph with a sharp increase. This value V
_In the following explanation, _F is about 0.7V for ease of explanation.
Suppose that Therefore, the output signal of the output terminal 105 is V of the parasitic diode related to the input of the succeeding stage.
_{When F} (eg, 0.7 V) is exceeded, signal voltages above V _F volts are clamped by the forward biased parasitic diode. If the TL is an EMSESFET, its threshold voltage (V _T ) is about 0.15V, and such a MESFET turns on strongly before its gate-source voltage (VGS) equals 0.7V. Please note that. Therefore, V _DD is in the range of 1.5V, when the output signal rises toward the V _DD volts exceed V _F volts, the output voltage of the output terminal 105 of greater than V _F bolts driven circuit Has almost no effect on increasing the response speed of. However, this actually overdrives the inputs of subsequent stages. Two problems arise when the inputs of the subsequent stages are overdriven.
One of the problems is the unnecessary increase in power loss. Another problem is that this parasitic diode can couple false signals and noise into the drain or source circuits of the subsequent stage.

Another problem with the circuit of FIG. 2 is the EM
In the drain circuit of Q7a which is ESFET, DMESF
Providing ET Q7b is undesirable. This is because depletion type devices and enhancement type devices are formed using different process steps and their characteristics do not match and do not follow.

[0011]

While providing the functions of the prior art circuits described above, it is desirable to provide a MESFET circuit that has low power dissipation and low output high ("1") level.

[0012]

SUMMARY OF THE INVENTION The present invention comprises means for limiting the value of the "high"("1") voltage level of a signal produced at the output of a circuit without significantly affecting the speed of response of the signal. Intended for circuits. An exemplary circuit according to the present invention has first and second metal semiconductor field effect transistors (MESFETs) having source and drain electrodes and gate electrodes, respectively, that define the ends of the conductive paths.
Equipped with.

The conductive path of the first MESFET is connected between the first power terminal and the first output terminal. Second MESFE
A conductive path of T is connected between the output terminal and the second power terminal. An operating potential is applied between the first power terminal and the stage 2 power terminal. The gate of the first MESFET is coupled to a first means for selectively turning it on, which first means seeks to drive the voltage at the output terminal to the value of the voltage applied to the first power terminal. To do. The gate of the second MESFET is coupled to second means for selectively turning it on and clamping the output terminal to the voltage level applied to the second power terminal. The feedback means has an output terminal and a first
A first MESF coupled between the gates of the MESFETs.
Limits the value of the voltage developed at the output terminal when ET turns on and the second MESFET turns off.

In the preferred embodiment, the steady state value of the voltage developed at the output terminal when the first MESFET is turned on is:
Limited to values close to V _F. However, when V _F exceeds that value, the diode current of the parasitic diode existing between the gate and the source of each MESFET rapidly increases,
It is the value of the forward voltage drop.

In a circuit embodying the present invention, the feedback means preferably comprises a third MESFET whose conductive path is connected between the reference potential point and the gate of the first MESFET, the gate of which is connected to the output terminal. .

In a circuit embodying the present invention, a first MESF
The first means for controlling the turning on and off of the ET includes a fourth MESFET having its conductive path connected between the first power terminal and the gate of the first MESFET, and a conductive path between the gate of the first MESFET and the second power terminal. 5th M to which the route is connected
An ESFET is preferably provided.

In the preferred embodiment of the present invention, the first to fifth MESFETs are preferably enhancement type transistors.

In another aspect, the present invention provides first and second power terminals to which an operating potential is applied, and first, second, third, fourth and fifth metal semiconductor field effects. A circuit including a transistor (MESFET) is targeted. Each MESFET has a source electrode and a drain electrode that define the end of the conductive path, and a control electrode. The first MESFET is a depletion type MESFET, and the second to fifth MESFETs are enhancement type MESFETs. The drain of the first MESFET is coupled to the first power terminal and its source and control electrode are coupled to the control electrode of the second MESFET. Second M
The source of the ESFET is coupled to the control electrode of the third MESFET and the drain electrode of the fourth MESFET. Second M
The drains of the ESFET and the third MESFET are coupled to the first power terminal. The drain of the fifth MESFET is coupled to the source of the third MESFET. 4th MESFE
The sources of T and the fifth MESFET are coupled to the second power terminal and the control electrodes of the fourth MESFET and the fifth MESFET are coupled to each other.

The present invention will be better understood upon consideration of the detailed description below in conjunction with the accompanying drawings and claims.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings, like reference numbers indicate like elements.

A circuit embodying the invention is illustrated using an n-channel metal semiconductor field effect transistor (MESFET) formed in gallium arsenide technology. However, it should be understood that, instead, transistors having similar characteristics formed using other techniques may be used. In the embodiment of FIG. 5, each MESFET is typically formed in a semi-insulating gallium arsenide substrate and has an n-channel MES.
It is a FET.

Each MESFET has two main electrodes, which define the ends of the conductive path, called the source and drain, and
It has a control electrode (gate) whose potential is applied to determine the conduction state of the conductive path. n-channel MESFE
For T, the source is defined as the electrode of the two main electrodes to which the lower positive potential is applied. MESFET
Is bidirectional in the sense that when an enable signal is applied to the gate (control) electrode, current can flow in either direction in the conductive path defined by the first electrode and the second electrode. .

Referring to FIG. 5, a super buffer logic (SBL) circuit 50 according to the present invention is shown. S
The BL circuit 50 is a depletion type MESFET (DM
ESFET) T1, enhancement type MESFET
(EMESFET) T2, T3, T4, T5, T6, and an output node D coupled to load circuit 52 (shown in the dashed rectangle). The drain of the DMESFET T1 is connected to the power terminal 24, and the power terminal 24 has a +
An operating voltage of V volts is applied. The source and gate of T1 are connected to node B, and EMESFET is connected to node B.
The gate of T2 is also connected. The drain of T2 is connected to the power terminal 24, its source is connected to the node C, and the gate of T3, one end of the conductive path of T4 (electrode 41) and the drain of T5 are also connected to the node C. T5
Is connected to the terminal 26, and the ground potential is applied to the terminal 26. The drain of T3 is connected to the power terminal 24, its source is connected to the output node D, and the gate of T4 and the drain of T6 are also connected to the output node D. T
The source of 6 is connected to terminal 26. The other end (electrode 42) of the conductive path of T4 is connected to the terminal 45, and the reference potential V _REF is applied to the terminal 45.

As discussed below, during operation of the SBL circuit 50, T1 and T2 function as pull-up load devices, T3 functions as a source (voltage) follower pull-up transistor, and T5 and T6 , T4 as a switching (driver) device, and T4 as a feedback device used to control the maximum amplitude of the "high" output produced at output node D.

The output node D of SBL circuit 50 is coupled to the gate of MESFET T7, which serves as the input of load circuit 52. The portion of the load circuit 52 shown in FIG.
Enhancement MESFETs T7 and T8,
Includes a depletion type MESFET T9. MESF
ET T7, T8, T9 interconnects are each MES
It is similar to the interconnection of FETs T1, T2, T5.
The source of T7 is connected to the terminal 26, the drain thereof is connected to the node E, and the source of T8 is connected to the node E. The drain of T8 is connected to the power terminal 24,
Is connected to the gate and source of T9, and the drain of T9 is connected to the power terminal 24. The output node D of the SBL circuit 50 is shown as a single EMESFET T7.
Connected to. However, other MESFET (not shown)
The gate electrode and source electrode of is connected in parallel with T7,
It should be appreciated that these other MESFETs could also be used to drive different nodes of load circuit 52 or other circuits.

In order to better explain and understand certain aspects of the present invention, some parasitic Schottky-like diodes associated with some MESFETs are shown in dashed lines in FIG. The parasitic Schottky diode that exists between the gate and source of a typical transistor Ti (not shown) is shown in dashed lines and is designated DiA. The parasitic Schottky diode existing between the gate and the drain is represented by DiB. For example, transistor T3 has associated parasitic diodes D3A and D3B.

The operation of the SBL circuit 50 of FIG. 5 is, for example, + V volt = 1.4V, V _REF = 0.3V, enhancement type MESFET (EMESFET) threshold voltage (V _T ) = 0.15V, depletion type. MESF
ET (DMESFET) threshold voltage (V _TD ) = − 0.
5V, a simpler explanation, assuming a forward voltage drop value V _F = 0.7V when the parasitic Schottky diode begins to conduct significant current.

It is also assumed that the binary input signal ei is applied to the input node A to which the gate electrodes of the transistors T5 and T6 are connected. The input signal ei is either 0V or a first value near 0V, also referred to as a "low" or logic "0" state, or exceeds the threshold voltage (eg 0.15V) of the switching EMSESFET (ie T5, T6), both of which Takes on either a "high" or a second value called "1" that strongly turns on. If a high value is produced by a circuit (not shown) that does not incorporate the present invention,
The "high" value of the input signal can be significantly greater than 0.7V. The response of this circuit to the two different binary states will now be described in detail.

First, assume that the value of the input signal ei is "high" (that is, 0.7V), sufficiently higher than the threshold voltage V _T (that is, 0.15V) of T5 and T6, and both of them are strongly turned on. To do. When T5 is on, current flows through the conduction path of T1 to node B, from node B to node C through parasitic diode D2A that conducts in the forward direction, and to the ground through the conduction path of T5. . Current is +
The current also flows from V to the drain of T5 through the conductive path of T2. Note that T2 is on because the V _T of T2 is 0.15V and the V _F of D2A (which branches from the gate to the source of T2) is 0.7V. Therefore, T2 is completely conductive. Since T2 is conducting and tries to pull up the node C toward + V, T5 cannot clamp the node C to the ground potential although it is in the strong ON state. However, the impedance of the conductive path of T2 and T5 becomes equal to approximately 0.15V at node C when T5 is strongly turned on, and the voltage at node B becomes approximately 0.85V due to the voltage drop across D2A. Is designed to be equal to. e
The voltage states of the node B, the node C and the output node D when i is "high" are shown at time t1 in FIG.

Referring to FIGS. 6 and 7, the input node A (ei), the node B (eB), and the node C (where the Y-axis is voltage (volt) and the X-axis is time t (nanosecond). eC)
And a graph of the voltage waveform at the output node D (eD) is shown. At the same time, a "high" (ei = "1") is applied to the gate of T6, turning it on strongly. When T6 is strongly turned on, it clamps the voltage of the output node D to the ground potential or pulls it down to the vicinity thereof. This occurs because the source follower transistor T3 (with 0.15V applied to its gate) is turned off or close to it. Therefore, when the input signal ei is "high", the output signal of the output node D is at ground potential or very close to ground potential (this is
Corresponds to a "low" or logic "0" state). When T6 turns on, feedback transistor T4 turns off. This is because 0V existing at the output node D is applied to its gate, the electrode 41 of T4 (connected to the node C) is 0.15V, and the electrode 42 of T4 (terminal 45).
Connected to) is 0.3V. Therefore, T4 has a gate (0V), a source (electrode 41) 0.15V, and a drain (electrode 4) T4.
Since 2) is 0.3V, it is strongly turned off. If the signal at output node D is at or near 0V, EMES
FET T7 is turned off and there is no current flowing to ground through its conductive path. However, since T9 is a depletion type device, it conducts and provides a turn-on bias to the gate of T8, which causes the "high" signal at node E.

The input signal ei of the input node A is T = t1
Now consider the operation of this circuit as it goes from "high" to "low" between t2 and t2. When the input signal ei drops below 0.15V, T5 and T6 turn off. As soon as T5 is turned off, T2 has been conducting until then and remains conducting thereafter, so that the voltage at node C rises very sharply towards + V volts, as shown by waveform eC in FIG. The sharp voltage rise at node C is coupled to the gate of T2 at node B through the gate-source capacitance (Cgs2) of T2, causing the voltage at node B to rise, as shown by waveform eB in FIG. . The voltage at node B is
Since it was 0.85 V immediately before T5 was turned off, the voltage increase due to this capacitive coupling can raise the potential of the node B substantially higher than + V volt. Therefore, T2 is turned on more strongly.

During the transition period when T4 is absent and the voltage at nodes B and C is rising very sharply, the output node D
If no load or clamp is applied to V, the voltage at node C can rise to around + V volts and the voltage at output node D will then be (if output node D is not clamped) only V _{T of} T3 above + V volts. It can rise to or near low values. + V on output node D
When a voltage close to Volts (ie, V _T below 1.4 V) occurs, T7 turns on very effectively.
However, whenever the voltage at node D rises above 0.6V, a significant current will flow to ground through parasitic diode D7A. If the voltage at node D rises above the assumed value of V _F (ie, 0.7 V), a significant current will flow through the parasitic diode, and a significant amount of power due to subsequent overdrive of the input of load circuit 52. Is lost. Furthermore, if the gate voltage to T7 is more positive than its drain voltage, current will still flow through the gate-to-drain diode D7B, introducing an unwanted noise signal into the load circuit 52.

The above problem is that feedback MESFET T4, which functions to limit the voltage rise at output node D to a value equal to or near the value of V _F , does not slow the response of SBL circuit 50. Will be solved. The point at which the voltage at node C exceeds the value of V _REF is reached when ei changes from high to low and the voltage at node C rises from 0.15 V to + V volts (or more). At that point, the electrode 41 of T4 begins to function as the drain of T4 and the electrode 42 begins to function as the source of T4.

At the same time, when the voltage at output node D rises above V _REF to V _T volts (ie, 0.15 V), transistor T4 turns on and node C goes to V
I try to lower it towards _REF . The voltage at the output node D is
Higher than V _T + V _REF (ie, V _T = 0.15, V _REF
= 0.4, so that (above 0.45V), T4 turns on more and more strongly, trying to suppress the voltage rise at node C and output node D. When T4 is on, T2 and T4 have a +2 conductive path.
Note that the conductive path of T4 connected between V and node C forms a voltage divider network connected between node C and V _REF . The resulting voltage at node C is
It is a function of the equivalent impedance of T2 connected between + V and node C and T4 connected between node C and V _REF . The ratio of this equivalent impedance is such that the design of this circuit controls the voltage rise at node C, beyond which the voltage at output node D causes a significant amount of current to flow through the parasitic diode, the forward voltage drop V.
The value is such that the value is limited to a value close to the value of _F (that is, 0.7 V). The voltage limit of the node C from time t3 to t4 is shown by the waveform eC, and the voltage limit of the output node D is shown by the waveform eD. Output node D "high" voltage is V
Limiting to a value close to _F volts has a dramatic effect on SBL circuit 50 power dissipation.

Referring now to FIG. 7, there is shown a graph of output current Iout from output node D with and without transistor T4 in SBL circuit 50 of FIG. If there is T4 in the SBL circuit 50 and the steady state voltage at the output node D rises to near V _F volts but does not exceed it, the driven transistors in subsequent stages such as T7 will be very fast and very strong. Note that it turns on. The "high" output voltage limits are switched only after the output voltage at the output node D has risen to a value sufficient to turn them on strongly. This is achieved with very little power loss through the parasitic diodes in the driven stage, since in the steady state it does not exceed V _F of the parasitic diodes in the driven stage. The voltage at the output node D, which is not the case in steady state, may momentarily exceed V _F volts during a switching transition (as shown between times t2 and t3 of waveform eD in FIG. 7). Please note.

It should be understood that the feedback transistor T4 and the load transistor T2 form a voltage divider network in the gate circuit of T3. T2 is typically a much higher impedance (smaller) device than T3, thus allowing T2 and T4 to be relatively small (ie, high impedance, small area) devices. Thus, when T2 and T4 conduct, they form a voltage divider network that limits the "high" value of the output signal without significant power dissipation.

When T4 is combined with T2, T5 is obtained.
It should be appreciated that node C will not float when T6 and T6 turn off, thus making the response time (ie delay) of SBL circuit 50 more predictable. Also, T2 is not EMSESFE but DMESFET.
It should be understood that the reason for T is that, in the absence of clamping and feedback, T2, at steady state, produces a voltage at its source (node C) equal to + V-V _T volts. The voltage at node C is applied to the gate of T3, producing a voltage at output node D equal to (+ V-2V _T ) volts. Therefore, T2 is
ET helps with the task of controlling and limiting the "high" level values that occur at node D.

Another reason for making T2 an EMESFET is that it can be manufactured in the same process as transistors T5 and T3, whose characteristics match and follow those of T5 and T3. This is in contrast to the circuit of FIG. In the circuit of FIG. 2, the device Q7b of DMESFET is connected to the drain circuit of the driver transistor Q7a of EMESFET, but Q7a is
Due to the different process steps used in its manufacture, it may not match and not follow the EMESFET transistor of this circuit.

EMESFET in the drain circuit of T5
One problem that arises from using (eg, T2) is that the load EMESFET must turn on to drive T3 in the follower stage when T5 turns off. In FIG. 5, T2 is D, which functions as a current source.
Turned on by MESFET T1. When T5 turns on, current is drawn through the conductive path of T2 and through the conductive path of T1 and the parasitic diode D2A. T1
Since the gate of is connected to its source, the drain-source current through T1 is limited, and there is some "saturation" even when the drain-source potential increases significantly.
It does not increase beyond the level. Therefore, T1
The electric power loss caused by is controlled. When T5 is off,
T1 and T2 supply a sharp boost to T3
At the same time when is turned on, the output of the output node D
Establish a steady state value of 2V _T volt. Therefore,
The combination of T1, T2, T3, T5, T6 (even without feedback transistor T4) provides an inverting buffer circuit with substantially lower power dissipation than prior art circuits while at the same time providing a fast response. Please understand that it works.

In the SBL circuit 50 of FIG. 5, a single switching transistor (ie, T5) is shown in the input inverting stage and a single switching transistor (ie, T6) is shown in the output stage. Since it is formed in this way, the SBL circuit 50 functions as an inverting circuit. In order for the SBL circuit 50 to function as a 2-input NOR logic gate, the SBL circuit 50 of FIG. 5 is modified as shown in FIG.

Referring now to FIG. 8, two transistors T5 and T51 have their conduction paths at node C.
And transistor T6 connected in parallel between the
And T61 have their conductive paths connected in parallel between node D and ground. Some input signal (ie e
i1) is applied to the gates of T5 and T6 and another input signal (ie ei2) is applied to the gates of T51 and T61. Of course, the other transistors of FIG. 5 are also used to form this 2-input NOR logic gate. The circuit of FIG. 8 is further modified by connecting an additional transistor (in parallel with T5 and T51) between node C and ground to connect node D
An additional transistor (T6 and T61
It should be understood that a three (or more) input NOR gate can be created by connecting (in parallel with).

The SBL circuit 50 of FIG. 5 can be modified to function as a 2-input NAND logic gate, as shown in FIG.

Referring now to FIG. 9, the conductive paths of the two transistors T5 and T52 are connected in series between node C and ground, and the two transistors T6 and T62.
Is connected in series between node D and ground. One input signal (ei1) is applied to the gates of T5 and T6 and another signal (ei3) is applied to the gates of T52 and T62. Of course, the other transistors in FIG.
Used to form this 2-input NAND logic gate. Similar to the discussion above, forming a three-input NAND by stacking the conductive paths of three transistors in series between node C and ground and the conductive paths of three transistors between node D and ground. You can

The feedback network shown in FIG. 5 includes a single transistor whose conductive path is connected between node C and the reference potential V _REF point. However, it should be understood that the invention may be practiced with other circuit configurations.

The examples described herein are intended to be illustrative of the general embodiments of the invention. Various changes can be made without being inconsistent with the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a prior art MESFET circuit.

FIG. 2 is a schematic diagram of a prior art MESFET circuit.

FIG. 3 is a schematic diagram of an exemplary load circuit connectable to the circuit of FIG.

FIG. 4 is a graph showing the voltage-current characteristics of a typical parasitic diode associated with a MESFET.

FIG. 5 is a schematic diagram of a circuit using a MESFET according to the present invention.

6 is a diagram showing waveforms associated with various nodes of the circuit of FIG.

7 is a diagram showing waveforms related to the output node D of the circuit of FIG.

FIG. 8 is a schematic diagram showing a modification to the circuit of FIG. 5 to create a NOR logic gate.

9 is a schematic diagram showing a modification to the circuit of FIG. 5 to create a NAND logic gate.

[Explanation of symbols]

 24 power terminal 26 ground terminal 41 electrode 42 electrode 45 reference potential terminal 50 super buffer logic (SBL) circuit 52 load circuit 101 terminal 103 power terminal 105 output terminal 107 input terminal

Claims (15)

[Claims] 1. A first and a second power terminal to which an operating potential is applied, a source electrode and a drain electrode defining an end of the conductive path, and a gate for controlling a conductive state of the conductive path. A first and a second metal semiconductor field effect transistor (MESFET) having an electrode, comprising:
A conductive path of the ESFET couples the first power terminal to an output terminal of the circuit, a conductive path of the second MESFET couples the output terminal and the second power terminal to a gate electrode of the first MESFET. A first means for selectively turning on the first MESFET to drive the voltage at the output terminal towards the voltage applied to the first power terminal, and coupled to the gate electrode of the second MESFET, Second means for selectively turning on the second MESFET and driving the output terminal to the voltage level applied to the second power terminal; coupled between the output terminal and the gate electrode of the first MESFET. A feedback means for limiting the value of the voltage generated at the output terminal when the first MESFET is turned on. 2. Each MESFET has a parasitic diode between its gate and source that conducts a substantial current when the gate voltage is more positive than the voltage applied to the source by a voltage V _F or more. The circuit of claim 1, wherein the feedback means limits the steady state value of the voltage developed at the output terminal when the first MESFET is turned on to a value close to the V _F. 3. The feedback means includes a third MESFET having a conductive path and a gate electrode, the conductive path of the third MESFET being coupled between a reference potential terminal and the gate electrode of the first MESFET, The circuit of claim 1, wherein a gate electrode is coupled to the output terminal. 4. The first means includes a fourth MESFET having a conductive path and a gate electrode respectively, the second means includes a fifth MESFET, and the conductive path of the fourth MESFET includes the first power terminal and the first power terminal. Coupled between the gate electrodes of the first MESFET,
The conductive path of the fifth MESFET is the first MESF.
Is coupled between the gate electrode of ET and the second power terminal,
The gate electrode of the fifth MESFET is the second MESF.
A circuit according to claim 3, characterized in that it is coupled to the gate electrode of the ET. 5. The first means also includes a sixth MESFET having a conductive path and a gate electrode, the conductive path of the sixth MESFET being coupled between the first power terminal and the gate electrode of the fourth MESFET. The gate electrode of the sixth MESFET is the fourth MES
The circuit according to claim 4, wherein the circuit is connected to the gate electrode of the FET. 6. The first, second, third, fourth, and fifth MESFETs are all enhancement-type transistors, and the sixth MESFET is a depletion-type transistor. Circuit. 7. The second and fifth MESFETs are turned on at the same time and turned off at the same time,
The circuit of claim 5. 8. A switching transistor, which is an enhancement-type metal semiconductor field effect transistor (EMESFET), each EMESFET having a source electrode and a drain electrode and a gate electrode defining an end of a conductive path. Switching EMSESFET
To turn on any one of the above, the voltage applied between its gate electrode and source electrode must exceed the threshold voltage V _T, and each of the EMESFETs described above causes a parasitic diode to operate as a parasitic diode. In an integrated circuit characterized in that it has between the electrodes and conducts a considerable current when the voltage at the gate exceeds the voltage at the source by a forward voltage drop V _F (V _F is greater than V _T ). terminal and an output terminal, in response to the binary signal applied to the input terminal, has a smaller amplitude than V _T is in one binary state, larger V _F than V _T in the other binary state An integrated circuit comprising at least four of said EMESFETs interconnected to form a buffer means for producing a binary signal having a smaller amplitude at said output terminal. 9. A first and second power supply having first and second power terminals to which an operating potential is applied, source and drain electrodes respectively defining an end of a conductive path, and a gate electrode. , Third, fourth and fifth metal semiconductor field effect transistors (MESFETs), the first MESFET is a depletion type MESFET, the second to fifth MESFETs are enhancement type MESFETs, and the drain of the first MESFET is The source and gate electrodes are coupled to the first power terminal, the source and gate electrodes are coupled to the gate electrode of the second MESFET, the source electrode of the second MESFET is coupled to the gate electrode of the third MESFET and the drain electrode of the fourth MESFET, and the second and The drain electrode of the third MESFET is coupled to the first power terminal. A drain electrode of the first 5MESFET, the 3MESFET
A source electrode of the fourth and fifth MESFETs is coupled to the second power terminal, and gate electrodes of the fourth and fifth MESFETs are coupled to each other. 10. A conductive path and a gate electrode,
Sixth ME with reference potential terminal at one end of conductive path
SFET is provided, and the other end of the conductive path of the sixth MESFET is the third MESFE.
10. The circuit of claim 9, wherein the circuit is coupled to the gate electrode of T and the gate electrode of the sixth MESFET is coupled to the drain electrode of the fifth MESFET and the source electrode of the third MESFET. 11. The circuit of claim 10, wherein the sixth MESFET is an enhancement MESFET. 12. A sixth and a seventh MESFET each having a conductive path and a gate electrode, wherein the conductive path of the sixth MESFET is connected in parallel with the conductive path of the fourth MESFET and the conductive path of the seventh MESFET is formed. , The fifth MESFET is connected in parallel with the conductive path of the fifth MESFET.
Circuit. 13. The gate electrodes of the fourth and fifth MESFETs are coupled to the first input terminal, and the gate electrodes of the sixth and seventh MESFETs are coupled to the second input terminal. 13. The circuit of claim 12, 14. A sixth and a seventh MESFET, each having a conductive path and a gate electrode, the source electrode of the fourth MESFET being coupled to the second power terminal via the conductive path of the sixth MESFET, 10. The circuit of claim 9, wherein the source electrode of the fifth MESFET is coupled to the second power terminal via the conductive path of the seventh MESFET. 15. The gate electrodes of the fifth and sixth MESFETs are both coupled to the first input terminal to form fourth and fifth MESFETs.
15. The circuit of claim 14, wherein the gate electrodes of the MESFETs of are both coupled to the second input terminal.