JPH0661324A - Semiconductor wafer defect inspection device - Google Patents

Abstract

PURPOSE:To judge the electric discontinuity or short circuit in a circuit of a semiconductor device by providing a defect judging circuit and a defect information recording circuit. CONSTITUTION:The defect in a pattern information is detected by a defect judging circuit 10 by scanning an ion beam on the surface of a semiconductor wafer, the secondary electron generated by the semiconductor wafer is caught, pattern information is taken in successively, and the defect of the pattern information is detected. The above-mentioned defect of pattern information and the information of defective position are recorded on a defect information recording circuit 11. As a result, the defect on the semiconductor wafer is detected, and whether there is an electric discontinuity or short circuit in the circuit of the semiconductor device can be judged instantaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer defect inspection apparatus capable of detecting a pattern defect on a semiconductor wafer and determining the effect of the defect electrically on a semiconductor device circuit.

[0002]

2. Description of the Related Art Conventionally, pattern defects, particles and the like generated in the process of manufacturing semiconductor devices have been a major cause of reduction in manufacturing yield. A semiconductor wafer defect inspection apparatus is used to detect these pattern defects and particles. Conventionally, although not shown in the drawings, for example, C
There is a semiconductor wafer defect inspection apparatus having a CD camera and an XY stage on which a wafer is mounted. In addition, this apparatus was provided with an optical microscope for further magnifying and observing a defective portion of a semiconductor wafer imaged by a CCD camera.

When inspecting a semiconductor wafer with this semiconductor wafer defect inspection apparatus, first, the semiconductor wafer is placed on an XY stage, the CCD camera and the XY stage are relatively moved in order in the XY directions, and the semiconductor is detected by the camera. The entire surface of the wafer is photographed and inspected for defects such as pattern shorts and disconnections, and the presence of particles. Next, the positions of the optical microscope and the CCD camera are exchanged, and the detected defective portion is enlarged and observed. However, the influence of these detected defects on the semiconductor device was judged only by the size of the defect, and in fact, the influence was found only by a non-defective product inspection after the semiconductor device was completed. It was

[0004]

However, with the high integration of semiconductor devices in the future, it is inevitable that the manufacturing period will be prolonged. In order to increase the manufacturing yield at an early stage, in addition to judging the size of the defects detected by the semiconductor wafer defect inspection device, whether the circuit of the semiconductor device is electrically disconnected or short-circuited on the spot. It has become indispensable to make a judgment.

[0005]

SUMMARY OF THE INVENTION A semiconductor wafer defect inspection apparatus according to the present invention comprises a stage on which a semiconductor wafer is placed, an ion gun for generating an ion beam, and an ion beam deflected in one direction so that the surface of the semiconductor wafer is deflected. A scanning coil for scanning, an inspection area control circuit for moving the stage in a stepwise direction perpendicular to the scanning direction, a scintillation counter for capturing secondary electrons generated from the semiconductor wafer, and the captured secondary electrons. To a pattern signal and store the pattern signals in sequence, a defect determination circuit for determining an abnormality and a defect from the pattern information sequentially output from the signal amplifier, and a defect determination circuit for determining a defect. Defect information storage circuit that stores the defect and the position information of the defect, and a table that displays this defect. And a device.

The present invention as described above provides a semiconductor wafer defect inspection apparatus capable of detecting pattern defects and particles generated in a semiconductor device and, at the same time, determining whether the circuit is electrically disconnected or short-circuited.

[0007]

The present invention will be described below with reference to the drawings. 1 is a block diagram of a semiconductor wafer defect inspection apparatus showing a first embodiment of the present invention.

As shown in the drawing, this semiconductor wafer defect inspection apparatus comprises an ion gun 1 for generating an ion beam,
Lenses 2 and 3 for converging the ion beam, an accelerator 4 for accelerating the ions, a scanning coil 5 for converging the ion beam and scanning the surface of the semiconductor wafer, and scintillation for trapping secondary electrons emitted from the semiconductor wafer. A counter 6, a test region control circuit 8 for moving the sample stage 7 in a direction perpendicular to the scanning direction of the ion beam, and a signal for converting the electrons captured by the scintillation counter 6 into an electric signal and storing it as pattern information. An amplifier 9, a defect determination circuit 10 that determines a defect based on an abnormal periodicity of stored pattern information, a defect information recording circuit 11 that stores an image and position information of the defect, and a CRT 12 that displays a defect information pattern. Have Further, an accelerating power source 13 for applying an accelerating voltage to the other ion gun 1, a lens power source 14 for supplying a lens current, a scanning power source 15 for supplying a current to a scanning coil, and a magnification device 16 for changing a scanning width. Have.

Next, the operation of the semiconductor wafer defect inspection apparatus will be described. First, with the acceleration power supply 13, for example, 30K
A voltage of about eV is applied to the accelerator 4 to accelerate the ion beam extracted from the ion gun. Ga, which is a liquid metal, was used as the ion source. Next, the ion beam is converged by the two lenses 2 and 3 and focused at about 50 nm. Next, this ion beam is scanned by the scanning coil 5 in the Y direction, for example, and the sample stage 7 is moved stepwise in the X direction, for example, every time the ion beam is scanned. As a result, the semiconductor wafer placed on the sample stage is irradiated with the ion beam. Then, secondary electrons sequentially emitted from the semiconductor wafer are captured by the scintillation counter 6. Here, as described above, the sample stage 8 is preset in the inspection area control circuit 8 at the time when the scanning of the scannable range by the scanning coil, that is, the scan range set by the magnification unit 16 is completed. Move in steps. That is, the sample stage 7 is controlled so as to sequentially move within the inspection area set in the inspection area control circuit, scan the ion beam, and automatically continue the inspection. Next, the secondary electrons detected by the scintillation counter 6 are converted into electric signals by the signal amplifier 9 and stored as pattern information. Next, the defect determination circuit 10 is used to detect an abnormality in the periodicity of the stored pattern information, thereby determining whether the defect is a normal pattern.
Next, if a defect is found during scanning with the ion beam, the image of the defect and the position information of the defect are stored in the defect information circuit 11. Separately from this, the pattern information sequentially stored in the signal amplifier 9 is sequentially stored in the CRT 12
Sent to and displayed. Next, when the inspection of the inside of the semiconductor wafer surface is completed, the defect image is observed by the CRT 12. The image of the defect obtained by CRT is SIM (Scanning Ion Micros) using Ga ion limit.
image), the degree of conductivity and insulating property is largely reflected in the image contrast.

FIG. 2 shows an example of an image of a defect detected by the wafer defect inspection apparatus of the present invention.

FIG. 2A is an image in which the conductive wiring 18 is formed on the insulating film base substrate 17, and the pattern defect 19 of the conductive foreign material is detected between the conductive wirings 18. In this case, the contrast of the pattern defect 19 of the conductive foreign matter was almost equal to that of the conductive wiring 18.

On the other hand, FIG. 2B shows an image in which the pattern defect 20 of the insulating foreign matter is detected. In this case, the pattern defect 20 of the insulating foreign matter was obtained with the same contrast as that of the insulating film base substrate 17.

FIG. 2C shows an image in which a disconnection defect 21 is generated in the conductive wiring 18 and the conductive wiring 22 having a different contrast due to charge-up is detected.

In FIG. 2D, a normal contact hole is formed in the conductive wiring 18, whereas a contact hole 24 with poor opening is formed, so that the conductive wiring 22 having a different contrast is detected. It is an image.

FIG. 3 is a block diagram of the lens barrel portion of the defect inspection apparatus showing the second embodiment of the present invention. The optical microscope 25 with a zoom function is installed in the lens barrel of the defect inspection apparatus shown in FIG. When observing the defect detection location, the sample stage 7 is set perpendicularly to the optical axis of the optical microscope 25 with a zoom function. Since the ion beam is generally limited to the information on the surface state of the semiconductor wafer, it becomes possible to obtain information about the influence from the semiconductor wafer pre-manufacturing process by making it possible to confirm the defect detection location with an optical microscope.

[0016]

As described above, according to the present invention, the surface of a semiconductor wafer is scanned with an ion beam, secondary electrons generated from the semiconductor wafer are captured, pattern information is sequentially captured, and defect determination for finding abnormal pattern information is performed. By providing a circuit and a defect information recording circuit for recording this defect and defect position information, the defect on the semiconductor wafer is detected,
Further, there is an effect that it is possible to obtain a semiconductor wafer defect inspection apparatus capable of determining whether the circuit of the semiconductor device is electrically disconnected or short-circuited on the spot by the contrast of the defect image.

[Brief description of drawings]

FIG. 1 is a block diagram showing a wafer defect inspection apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an image example of a defect detected by the wafer defect inspection apparatus of the present invention.

FIG. 3 is a configuration diagram showing a lens barrel portion of a wafer defect inspection apparatus according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Ion Gun 2 Lens 3 Lens 4 Accelerator 5 Scanning Coil 6 Scintillation Counter 7 Sample Stage 8 Inspection Area Control Circuit 9 Signal Amplifier 10 Defect Judgment Circuit 11 Defect Information Recording Circuit 12 CRT 13 Acceleration Power Supply 14 Lens Power Supply 15 Scanning Power Supply 16 Magnification 17 Insulating film base substrate 18 Conductive wiring 19 Pattern defect of conductive foreign matter 20 Pattern defect of insulating foreign matter 21 Disconnection defect 22 Conductive wiring with different contrast 23 Normal contact hole 24 Contact hole with poor opening 25 Optical microscope with zoom function

Claims (1)

[Claims] 1. A stage for mounting a semiconductor wafer,
An ion gun that generates an ion beam, a scanning coil that deflects the ion beam in one direction to scan the semiconductor wafer surface, and an inspection area control circuit that moves the stage in a step shape in a direction perpendicular to the scanning direction, A scintillation counter that captures secondary electrons generated from the semiconductor wafer, a signal amplifier that converts the captured secondary electrons into a pattern signal and sequentially stores the pattern signal, and pattern information that is sequentially output from the signal amplifier. And a defect information storage circuit that stores the defect determined by the defect determination circuit and position information of the defect and a display device that displays the defect. A semiconductor wafer defect inspection apparatus characterized by: