JPH0661265A - Formation of schottky junction gate - Google Patents
Formation of schottky junction gateInfo
- Publication number
- JPH0661265A JPH0661265A JP13645392A JP13645392A JPH0661265A JP H0661265 A JPH0661265 A JP H0661265A JP 13645392 A JP13645392 A JP 13645392A JP 13645392 A JP13645392 A JP 13645392A JP H0661265 A JPH0661265 A JP H0661265A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- schottky gate
- gate electrode
- forming
- low resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はショットキーゲートの形
成方法に係わり、特に電界効果トランジスタのゲートの
形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a Schottky gate, and more particularly to a method of forming a gate of a field effect transistor.
【0002】[0002]
【従来の技術】従来の低抵抗のショットキーゲートの形
成方法として、ガリウムひ素を半導体とした例を図3
(a)〜(c)を用いて説明する。2. Description of the Related Art As a conventional method of forming a low resistance Schottky gate, an example of using gallium arsenide as a semiconductor is shown in FIG.
A description will be given using (a) to (c).
【0003】まず、図3(a)に示すように、動作層2
を有するガリウムヒ素基板1上に絶縁膜3を堆積した
後、フォトレジストをパターニングする。次いでフォト
レジストをマスクとして所望の開口部が得られるように
絶縁膜3を選択的にエッチング除去し、動作層2を露出
させる。First, as shown in FIG. 3A, the operation layer 2
After depositing the insulating film 3 on the gallium arsenide substrate 1 having, the photoresist is patterned. Next, using the photoresist as a mask, the insulating film 3 is selectively etched and removed so as to obtain a desired opening, and the operating layer 2 is exposed.
【0004】次いで図3(b)に示すように、ガリウム
ひ素とショットキー接合を形成する全面にスパッタ法に
より例えばタングステンシリサイド等の耐熱金属4を被
着し、続いて白金等からなるバリアメタル5を被着し、
続いて金等の低抵抗金属6を被着し、さらにTi(チタ
ン)又はTiN(窒化チタン)等のメタル7を被着す
る。そして開口部を被うようにフォトレジスト8Aをパ
ターニングして、それをマスクとして、図3(c)に示
すように、メタル7,低抵抗金属6,バリアメタル5,
耐熱金属4,絶縁膜3をエッチング除去し、ショットキ
ーゲート(電極)を形成し、その後、その表面に保護膜
9を堆積する。Next, as shown in FIG. 3B, a refractory metal 4 such as tungsten silicide is deposited on the entire surface forming the Schottky junction with gallium arsenide by a sputtering method, and then a barrier metal 5 made of platinum or the like. Put on,
Subsequently, a low resistance metal 6 such as gold is deposited, and further a metal 7 such as Ti (titanium) or TiN (titanium nitride) is deposited. Then, the photoresist 8A is patterned so as to cover the opening, and using it as a mask, as shown in FIG. 3C, the metal 7, the low resistance metal 6, the barrier metal 5, and the like.
The heat resistant metal 4 and the insulating film 3 are removed by etching to form a Schottky gate (electrode), and then a protective film 9 is deposited on the surface thereof.
【0005】金等の低抵抗金属6の上にTi又はTiN
等のメタル7を被着することは、保護膜9と低抵抗金属
6との密着性を良くする為に必要である。Ti or TiN is deposited on a low resistance metal 6 such as gold.
It is necessary to adhere the metal 7 such as the above in order to improve the adhesion between the protective film 9 and the low resistance metal 6.
【0006】[0006]
【発明が解決しようとする課題】上述した従来のショッ
トキーゲート電極の形成方法は、特にゲート長が小さい
場合はゲートを低抵抗化するために低抵抗金属を厚くつ
けると、スパッタ法によるカバレッジが悪く、ゲートに
巣(空胴)が出来る為に必ずしも低抵抗化しないという
問題点があった。In the conventional method of forming the Schottky gate electrode described above, when a low resistance metal is thickly formed in order to reduce the resistance of the gate especially when the gate length is small, the coverage by the sputtering method is increased. Poorly, there was a problem that the resistance was not necessarily lowered because a nest (cavity) was formed in the gate.
【0007】[0007]
【課題を解決するための手段】本発明のショットキーゲ
ート電極の形成方法は、ガリウムひ素基板上に動作層と
絶縁膜とを順次形成する工程と、前記絶縁膜をパターニ
ングしショットキーゲート電極形成領域に溝を形成する
工程と、露出した動作層を含む全面に耐熱金属とバリア
メタルとを順次形成する工程と、前記ショットキーゲー
ト電極領域内のバリアメタル上に低抵抗金属をメッキす
る工程と、前記低抵抗金属上にTiを蒸着する工程と、
全面にミリング等のドライエッチングを行い、前記ショ
ットキーゲート電極領域外の耐熱金属とバリアメタルと
の除去及び前記ショットキーゲート電極領域内の前記T
iの表面を削る工程と、前面に保護膜を形成する工程と
を含んで構成させる。A method of forming a Schottky gate electrode according to the present invention comprises a step of sequentially forming an operating layer and an insulating film on a gallium arsenide substrate, and patterning the insulating film to form a Schottky gate electrode. A step of forming a groove in the region, a step of sequentially forming a refractory metal and a barrier metal on the entire surface including the exposed operation layer, and a step of plating a low resistance metal on the barrier metal in the Schottky gate electrode region. Depositing Ti on the low resistance metal,
Dry etching such as milling is performed on the entire surface to remove the refractory metal and the barrier metal outside the Schottky gate electrode region and the T inside the Schottky gate electrode region.
The step of scraping the surface of i and the step of forming a protective film on the front surface are included.
【0008】また、前記形成方法において、低抵抗金属
上にTiを蒸着する工程の後に表面にチッ素イオンを注
入してTiNを形成する工程と、全面にミリング等のド
ライエッチングを行い、前記ショットキーゲート電極領
域外の耐熱金属とバリアメタルとの除去及び前記ショッ
トキーゲート電極領域内の前記TiNの表面を削る工程
と、全面に保護膜を形成する工程とを含むことができ
る。Further, in the above-mentioned forming method, after the step of depositing Ti on the low resistance metal, a step of implanting nitrogen ions into the surface to form TiN, and the entire surface is subjected to dry etching such as milling to obtain the shot. The process may include removing the refractory metal and the barrier metal outside the key gate electrode region, removing the surface of the TiN in the Schottky gate electrode region, and forming a protective film over the entire surface.
【0009】[0009]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0010】図1(a)〜(c)は本発明の第1の実施
例を工程順に示した半導体チップの断面図である。FIGS. 1A to 1C are sectional views of a semiconductor chip showing a first embodiment of the present invention in the order of steps.
【0011】まず図1(a)に示すように、動作層2を
有するガリウムひ素基板1上に所望の開口部を有する絶
縁膜3を形成する。First, as shown in FIG. 1A, an insulating film 3 having a desired opening is formed on a gallium arsenide substrate 1 having an operating layer 2.
【0012】次に図1(b)に示すように、ショットキ
ー接合を形成するタングステンシリサイド等の100n
m(ナノメータ)程度の膜厚の耐熱金属4及び膜厚15
0nm程度の白金等からなるバリアメタル5をスパッタ
法により被着する。そして開口部よりも広い寸法の開口
幅を持つフォトレジスト8を形成する。このフォトレジ
スト8は厚さが2μm以上を有しかつ、開口部がイメー
ジリバース法により逆テーパになっている。耐熱金属4
及びバリアメタル5を給電層として選択的に金めっきに
より低抵抗金属6としての金属を400nm程度膜厚に
形成し、続いてTi膜7Aを500〜600nmの膜厚
に蒸着する。その後、リフトオフ法によりレジスト8及
びレジスト8上のTi7A膜を除去する。Next, as shown in FIG. 1B, 100 n of tungsten silicide or the like forming a Schottky junction is formed.
Heat-resistant metal 4 and film thickness 15 of about m (nanometer)
A barrier metal 5 of about 0 nm made of platinum or the like is deposited by the sputtering method. Then, a photoresist 8 having an opening width wider than the opening is formed. The photoresist 8 has a thickness of 2 μm or more, and the opening is inversely tapered by the image reverse method. Heat-resistant metal 4
Further, a metal as the low resistance metal 6 is formed to a thickness of about 400 nm by selective gold plating using the barrier metal 5 as a power supply layer, and then a Ti film 7A is vapor-deposited to a thickness of 500 to 600 nm. After that, the resist 8 and the Ti7A film on the resist 8 are removed by the lift-off method.
【0013】次に図1(c)に示すように、全面にミリ
ング等のドライエッチングを行い、耐熱金属4とバリア
メタル5からなる給電層の露出部分を除去する。その
際、金めっき上のTi7Aは少くとも膜厚50nmは残
すようにする。その後、保護膜9を堆積する。Next, as shown in FIG. 1C, dry etching such as milling is performed on the entire surface to remove the exposed portion of the power feeding layer made of the refractory metal 4 and the barrier metal 5. At that time, Ti7A on the gold plating is left to have a film thickness of at least 50 nm. Then, the protective film 9 is deposited.
【0014】図2(a),(b)は本発明の第2の実施
例を工程順に示した半導体チップの断面図である。FIGS. 2A and 2B are sectional views of a semiconductor chip showing a second embodiment of the present invention in the order of steps.
【0015】第2の実施例の図2(a)は、第1の実施
例の図1(a),(b)で説明された工程の後に、表面
にチッ素イオンを注入してTiN7Bを形成する。FIG. 2 (a) of the second embodiment shows that after the steps described in FIGS. 1 (a) and 1 (b) of the first embodiment, nitrogen ions are implanted into the surface to form TiN7B. Form.
【0016】そして図2(b)に示すように、全面にミ
リング等のドライエッチングを行い給電層4,5の露出
する部分を除去し、続いて絶縁膜3をウェットエッチン
グ除去する。その際、TiNは絶縁膜3のウェットエッ
チングに耐える厚さ、少なくとも膜厚50nmは残すよ
うにする。その後保護膜9を堆積する。Then, as shown in FIG. 2B, dry etching such as milling is performed on the entire surface to remove the exposed portions of the power feeding layers 4 and 5, and then the insulating film 3 is removed by wet etching. At this time, TiN is left to have a thickness that can withstand the wet etching of the insulating film 3, at least a film thickness of 50 nm. After that, the protective film 9 is deposited.
【0017】この実施例では絶縁膜3が除去されるの
で、ゲート容量が減少し電界効果ランジスタの特性が向
上する。Since the insulating film 3 is removed in this embodiment, the gate capacitance is reduced and the characteristics of the field effect transistor are improved.
【0018】[0018]
【発明の効果】以上説明したように、本発明はショット
キーゲート電極の低抵抗金属6を金めっきとして巣(空
胴)をなくしたのでゲート抵抗の低抵抗化が可能とな
り、かつ金めっき上にTi(チタン)またはTiN(チ
ッ化チタン)を残すことにより、保護膜との密着性を良
くし、かつ自己整合的にゲート形状が決定できるという
効果を有する。As described above, according to the present invention, the low resistance metal 6 of the Schottky gate electrode is plated with gold to eliminate cavities (cavities), so that the gate resistance can be lowered and the gold plating can be performed. By leaving Ti (titanium) or TiN (titanium nitride) in the film, it is possible to improve the adhesion to the protective film and to determine the gate shape in a self-aligned manner.
【図1】本発明の第1の実施例を工程順に示した半導体
チップの断面図。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention in process order.
【図2】本発明の第2の実施例を工程順に示した半導体
チップの断面図。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention in process order.
【図3】従来技術の方法を工程順に示した半導体チップ
の断面図。FIG. 3 is a cross-sectional view of a semiconductor chip showing a method of the related art in the order of steps.
1 ガリウムひ素基板 2 動作層 3 絶縁膜 4 耐熱金属 5 バリアメタル 6 低抵抗金属 7,7A メタル 8,8A フォトレジスト 9 保護膜 1 gallium arsenide substrate 2 operating layer 3 insulating film 4 heat resistant metal 5 barrier metal 6 low resistance metal 7,7A metal 8,8A photoresist 9 protective film
Claims (3)
を順次形成する工程と、前記絶縁膜をパターニングしシ
ョットキーゲート電極形成領域に溝を形成する工程と、
露出した動作層を含む全面に耐熱金属とバリアメタルと
を順次形成する工程と、前記ショットキーゲート電極領
域内のバリアメタル上に低抵抗金属をメッキする工程
と、前記低抵抗金属上に保護膜との密着性のよい密着金
属を形成する工程と、全面をドライエッチングにより、
前記ショットキーゲート電極領域外の耐熱金属とバリア
メタルとの除去及び前記ショットキーゲート電極領域内
の前記密着金属の表面を削る工程と、全面に保護膜を形
成する工程とを含むことを特徴とするショットキーゲー
トの形成方法。1. A step of sequentially forming an operating layer and an insulating film on a gallium arsenide substrate, and a step of patterning the insulating film to form a groove in a Schottky gate electrode formation region.
A step of sequentially forming a refractory metal and a barrier metal on the entire surface including the exposed operation layer, a step of plating a low resistance metal on the barrier metal in the Schottky gate electrode region, and a protective film on the low resistance metal. By the process of forming an adhesion metal having good adhesion with and the whole surface by dry etching,
A step of removing the refractory metal and the barrier metal outside the Schottky gate electrode area, a step of shaving the surface of the adhesion metal in the Schottky gate electrode area, and a step of forming a protective film on the entire surface. Method of forming Schottky gate.
タンでありこれを蒸着により形成したことを特徴とする
請求項1に記載のショットキーゲートの形成方法。2. The method of forming a Schottky gate according to claim 1, wherein the adhesion metal having good adhesion to the protective film is titanium, which is formed by vapor deposition.
後に、表面にチッ素イオンを注入して窒化チタンを形成
する工程と、全面をミリング等のドライエッチングを用
い、前記ショットキーゲート電極領域内の前記窒化チタ
ンの表面を削る工程と、全面に保護膜を形成する工程と
を含むことを特徴とする請求項2に記載のショットキー
ゲートの形成方法。3. The Schottky gate electrode is formed by using a step of implanting titanium ions on the surface to form titanium nitride after the step of depositing titanium on the low resistance metal, and a dry etching such as milling on the entire surface. 3. The method of forming a Schottky gate according to claim 2, including a step of removing the surface of the titanium nitride in the region and a step of forming a protective film on the entire surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13645392A JPH0661265A (en) | 1992-05-28 | 1992-05-28 | Formation of schottky junction gate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13645392A JPH0661265A (en) | 1992-05-28 | 1992-05-28 | Formation of schottky junction gate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0661265A true JPH0661265A (en) | 1994-03-04 |
Family
ID=15175472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13645392A Withdrawn JPH0661265A (en) | 1992-05-28 | 1992-05-28 | Formation of schottky junction gate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0661265A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3604073A1 (en) * | 1986-02-08 | 1987-08-13 | Koenig & Bauer Ag | Device for clamping printing formes in a groove of a forme cylinder of a sheet-fed rotary printing machine |
-
1992
- 1992-05-28 JP JP13645392A patent/JPH0661265A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3604073A1 (en) * | 1986-02-08 | 1987-08-13 | Koenig & Bauer Ag | Device for clamping printing formes in a groove of a forme cylinder of a sheet-fed rotary printing machine |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990803 |