JPH0659978A - Information processor - Google Patents

Abstract

PURPOSE:To prevent a pipeline from being emptied until an instruction is loaded from an instruction cached into a main storage device. CONSTITUTION:The leading address of an exceptional processing routine is stored in a result register 116, and in a succeeding cycle, the leading address is transferred to an instruction pointer 102 to start an instruction cache 104. A finite status logic 111 goes to the succeeding step independently of the existence of the address of the pointer 102 in the cache 104. Even when a cache miss is generated, the data transfer of the cache 104 to/from the main storage device can be overlapped to the succeeding step of the logic 111, so that a required instruction can be prevented from being queued due to the generation of a miss in the cache 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to control of an instruction cache memory in a processor having a cache memory in which instructions and data are separated.

[0002]

2. Description of the Prior Art In order to continuously supply instructions to a pipelined processor, an instruction-only cache memory is employed. The instruction-only cache memory is simply referred to as an instruction cache here. The instruction cache can eliminate a collision between fetching of an instruction and data (operand), which occurs when the instructions are overlapped and executed in a pipeline manner.

[0003]

However, the instruction cache has a small capacity due to its high speed, and unless the instructions of the entire program operating on the processor are stored in the instruction cache, the instructions cannot be fetched at the necessary timing (that is, , Cache miss) can occur. At this time, the pipeline becomes empty until the desired instruction is loaded from the main memory to the instruction cache, resulting in a decrease in performance.

[0004]

The information processing apparatus according to the present invention comprises: a. Aside from the instruction fetch operation, fetching data at a predetermined address or an address designated by a specific instruction from the main storage device; b. Even if the instruction cache is requesting data to the main memory device, it will accept the subsequent request unless the requested address of the subsequent request is the same as the address being requested to the main memory device. In addition, the purpose of the present invention is to load the instruction from the main memory device to the instruction cache by overlapping with the operation in the other processor so as to minimize the empty space of the pipeline generated in the conventional device.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. One of the embodiments of the present invention is a case where the instruction execution unit in the pipeline is realized by a sequential circuit, and when the sequential circuit operates for a long cycle and the instruction fetch operation stops, It guarantees that the instruction fetched later will be in the instruction cache. The other is to issue an instruction that guarantees that the instruction at the specified address exists in the instruction cache, prior to the actual instruction fetch (which is likely to be a branch instruction). . This instruction can be inserted into the program by the compiler if the number of cycles required to fetch the instruction from the main memory is known.

First, the positioning of both instruction and data caches in the information processing apparatus will be briefly described with reference to FIG. The information processing apparatus is the central processing unit 1 (PRO
C) and the main memory 2 (MM). Besides, there is an input / output means for communicating with an external storage means and an interface with a human, but it is omitted because it is not essential for instruction execution.

Now, the basic operation of the central processing unit 1 is to take out one instruction in the main storage device 2 and to perform the operation instructed therein by the data (operand) in the main storage device 2 or the central processing unit 1. This is done with respect to the internal state, and the state in the main storage device 2 is changed or reflected in the internal state of the central processing unit 1. At most 3 in this operation
There are two memory operations. That is, a. Instruction fetch,
b. Operand fetch, c. It is the writing of the result.
In the cache memory, these operations are executed by the instruction execution unit (I
P) A high-speed memory, which has a small capacity but the same cycle time as that of the instruction execution unit 3, has a decrease in performance due to a main memory having a cycle time which is several to several tens of times slower than that of the P. It is meant to avoid by placing.

There is an instruction cache (IC) 4 for the memory operation a and a data cache (DC) 5 for the memory operations b and c.

FIG. 1 is a block diagram showing a central processing unit according to the first embodiment of the present invention. First, the overall movement will be described.

The instruction is fetched from the instruction cache (I-CACHE) 104 at the address indicated by the instruction pointer (IP) 102. The instruction pointer 102 is normally updated by the +1 adder (+1) 103 to indicate the next instruction when the fetching of a certain instruction is completed. When a branch instruction is executed, the execution result of the operation unit, which will be extended later, is supplied by the signal line 151, so that it is selected and stored in the instruction pointer 102.

If the instruction of the address designated by the instruction pointer 102 is not found in the instruction cache 104, the address is stored in the instruction memory address register and the instruction memory address register 106, and the main memory (not shown here). No.) requesting the data of the necessary address through the signal line 168. At that time, the update of the instruction pointer 102 is suspended.

After several cycles, the desired data is sent from the main memory through the signal line 167, so that the instruction cache 104 registers it in itself and stores it in the instruction register (IR) 105 and holds it. The update of the instruction pointer 102 that has been performed is reunited.

The instruction stored in the instruction register 105 is decoded by an instruction decoder (DECODE) 107 so as to be easily controlled by hardware, and stored in a decoded instruction register (DIR) 108.

The decoded information, that is, a part of the information stored in the decoded instruction register 108, is used to select an operand. That is, the address of the arithmetic register, the address of the data in the memory, and the like.

Based on these pieces of information, two operands are finally selected, and the operand register (OR1) 11
2 and (OR2) 113. The data cache 110 is used to retrieve the memory data. Since the operation when the requested data is not found in the data cache 110 is almost the same as that of the instruction cache 104, the description thereof is omitted (the interface with the main storage device is also omitted). When the operation register is designated as an operand, the data in the register file (REGS) 109 is taken out.

The rest of the decoded information becomes the initial state of the finite state logic (FSM) 111 which controls the operation of the instruction. Finite state logic 111 receives the initial state from decoded instruction register 108 via signal line 157,
A new state is generated by a predetermined logic to generate a next state, and the next state is stored in the state register (STATE) 114. The output of the state register 114 includes information for determining the next state of the finite state logic 111 itself, as well as designation of the operation of the arithmetic logic unit (ALL) 115, a fetch instruction of the next operand, and the like. Signal line 16 in FIG.
5 corresponds to the former, and the signal line 166 corresponds to the latter.

The finite state logic 111 may be realized by a sequential circuit composed of a logic circuit or may be realized by a microprogram system.

The data stored in the operand register 112 and the operand register 113 is subjected to the operation designated by the status register 114 in the arithmetic logic unit 11.
5, and the operation result is stored in the result register (RDR) 116. Then, in the next cycle, the data in the result register 116 is stored in the register file 109 or the data cache 110 according to the designation of the status register 114 at that time. With the storage of this result, the operation of the finite state logic 111 ends and execution of the next instruction begins.

Next, one example in which the effect of the present invention is exhibited in the first embodiment will be described.

An exceptional event occurs in the middle of a certain process,
It is often implemented by software in order to give the corresponding processing flexibility. However, since the processing is exceptional, the instruction does not exist in the instruction cache when the instruction is needed, and a considerable delay often occurs when the (cache miss) software processing is started.

At this time, from the occurrence of the exceptional event to the jump to the final software routine, the above-mentioned finite state logic 111 operates, and steps such as investigating the cause, saving the state and initial setting are taken. . This is illustrated in FIG. Steps 302, 303, 304 of these finite state logic 111 require 10 to 30 cycles, and no instruction is fetched during this period.

In order to guarantee that the exception handling routine exists in the instruction cache at the required time, if the address is requested from the instruction cache at the beginning of the operation step of the finite state logic 111, the subsequent finite State logic 11
Since the step 1 and the fetching into the instruction cache overlap, an instruction becomes a necessary stage and is not made to wait due to an instruction cache miss. FIG. 5 shows the flow of this improved finite state logic. 3 in the figure
08, 310, and 311 are 302 and 30 of FIG. 4, respectively.
This is a step corresponding to 3,304, and 309 is a step of instructing the instruction cache to fetch the above-mentioned instruction. The operation at this time will be described with reference to FIG. 1. In step 309, the start address of the exception handling routine is stored in the result register 116, and the instruction pointer 1 is set in the next cycle.
It is moved to 02 and the instruction cache 104 is activated.

Whether the address of the instruction pointer 102 is in the instruction cache 104 or not, the finite state logic 11
1 proceeds to the next step. As a result, even if a cache miss occurs in the instruction cache 104, the above-described interaction with the main memory of the instruction cache 104 and the subsequent step of the finite state logic 111 can be overlapped.

If the cache miss operation in the instruction cache 104 is completed before the instruction fetch of the exception handling routine is started, the exception handling routine can be started without delay.

Next, FIG. 2 is a block diagram showing the central processing unit of the second embodiment. In FIG. 2, this central processing unit executes one instruction in a 4-stage pipeline, and unlike FIG. 1, there is no finite state logic in the execution unit, and execution of the instruction is necessarily completed in one cycle. It is like this. Therefore, the pipeline stops at the instruction cache (I-
Only when a cache miss occurs in CACHE) 205. Each stage of the pipeline is
tch), arithmetic (A), memory (Memory) M, and write (Write) W. Operations are always performed between registers and written back to the registers again.

The operations on the memory are only loading to the register and storing the data in the register to the memory, and no operation is performed at that time.

Now, explaining the general operation of this central processing unit, an instruction is always pointed to by an instruction pointer (IP) 201, and the instruction pointer 201 is incremented by +1 by a +1 adder (+1) 202 every cycle except for branch instructions. It The instruction cache 205 may be the same as 104 in FIG. However, as will be described later, the instruction pointer 20 of the request address
Not only 1 but also the address register (PA
R) 203. The fetched instruction is stored in the A stage instruction register (AIR) 207. This output is supplied to the instruction decoder (DECODE) 209 and used to generate the control signal of the A stage. For example, the signal line 261 specifies the source operand register addresses (two), the general register file (GRS) 210 is read, and the arithmetic logic unit (ALU) 2 is read by the signal lines 265 and 266, respectively.
11 is supplied. At the same time, signal line 264 specifies the operation performed by arithmetic logic unit 211. The output 251 of the arithmetic logic unit 211 is stored in the address register (MAR) 213 of the M stage. here,
If the instruction is a branch instruction, arithmetic logic unit 2
The output of 11 is stored in the instruction pointer 201. Also,
If the instruction is a store instruction, the general-purpose register file 210
Of the data is stored in the data register 214 of the M stage through the signal line 266.

On the other hand, the instruction register 212 of the M stage stores the instruction in the instruction register 212 of the M stage in accordance with the control signal of the M stage.

In the M stage, the data cache (D-
CACHE) 215 is an M-stage address register 2
13 for the address and M stage instruction register 21
Memory operation by a part of 2 (signal connection 268), and in the case of a store instruction, M stage data register 214
The data is instructed by.

The operation of the data cache is the same as 110 of FIG. 1 and is omitted here.

If the instruction is not related to memory operation, the contents of the address register 213 of the M stage is stored in the data register (WDR) 217 of the W stage through the bypass of the signal line 269. Otherwise, the content of the output 271 of the data cache 215 is fetched into the data register 217 of the W stage.

W stage instruction register The W stage instruction register 216 is a destination address (signal line 260) for writing back the result (the contents of the W stage data register 217) to the general register file 210.
Execution of one instruction is completed by writing the result including.

Next, consider a case where a branch instruction causes a cache miss with a branch instruction in FIG. The timing in that case is shown in FIG.

In the branch instruction, the address of the branch destination is stored in the instruction pointer 201, and the subsequent instruction becomes ineffective. Then, the instruction of the new address is supplied to the pipeline. At this time, the branch destination address is often a memory area different from the address before the branch, and a cache miss often occurs when the instruction of the branch destination (target) is fetched. In that case, as shown in FIG. 6, a delay due to a cache miss appears.

Next, the case of this embodiment will be described.
First, a branch destination preload (TPL) instruction is newly provided. T
The PL instruction has the same format as the branch instruction and calculates the same branch destination address. The calculation result is the instruction pointer 201.
Not special address register for preload (PAR)
It is stored in 203 and accesses the instruction cache 205. At this time, the TPL instruction is terminated regardless of whether the instruction of the address designated by the preload address is in the instruction cache 205 or not. When the instruction cache 205 is accessed by the preload address register 203, the update (+1) of the instruction pointer 201 is suppressed. That is, there is only one empty space in the pipeline
Only cycles.

If a cache miss occurs when the instruction cache 205 is accessed by the preload address register 203, the address stored in the preload address register 203 is the multiplexer 20.
Instruction memory address register (IMAR) via 4
It is stored in 206. Then, a request is made to the main storage device (not shown) through the signal line 258. It takes several cycles (10 cycles in this case) until the data is returned from the main memory, but as described above, the TPL instruction ends regardless of cache hit / miss and the subsequent instruction is executed, so this time Disappears. If a subsequent instruction requests the same address as the instruction memory address register 206 or causes a cache miss, the instruction fetch operation is suspended until the request to the current main memory is completed.

FIG. 7 shows the effect of the TPL instruction of this embodiment. In the sequence of FIG. 6, the number of cycles per instruction is about 2.1, whereas that of the sequence of FIG. 7 is 1.3.

[0038]

As described above, the present invention guarantees the existence of the necessary instruction in the instruction cache by overlapping with the arithmetic operation, thereby delaying the cache miss at the time when the instruction is needed. Prevents empty pipelines and improves performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a position of a cache memory in the information processing device.

FIG. 4 is a diagram illustrating an F.V. for explaining the first embodiment. S. M. It is a figure which shows the operation | movement flow of.

FIG. 5 is a diagram illustrating the F.V. of the first embodiment. S. M. FIG. 6 shows an improved flow of FIG.

FIG. 6 is a diagram showing an instruction execution state (branch destination cache miss with a branch instruction) for explaining a second embodiment.

FIG. 7 is a diagram showing an instruction execution situation (effect of a branch destination preload instruction) after application of the second embodiment.

[Explanation of symbols]

 1 Central Processing Unit (PROC) 2 Main Memory (MM) 3 Instruction Execution Unit (IP) 4 Instruction Cache Memory (IC) 5 Data Cache Memory (DC) 102 Instruction Pointer 103 +1 Adder (+1) 104 Instruction Cache (I -CACHE) 105 instruction register (1R) 106 instruction memory address register (IMAR) 107 instruction decoder (DECODE) 108 decoded instruction register (DIR) 109 register file 110 data cache (D-CACHE) 111 finite state logic (FS) .. M.) 112 Operand register (OR1) 113 Operand register (OR2) 114 Status register (STATE) 115 Arithmetic logic unit (ALU) 116 Result register (RDR) 201 Instruction pointer (IP) 20 +1 adder (+1) 203 Preload address register (PAR) 204 Multiplexer (MUX) 205 Instruction cache (I-CACHE) 206 Instruction memory address register (IMAR) 207 A stage instruction register (AIR) 208 Comparator 209 Instruction decoder 210 General Purpose Register File (GRS) 211 Arithmetic Logic Unit (ALU) 212 M Stage Instruction Register (MIR) 213 M Stage Address Register (MAR) 214 M Stage Data Register (MDR) 215 Data Cache (D-CACHE) 216 W stage instruction register (WIR) 217 W stage data register

Claims (2)

[Claims] 1. A relatively low-speed, large-capacity main memory device, and a relatively high-speed, small-capacity device which is used by appropriately replacing the contents of the main memory device in order to access the contents of the main memory device at high speed. The cache memory serving as a storage means has two separate cache memories, an instruction cache for storing an instruction and a data cache for storing operand data specified in the instruction, and the instruction cache fetches an instruction. An information processing apparatus, characterized in that data of a predetermined address is extracted from the main storage device separately from the address. 2. The instruction cache has an instruction for fetching data at a predetermined address from the main memory, and the instruction cache decodes the instruction to cause the instruction cache to Performing the fetch, and allowing the instruction cache to accept a subsequent request even while requesting data to the main storage device only if the address is the same as the address currently requested to the main storage device. The information processing apparatus according to claim 1, which is characterized in that.