JPH0659026B2 - AND circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a logical AND circuit having a plurality of inputs and a rectifying circuit for rectifying the output thereof, like a logical product circuit used in a railway signal processing device. Regarding improvement of a logical product circuit.

Conventional technology Output signals from multiple-input AND operation oscillators
Various AND circuits that rectify the voltage doubled and use the rectified output as the circuit output have been proposed (Japanese Patent Publication No. 45-2905).
No. 4, No. 57-4764. However, in the conventional AND circuit of this kind, since the AND operation oscillator is an oscillator configured to oscillate only when each input signal is at a predetermined level, when all the input signals are not at the predetermined level, The direct current output of the logical product operation oscillator is at L level (or H level), but the DC output of the logical product operation oscillator changes from L level to H level (or its level) when one of the input signals reaches a predetermined level. Vice versa)
On the contrary, since the input signal that has reached the predetermined level no longer reaches the predetermined level, the DC output of the AND operation oscillator changes from the H level to the L level (or from the L level to the H level).
The DC output level of the logical product operation oscillator changes with the change of the input signal level such as the change to the level), and this change causes spike noise in the output of the rectifier circuit, which may be followed. The drawback is that it adversely affects the circuit.

An object of the present invention is to provide an AND circuit which suppresses the generation of spike noise when the output level of an AND operation oscillator changes.

To achieve the above object, in the present invention, a logical product circuit is provided with a logical product operation oscillator and a clamp for outputting the output signal of the logical product operation oscillator by clamping it to one side of the power supply potential or the ground potential. Circuit (20) and the clamp circuit (2
0) output, and the potential on the side different from the potential (clamp potential) used by the clamp circuit (20) for clamping is used as a power source for the sum of the output level of the clamp circuit (20) and the power source potential. A switch circuit that generates an output signal with amplitude and an output signal of the switch circuit that is clamped to a potential (clamping potential) different from the potential used for clamping in the clamp circuit (20) to generate an output signal It is composed of the rectifier circuit.

EXAMPLES The present invention will be described below based on examples shown in the drawings.

FIG. 1 is a circuit diagram showing a 2-input AND circuit which is an embodiment of the present invention. This circuit has a configuration in which a clamp circuit is inserted between a known AND operation oscillator and a rectifier circuit.

That is, in the figure, (1) is a logical product operation oscillator that has upper and lower threshold values and does not oscillate due to a failure of a circuit element, (
2) is a clamp circuit that clamps the output signal of the AND operation oscillator (1) to a predetermined potential, and (3) is a rectifier circuit that rectifies and smoothes the output signal of the clamp circuit (2).

In this AND circuit, the terminal (T3) is used as the positive terminal, the terminal (T4) is used as the negative terminal, and the voltage (E) of the power supply for the AND operation oscillator (1) is applied between both terminals (T3, T4). Apply and input the input signal to the terminals (T1, T2) of the logical product operation oscillator (1) and output the signal obtained between the output terminals (T5, T6) of the rectifier circuit (3) to the circuit output of the logical product circuit. Used as.

Hereinafter, each part will be described.

The logical product operation oscillator (1) is a known circuit, and in the example of FIG. 1, it is an oscillator that operates as a window comparator as a whole, and has an individual window characteristic for the input signal to the terminals (T1, T2). Is.

The terminals (T1, T2) are individually connected to each other to determine the window characteristics, and two circuits (10, 11) and both circuits (10, 11) are connected in cascade to provide oscillation. And a phase inversion circuit (12).

The circuit (10, 11) is a transistor delay circuit, but in the following description, the circuit (10, 11) is referred to as a window comparator circuit for convenience.

It should be noted that the present invention can also be applied to the case of using another known AND logical operation oscillator.

Each window comparator circuit (10, 11) has three transistors (Q1, Q2, Q) connected in series in the illustrated example.
3) (Q5, Q6, Q7) and 8 resistors (R1, R2, R3, R4,
R5, R6, R7, R8) (R11, R12, R13, R14, R15,
R16, R17, R18). The transistors (Q2) and (Q3) and (Q6) and (Q7) are complementary transistors. Further, the transistors (Q2) and (Q6) function as an amplifier whose power source is E.

Transistor (Q of window comparator circuit (10)
The output of the transistor (Q7) of the window comparator (11) is the collector resistance (R16, R17) at the base of 1).
The voltage is divided by the resistor (R18) and input through the resistor (R18), and the output of the transistor (Q1) is added to the base of the transistor (Q2) by the resistor (R2, R3) to shift the level of the power input to the terminal (T3). The voltage of the transistor (Q3) is divided and input. The output of the transistor (Q2) is divided by the resistors (R4, R5) and input to the base of the transistor (Q3). The output of the transistor (Q3) is input to the collector resistor (R6). , R7) and is supplied to the phase inverting circuit (12) via the resistor (R8). In this window comparator circuit (10), the power input to the terminal (T3) is E, and the terminal (T1) is
), And the resistance values of the resistors (R1, R2, R3, R6, R7) are R1, R2, R3, R6, R7 respectively, A terminal (T1) for oscillating the AND oscillator of FIG. 1 in which (hereinafter, referred to as one formula) is composed of (10), (11) and (12)
It becomes the condition in.

Transistor (Q of window comparator circuit (11)
The output of the phase inversion circuit (12) is input to the base of 5),
The base of the transistor (Q6) has a transistor (Q5
) Output is divided by the resistors (R12, R13) including the level shift of the power input to the terminal (T3) and input.
The base of the transistor (Q7) has a transistor (Q6
The output of) is divided by resistors (R14, R15) and input. This window comparator circuit (11)
When the power input to the terminal (T3) is E, the input signal to the terminal (T2) is I2, and the resistance values of the resistors (R11, R12, R13, R16, R17) are R11, R12, R13, R16, R17, respectively. , A terminal (T2) for oscillating the AND oscillator of FIG. 1 in which (hereinafter, referred to as equation 2) is composed of (10), (11), and (12).
It becomes the condition in. The output of the window comparator circuit (11) can be, for example, the collector output of the transistor (Q6).

The phase inverting circuit (12) is composed of a transistor (Q4) and two resistors (R9, R10). The base of the transistor (Q4) is a window comparator circuit (1
0) output terminal, the collector is connected to the terminal (T1) via the collector resistor (R9) and the window comparator circuit (1) via the resistor (R10).
It is connected to the base of the transistor (Q5) of 1), and the emitter is connected to the terminal (T3).

In this AND operation oscillator (1), when the input signal (I1) to the terminal (T1) exceeds the upper limit threshold value, the transistor (Q4) remains on, and the lower limit threshold value is set. If not, the transistor (Q2) remains on. Further, when the input signal (I2) to the terminal (T2) exceeds the upper limit threshold value, the transistor (Q1) remains on, and when it does not reach the lower limit threshold value, the transistor (Q6). Remains on.

However, when the input signal (I2) to the terminal (T2) satisfies the oscillation condition of the above formula 2, and the input signal (I1) to the terminal (T1) satisfies the oscillation condition of the above formula 1, In the logical product operation oscillator (1), each transistor oscillates by operating as follows. That is, Q 2 · off → Q 3 · off → Q 4 · on → Q 5 · off → Q
6 ・ OFF → Q 7 ・ OFF → Q 1 ・ ON → Q 2 ON → Q 3 ・
It oscillates by operating as ON → Q4 ・ OFF → Q5 ・ ON → Q6 ・ ON → ……. Further, in a state where the input signal (I1) to the terminal (T1) satisfies the oscillation condition of the above formula 1,
When the input signal (I2) to the terminal (T2) satisfies the oscillating condition of the above equation 2, each of the transistors in the logical AND operation oscillator (1) has the following characteristics: Q 6 · off → Q 7 · off → Q 1 · on → Q 2 on → Q
3 ・ ON → Q 4 ・ OFF → Q 5 ・ ON → Q 6 ・ ON → Q 7
・ Once → Q 1 ・ Off → Q 2 ・ Off.

Even if any of the circuit elements (R1 to R17) and (Q1 to Q7) forming the logical product operation oscillator (1) is short-circuited or broken, the logical product operation oscillator (1) does not oscillate.

The configuration and operation of the known AND operation oscillator (1) have been described above.

By the way, the output of the logical product operation oscillator (1) having the above-described configuration oscillates only when the input signals to the terminals (T1, T2) both satisfy the oscillation condition, so that the ground and the predetermined level (e) It becomes the signal shown in FIG. However, for example, a state in which an input voltage satisfying the oscillation condition of the above formula 1 is not applied to the terminal (T1) (hence,
Even if the AND logic operation oscillator (1) does not oscillate),
When a signal that satisfies the above formula 2 is input to 2), the transistor (Q6) is turned off, so that the power supply potential (E) changes to the ground level, and conversely the terminal (T2) is turned off when the transistor (Q6) is off. When there is no input signal to the transistor (Q6), the transistor (Q6) is turned on, so that the ground level changes to the power supply potential (E). That is, when the input potential of the terminal (T2) changes, the collector potential of the transistor (Q6) changes like a direct current as shown in FIG.

Next, the clamp circuit (2) which has not been used in the conventional circuit will be described.

This clamp circuit (2) is connected to the output of the logical product operation oscillator (1) and is a circuit for suppressing generation of spike noise generated in the final output of the logical product circuit due to the potential change as described above. A first circuit (20) for clamping the output of the logical product operation oscillator (1) to the zero potential of the terminal (T4), that is, the ground potential, and a second circuit (21) for clamping the output of the terminal (T3) to the potential. ing.

The first circuit (20) includes a coupling capacitor (22) to which the output of the AND operation oscillator (1) is input, an emitter connected to the output side of the capacitor (22), and a base via a resistor (23). An NPN type transistor (24) connected to the terminal (T4) and a diode (25) for connecting between the base and the emitter of the transistor (24) and clamping it negatively are provided.

The second circuit (21) includes a coupling capacitor (26) to which the output of the logical product operation oscillator (1) is input, a resistor (27) provided on the output side, a capacitor (26) and a resistor (27). The diode (28) is connected to the terminal (T3) for positive clamping. The collector of the transistor (24) and the output side of the resistor (27) are connected to the wired OR and connected to the signal input terminal of the rectifier circuit (3) at the next stage.

Here, the transistor (24) does not conduct between the collector and emitter when the clamp circuit (2) has no input signal, as will be described later. Therefore, when there is no input signal, the power supply potential (E) and the base potential (zero). Resistance between (R23) and (R27)
Since the potential divided by and, that is, R27 << R23, approximately the power source potential (E) is applied to the next stage rectifier circuit (3).
Has been inserted to give to.

In addition, the time constant at the time of discharging the capacitor (22) of the first circuit (20) in the clamp circuit (2) (mainly determined by the leakage between the diode (25) and the base of the transistor (25), and the 2 circuit (21) capacitors (2
6) The time constant during discharge (mainly determined by the leakage between the diode (28) and the collector-base of the transistor (23)) is large compared to the oscillation frequency of the AND logic operation oscillator (1). ing.

Next, the known rectifier circuit (3) following the above clamp circuit (2) becomes an output only when the oscillation output of the AND logical operation oscillator (1) is input, and the oscillation output is input. It is a fail-safe n-fold voltage rectifying and smoothing circuit that produces no output when not in use or when the circuit fails.
The terminal (T3) side is connected so as to output zero potential.

In the embodiment, the rectifier circuit (3) is a voltage doubler rectifier circuit, as shown in the figure, a coupling capacitor (30), two diodes (31, 32) provided on the output side, and a four-terminal capacitor. It is composed of (33) and.

Next, the operations of the clamp circuit (2) and the rectifier circuit (3) in the AND circuit of the embodiment having the above-mentioned configuration will be described.

First, the AND operation oscillator (1) is oscillating, and the input signal to the clamp circuit (2) (the signal at point (a) of the clamp circuit (2)) becomes the signal shown in FIG. 2 (a). The case will be described.

As already mentioned, the capacitor (22) of the first circuit (20)
Is selected so that the time constant during discharge is larger than the oscillation frequency of the AND operation oscillator (1), the input signal to the clamp circuit (2) (the signal at point (a)) is the second circuit. Since it is clamped by the diode (28) of (21), the signal of point (b) is clamped to the power supply voltage (E) every time the input signal to the clamp circuit (2) reaches a predetermined level (e). The signal shown in FIG. 2B changes such that it changes positively in the operated state (becomes higher than the power supply potential E by the input signal level (e)). On the other hand, the signal at the point (c) changes to negative every time it changes by the level (e) while being clamped to the ground potential (0) (it becomes lower than the ground potential by the input signal level (e)). , The signal shown in FIG. Then, since the negative signal voltage is applied between the base and the emitter of the transistor (24), the transistor (24) is switched by this negative signal. That is, the electric charge of the capacitor (26) flows as a current through the resistor (27) from the collector of the transistor (24) to the emitter of the transistor (24). Here, the transistor (24) operates as a switch circuit that is switched by the input signal of the first circuit (20), that is, the signal clamped to the negative. Since the signals in FIGS. 2B and 2C have mutually inverted phases, the signal at the connection point (D) between the first circuit (20) and the second circuit (21) becomes the second circuit ( As a result of the output of 21) being attenuated by the resistor (27), the output signal at the connection point (d) of the output of the clamp circuit of the second circuit (21) is Δe.
Then, between the ground and (E + e + △ e) (however, Δe
It becomes the signal shown in Fig. 2 (d) that changes with << e).

Where E is the power supply voltage, e is the signal of the clamp circuit (2) generated at the connection point (d) by the first circuit (20), and Δe
Is a signal component generated at the connection point (d) by the second circuit (21).

This signal is clamped at the level (E) as a signal at the point (e) on the output side of the capacitor (30) of the rectifier circuit (3), and changes to (E + e) as shown in Fig. 2 (e). Therefore, at the terminals (T5, T6), an output obtained by rectifying the oscillation output of the AND operation oscillator (1) is generated.

Next, in this AND circuit, the terminal (T1) or (T
The DC output level of the AND logic operation oscillator (1) changes from the ground level (0) to a predetermined level (e) as shown in FIG.
Then, the case where the power supply potential (E) is changed to the ground level (0) will be described.

The repetition cycle of the change in the DC output level corresponds to the capacitor (2) in the first and second circuits of the clamp circuit (2).
2, 26) is longer than the discharge time constant, the signal at the point (b, c) in the clamp circuit (2) in FIG. 1 becomes the signal (b, c) shown in FIG.

That is, when the input signal of the clamp circuit (2) changes positively, the positive change is short-circuited by the diode (25) in the first circuit (20) and is not output, but the second circuit (2)
In 1), the positive change amount of the input signal is superposed on the electric potential E in which the capacitor (26) is charged by the diode (28) before the positive change of the input signal occurs and is output. If the input signal remains positively changed, the positive change transmitted by the capacitor (26) will eventually disappear and become positive spike noise.

Next (after a while), when the input signal of the clamp circuit (2) falls and returns to its original value (which means that the input signal changed to negative), the diode (28) causes this negative change in the second circuit (21). Minutes are short-circuited and not output, but the first circuit (2
In (0), the falling component of this input signal is superimposed and output on the potential (ground potential) at which the capacitor (22) was charged by the diode (25) before the input signal fell and a negative change occurred. . Then, if the input signal remains returned to its original state, the negative change component transmitted by the capacitor (22) will eventually disappear and become negative spike noise. Here, the potential at the connection point (d) is approximately E when the input signal changes positively and when this change returns to its original value.

Then, the signal at the point (d) becomes a small signal as shown in Fig. 3 (d) in which the signal on the side higher than the power supply potential (E) is significantly attenuated by the resistor (27), and the rectifier circuit (3)
If the rectification time constant (determined by the rectification load and the capacitor (30)) is sufficiently smaller than the rising time constant of Fig. 3 (d) (the frequency of the AND operation oscillator is sufficiently high),
The signal at the point (e) becomes the signal shown in FIG. 3 (e), which hardly appears. That is, the signal at the point (e) is the output signal of the AND logic operation oscillator (1) from the first circuit (2).
Since the voltage is clamped to the potential of the terminal (T4) by (0) and the power source potential is clamped by the rectifier circuit (3), the signal on the positive side is removed to obtain the signal shown in FIG. This is because when the output of the AND logic operation oscillator (1) is directly input to the rectifier circuit (3) and positively rectified, the DC rising input signal as shown in FIG. To appear, it is equivalent to inserting a negative clamp circuit, that is, the first circuit (20) between the AND logic operation oscillator (1) and the rectifier circuit (3) so as to eliminate the positively changing signal by the clamp. To do.

The second circuit (21) of the clamp circuit (2) is a rectifier circuit (
It has a function to increase the input signal to 3) by E. If the second circuit (21) is not provided, the input signal to the rectifier circuit (3) is the output of the first circuit (20) being only e (Fig. 2 (c) or Fig. 3 (c)). Then, the level when there is no signal in FIGS. 2 and 3 (d) (the level of E in FIG. 2 or 3 when there is no change in the input signal) becomes zero, and the input signal If there is no level E, it does not occur (however, Δe does not occur).

And, without the second circuit (21), the first circuit as shown by the dotted line
If the input signal changes positively if the clamp circuit composed of the capacitor (22) and diode (25) of the circuit (20) and the rectifier circuit (3) are directly connected, it is indicated by the dotted line (called the dotted line part). ) Becomes zero potential, and when it changes to a negative potential (when it returns to the original), the potential of the dotted line portion becomes a negative potential. This signal is output as an output signal of the rectifier circuit (3) by being superimposed on the power supply potential E. At this time, the positive change in the dotted line (the rising component, which is the same as the rising component of the waveform in Fig. 3 (a)), is superimposed on the power supply potential E and output. That is, this positive spike noise does not disappear.

If the transistor (24) is added by adding the second circuit (21) (first
(The voltage applied to the collector of the transistor (24) via the clamp circuit (28) and the resistor (27) of the two circuits is the power supply potential of the transistor as an amplifier.)
Input signal of clamp circuit (2), ie diode (25)
The transistor (24) will be switched by the terminal voltage of. The change in the collector potential of the transistor (24) accompanying this switch is as shown in Fig. 3 (d), and the negative change in spike noise is not generated as the output signal of the rectifier circuit (3), and the positive change is small. Therefore, the output signal of the rectifier circuit (3) is also small. Here, the second circuit is not always necessary.
The collector output of the transistor (24) may be connected to the terminal T5 via the resistor (27). That is, the input signal of the clamp circuit (2) is generated as a switch signal of the transistor (24), and the output signal (collector output signal) accompanying this switch is approximately the amplitude of the sum of the input signal e and the power supply potential E. When the input signal is the input signal of FIG. 3 (a), the positive change (rising) signal has already been generated after the transistor (24) has been switched off (the collector potential is the power supply potential E).
Therefore, it does not occur as an input signal of positive change of the rectifier circuit (3). On the other hand, when the cycle of the input signal of the clamp circuit (2) is short as shown in Fig. 2, the signal accompanying ON / OFF of the transistor (24) changes with an amplitude of approximately e + e and is input to the rectifier circuit (3). Will be.

Therefore, the amplitude ratio of spike noise in the rectifier circuit (3) to a normal input signal (output signal of the logical operation oscillator), that is, the noise-to-noise ratio is Δe to E + e.

Next, another embodiment shown in FIG. 4 will be described.

In the AND circuit of FIG. 4, the rectifier circuit (3) is connected to the terminal (T4) on the ground side of the power source for negative rectification. This AND circuit is shown in FIG. 1 except that the first circuit (20) is connected to the positive terminal (T3) of the power source (E) and the second circuit (21) is connected to the ground terminal (T4). It has the same configuration as the AND circuit of. Therefore, even in this AND circuit,
When the DC output level of the AND operation oscillator (1) changes, the signal increases by the amount of the power supply (E) and at the same time the negative spike noise is significantly attenuated by the resistor (27), and the negative noise is AND operation. The output signal of the oscillator (1) is removed by being clamped to the potential of the terminal (T3) by the first circuit (20), and the output of the rectifier circuit (3) is not affected by noise.

Although the above-described embodiment has a positive input signal to the terminals (T1, T2), the present invention can be applied to the case where the input signal to the terminals (T1, T2) is negative. In this case, for example, a negative power source is used as the power source (E) and the terminal (T
3) is the negative side, the PNP type transistor is an NPN type transistor, the NPN type transistor is a PNP type transistor, and the clamp circuit (2) and the rectifier circuit (3) of FIG. 1 or 4 are used. Should be connected.

EFFECTS OF THE INVENTION As described above, according to the present invention, a clamp circuit that clamps an output signal of an AND operation oscillator to one side of a power supply potential or a ground potential and outputs the clamp signal, and a clamp circuit that is switched by the output of the clamp circuit. Since a switch circuit is provided in which an output signal is generated with an amplitude of the sum of the output level of the clamp circuit (and the power supply potential) using a potential on the side different from the potential used by the circuit for clamping (clamp potential) as a power source, The spike noise generated in the output of the rectifier circuit due to the change in the output level of the operational oscillator is small and does not affect the subsequent circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a first embodiment of a logical product circuit according to the present invention, and FIG. 2 is an explanatory diagram of electric signals at respective points when a logical product operation oscillator is oscillating. FIG. 3 is an explanatory diagram of electric signals at respective points when the DC output level of the logical product operation oscillator changes, and FIG. 4 is a diagram showing another embodiment of the logical product circuit according to the present invention. (1): AND operation oscillator, (2): Clamp circuit, (3): Rectifier circuit.

Claims (1)

[Claims] 1. A logical product circuit in which an output signal of an AND logical operation oscillator is clamped to a power supply potential side or a ground potential side to generate a rectified output signal. A clamp circuit (20) that clamps and outputs to one side, and a clamp circuit (20) that is switched by the output of the clamp circuit (20) and has a side different from the potential (clamp potential) used for clamping by the clamp circuit (20). A switch circuit that uses an electric potential as a power source to generate an output signal with the amplitude of the sum of the output level of the clamp circuit (20) and the power supply potential, and uses the output signal of the switch circuit for clamping in the clamp circuit (20). And a rectifying circuit that generates an output signal by clamping the potential to a different potential (clamping potential).