JPH0656844B2 - Oxide etch treatment method and etchant used therefor - Google Patents

Description

The present invention relates to an etching method used for manufacturing integrated circuits, and more particularly to a selective etching method for silicon oxide in the manufacturing process of integrated circuits. is there. [Prior Art] In the manufacture of integrated circuits, it is very often necessary to preferentially etch silicon oxide with respect to silicon. For example, phosphorus silicate glass (PS
G) or boron-phosphorus silicate glass (BPSG) or the like, in a case where a contact opening reaching a layer made of silicon (for example, moat or polycincon layer) is formed in an interlayer dielectric layer, this silicon layer is used. It is necessary to selectively perform the etching process. Until now, fluorine-deficient plasma was used to preferentially etch the oxide of silicon. In this case, the atomic ratio of fluorine to carbon in the fluorine-deficient plasma was typically about 2 to 1, and a small amount (for example, 5 mol% or less) of oxygen was usually used. If this amount of oxygen is too large, the oxygen component will remove carbon as carbon monoxide and the etching will proceed into the fluorine-rich region, resulting in the etching of both silicon and silicon oxide. Becomes. Thus, as previously proposed, C with O ₂ added
Using compound material HF _3, etc., CHF ₃ than the flow rate of _{O 2}
It means that the method such as increasing the flow rate of is made much higher. However, the present invention does not take such a conventional coping method at all. The reason is that firstly, nitrogen trifluoride is used as the main fluorine source (and preferably does not contain any carbon-containing component), and secondly, oxygen in the atomic composition of the gas mixture for etching is used. In the case of a practical example in which the content of is larger than that of fluorine and is preferable, this is because the flow rate of oxygen is set to about 10 times the flow rate of nitrogen trifluoride. The use of nitrogen trifluoride has been tried in various plasma etching methods for several years, but a mixed gas mainly composed of oxygen with a small amount of nitrogen trifluoride gives priority to oxide over silicon. There is no prior art that suggests that it physically etches. In addition, the various conventional methods for preferentially etching oxides on silicon have their own problems regarding residues. That is, since the polymer residue is deposited on the exposed area, by carefully adjusting the accurate mass flow rate, the chemical substance used in the process, and the conditions thereof, it is possible to obtain a good residue without depositing the residue. The problem is that these conditions must be set within the narrow range required to obtain selectivity. The oxide etching treatment method according to the present invention does not leave the above-mentioned residue, and in this respect has a great advantage over the conventional method. These advantages are especially exhibited in the etching of contacts, and when residue is deposited on the bottom of the contact opening,
Not only the contact resistance deteriorates, but also the variation in parameters increases and the quality of process control deteriorates. The above advantages are further advantageous when using the direct moat isolation method. In this method, instead of growing the field oxide in a pattern, the field oxide is grown (or deposited) over the entire surface and then patterned and etched. This field oxide is removed by an oxide etching process to remove the moat. The contact with the exposed surface does not cause defects in the gate oxide layer due to the deposition of residues. [Object of the Invention] Therefore, an object of the present invention is to provide an etchant that preferentially etches silicon oxide with respect to silicon. A second object of the present invention is to provide an etchant that preferentially etches silicon oxide with respect to silicon and does not cause residue deposition. A third object of the present invention is to provide an etchant that preferentially etches silicon oxide with respect to metal silicide. A fourth object of the present invention is to provide an etchant that preferentially etches silicon oxide with respect to silicide and does not cause residue deposition. There is a surprising advantage in using nitrogen trifluoride in combination with oxygen, and contrary to what has been said in the past,
It dramatically improves the selectivity of oxides to silicon. As a conventional theory of this kind, for example, V.
M. Donelli, D. L. Fulham, W. C. Dot Lemon
Smith and D.C. J. By Warder (Journal of Applied Physics, 55, 242, 1984). By the way, when the mixed gas of nitrogen trifluoride and oxygen is used, for example, when phosphorus silicate glass is preferentially etched with respect to single crystal silicon, the selectivity is 12 to 1, and P-type polycrystalline silicon is used. On the other hand, the selectivity when preferentially etching phosphorus silicate glass is
It becomes 13 to 1. The selectivity of plasma oxide for silicon is 2.2 to 1. Thus, the oxygenated trifluoride nitrogen chemistry of the present teachings is inherently less prone to residue deposition, and in this respect, has substantial advantages. The remarkable feature of the etch gas as described above is its high reactivity with organic materials such as photoresist. This is often a disadvantage and most applications require the use of a hardmask process. As described above, the present invention shows that the oxide to be etched is phosphorus silicate glass (hereinafter referred to as PSG) or boron phosphorus silicate glass (hereinafter referred to as BPSG).
Is more effective, and in addition to the above nitrogen trifluoride, an equal amount of CF ₄ , C ₂ F ₆ , and B is used.
F ₃ , SiF ₄ , SF ₄ or a mixture thereof may be used. [Means for Solving the Problems] Thus, in performing the etching treatment of the silicon oxide of the integrated circuit laminated body, the present invention has a completed integrated circuit laminated body having a dielectric containing silicon oxide on the surface. A body is prepared, the dielectric is partially covered by a patterned hard mask, oxygen and NF ₃ , CF ₄ , C ₂ F ₆ , BF ₃ , SiF ₄ , SF ₆
And contacting the integrated circuit laminate with plasma in a gas containing both a perfluorinated compound and oxygen selected from these mixtures, and the additive gas to this plasma has a higher oxygen content than the perfluorinated compound. An etch treatment method characterized by the above is provided. [Embodiment] Next, an embodiment of the present invention will be described with reference to a cantilever etch mask method. In this cantilevered etch mask method, an oxide etch according to the present invention is used to first undercut the organic spacer layer under a patterned polysilicon hard mask and then etch the PSG layer below the organic spacer layer. Perform processing.
However, it goes without saying that the present invention can be applied to various processes other than the integrated circuit manufacturing process. Embodiments of the present invention will be described below with reference to the drawings.
The process described below is intended to excavate contact openings in a 1 micron thick PSG layer on a 1000 Å thick plasma-enhanced CVD oxide film. In the figure, reference numeral 10 indicates this synthetic multilayer oxide laminate (multilevel oxide). In an embodiment of the present invention, an A
After spin coating Z 1400-31 resist, 180
The spacer layer 12 is formed by baking at ℃. Then, a plasma-enhanced CVD silicon hard mask layer 14 having a thickness of about 5000 Å is deposited on the upper surface of the spacer layer 12, and then a photoresist layer as a minimum layer is deposited, exposed, developed and post-baked.
(Note that in this case, it is preferable to avoid performing hot plate pre-baking before the photolithography process so that the spacer layer resist does not "foam" below the plasma-enhanced CVD silicon layer.) Since the barrel resist layer has good flatness obtained by the spacer layer 12 and the silicon hard mask layer 14, it may be an extremely thin layer. For example, when a photoresist such as AZ 1400-17 is used, Its thickness can be 6000 angstroms. An anisotropic silicon etch is then used to excavate the silicon hard mask layer 14 according to the mask defined by the top photoresist layer. The etching used in this case may be an ordinary etching method using an etching agent such as Freon 12. Then, the etching process, which is the main feature of the present invention, is started. In this example, first of all, for this purpose, a plurality of slices are packed in the reactive ion etching reactor.
As the reactor used here, for example, AME 8110
The reactor is used to provide 1000 watts of power at 13.56 MHz. The mixed gas in the furnace has a flow rate of oxygen gas of 1
Flow at 00 sccm and nitrogen trifluoride at a flow rate of 10 sccm so that the total gas pressure is 100 microns (ie, 100 milliTorr). The etch temperature is preferably cooled to a temperature slightly lower than the ambient temperature, for example 15 ° C. However, this cooling is not always necessary,
This helps to minimize the total amount of outgassing from the resist. In the case of the reactor AME 8110, the power density is
This is equivalent to about 150 milliwatts per square centimeter. Another method for calculating the power density when changing the processing conditions between reactors of different types is to calculate the power per single volume, such as the AME 8110 above.
In the case of, the volume is about 150 liters, so the power per unit volume in the plasma atmosphere is about 6.5 watts per liter. As will be understood later, this method is rather a low pressure etching method, and the anode region and the cathode region of the reactor are not equal, and thus the reactor is so-called RIE (reactive ion etching mode). It is a reactor of a method generally known as a method. The etching method according to the present invention is a timed etching method, that is, when the above-mentioned arrangement is used, the processing time is set to 75 minutes for processing 24 slices. Do. In this case, the small area of silicon exposed by the etching process is extremely smaller than the whole area, and the silicon hard mask is exposed to plasma in any case. It is impossible. Further, in this etching treatment method, the etching treatment is carried out so that the etching of the contact opening portion of the laminated body 10 is preferably 30%. However, although this method is merely a timed etching method and not an end point detection type etching method, it has been found that setting the time has relatively little effect. In a further test conducted on the present invention, the contact openings were simultaneously etched in the moat (ie, the silicon substrate) and the upper polysilicon layer to expose the upper polysilicon contact area with a resist layer approximately 1 micron thinner than the moat area. Coated. The etching process was performed in a timed manner to optimize the moat region, and the polysilicon contact region was overetched significantly. However, no difference was found in the contact area. In the case of this embodiment, the gas pressure of the entire gas used is 100 μm, but this gas pressure can be changed significantly, for example, at least 30 μm to 50 μm.
You can change this over the 0 micron range, or in some cases over a wider range. In any case, this total gas pressure is usually selected so as to satisfy the requirements concerning the anisotropy of the process itself using the method according to the present invention. In this respect, the present invention is advantageous in obtaining anisotropic properties suitable for various types of processes. If the amount of nitrogen trifluoride used is excessive, the silicon hard mask 14 will be etched, or at least pits will be formed. On the contrary, if nitrogen trifluoride is not used at all, it is impossible to perform an appropriate MLO (multilayer oxide) etch, and pure oxygen plasma cannot promptly excavate the oxide. ． Thus, the flow rate range of nitrogen trifluoride in the mixed gas for etching is preferably 2 sccm or more, but it is necessary to set it to a value lower than the flow rate of oxygen used. It appears that nitrogen trifluoride not only serves as a fluorine source for anisotropic oxide etching, but also has a role in removing residues. For example, in the example of the cantilevered etch mask method described above, the spacer layer of the organic material serves as a carbon source, and if the amount of nitrogen trifluoride used is set to zero, residue deposition occurs. Just a few sc of nitrogen trifluoride
Such deposition does not occur even if the flow rate is cm.
Therefore, although nitrogen trifluoride is used as the only fluorine-containing component in this example, various other perfluorinated compounds as listed above or a mixture of these compounds may be used if desired. However, when it is used as a mixture, it is necessary that the atomic weight of oxygen in the entire mixture is larger than that of fluorine, preferably at least 4 times. On the other hand, the flow rate of oxygen is preferably 100 sccm, but may be in the range of 10 to 1000 sccm if desired. However, the flow rate of oxygen is 30 to 20
It is desirable to set it to 0 sccm. Furthermore, regarding the area density of electric power, it is preferable to set this to 0.15 watts per square centimeter, but it may be in the range of 0.015 watts to 1.5 watts or other as long as the supply of cooling electric power is sufficient. As described above, when a mixed gas of nitrogen trifluoride and oxygen is used, for example, when the phosphorus silicate glass is preferentially etched with respect to the single crystal silicon, the selectivity 12
The selectivity is 13: 1 when the phosphorus silicate glass is preferentially etched with respect to P-type silicon. Furthermore, the selectivity of PSG for unimplanted polysilicon is about 11: 1 and the selectivity of PSG for plasma oxide is 5.6: 1. As described above, the present invention is particularly advantageous for selectively etching PSG and BPSG with respect to various silicon-containing materials (crystalline silicon, polysilicon, metal silicide, etc.). Further, as mentioned above, a significant feature of the etch gas used in the present invention is its high reactivity with organic materials such as photoresist, which is often a disadvantage and in most applications. It is required to adopt the hard mask process. However, this feature is very convenient for etching an oxide with a graded concentration profile using the cantilever lithography method. In particular, the polysilicon hard mask is process compatible with various processes, and it is most preferable to use the polysilicon hard mask in carrying out the present invention. This polysilicon hard mask is preferably combined with a planarization layer on the underside of the hard mask as in the previous embodiments. The composition of the spacer layer 12 can be selected from various planarizing polymer substances, but poly (methylmethacrylate = PMMA) is completely unsuitable for this type of layer, and is of novolac type. Photoresists are much more suitable. Generally speaking, as a photoresist, a photoresist containing a stable aromatic compound which is not present in PMMA, which is present in an AZ-based resist, is considered to be more suitable. Thus, the present invention provides a new type of etchant that preferentially etches silicon oxide with respect to silicon or silicide. Although the embodiments of the present invention have been described above, the method and the etchant according to the present invention are not limited to these embodiments, and it is to be understood that various additions or changes may be appropriately made to the described embodiments. Not too long.

[Brief description of drawings]

The figure is a diagram showing a laminate in which a contact opening is being formed by a cantilevered etch mask method using the method of the present invention. 10 …… Synthetic multilayer oxide laminate, 12 …… Spacer layer, 14 …… Silicon hard mask layer,

Claims (16)

[Claims] 1. An incomplete integrated circuit stack having a dielectric containing silicon oxide on its surface is prepared, the dielectric is partially covered by a patterned hard mask, oxygen and NF ₃ , CF ₄ , C ₂ F ₆ , BF ₃ , SiF ₄ , SF ₆
And contacting said integrated circuit stack with a plasma in a gas containing both a composition selected from these and
At this time, the additive gas to the plasma has a higher content of oxygen than that of the composition. 2. The oxide etching method according to claim 1, wherein the plasma is generated in a gas having a total gas pressure of 30 to 500 microns. 3. The plasma contains the oxygen in an amount of 4% of the composition.
The oxide etching method according to claim 1, wherein the oxide etching method comprises double or more times. 4. The oxide etching method according to claim 1, wherein the plasma is generated by applying electric power at an areal density in the range of 1 to 0.05 watts per square centimeter. 5. The plasma is generated in the reaction chamber of a reactor by supplying power to the gas at a volume density of 1 to 10 watts per liter near the incomplete integrated circuit stack. The oxide etching method according to claim 1, wherein the method is the same. 6. The oxide etching method according to claim 1, wherein the hard mask is substantially made of polysilicon. 7. The oxide etching method according to claim 1, wherein the dielectric material is substantially composed of phosphorus silicate glass. 8. The oxide etching method according to claim 1, wherein the hard mask layer is made of silicon. 9. The oxide etching method according to claim 1, wherein the dielectric is made of boron-phosphorus silicate glass. 10. When making contacts in an integrated circuit,
By preparing an incomplete integrated circuit stack having a dielectric containing silicon oxide on its surface, depositing a hard mask layer made of silicon on the dielectric, and etching the hard mask layer in a predetermined pattern. , Openings are formed at a plurality of predetermined contact positions of the hard mask layer, and oxygen and NF ₃ , CF ₄ , C ₂ F ₆ , BF ₃ , SiF ₄ , SF are formed.
Or contacting said integrated circuit stack with plasma in a gas containing both a composition selected from these mixtures,
At that time, the additive gas to the plasma has a higher oxygen content than that of the composition, and a patterned conductor is deposited to connect the contact openings to each other to form a predetermined circuit configuration. The method of making a contact on an integrated circuit characterized in that 11. An etchant for selectively etching silicon oxide with respect to silicon, comprising: (a) oxygen and NF ₃ , CF ₄ , C ₂ F ₆ , BF ₃ , SiF ₄ , and S.
A plasma in a gas consisting of F ₆ or a composition selected from a mixture thereof, and (b) the atomic weight of oxygen in the gas is greater than the atomic weight of fluorine in the composition. Etchant to be. 12. The etchant according to claim 11, wherein the atomic weight of oxygen in the gas is at least four times greater than the atomic weight of the fluorine composition in the gas. 13. The flow rate of oxygen is 10 to 1000 s.
Etchant according to claim 11 within the range of ccm. 14. The flow rate of oxygen is 10 to 1000 s.
The etchant according to claim 12, within the range of ccm. 15. The flow rate of oxygen is 30 to 200 sc
Etchant according to claim 11 within the range of cm. 16. The flow rate of oxygen is 30 to 200 sc
The etchant according to claim 12, within the range of cm.