JPH0654921B2 - Digital radio demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a modulation / demodulation system and a circuit system for data transmission using a wireless device, and a digital circuit for improving C / N to perform highly reliable transmission. The present invention relates to a demodulator of a wireless device.

[Conventional technology]

FIG. 5 is a block diagram showing a code transmission system by a conventional analog radio, in which 1 is a code converter, 2 is a modulator, 3 is a VHF radio transmitter, 4 is a transmitting antenna, and 5 is a transmitting antenna.
Is a receiving antenna, 6 is a VHF radio receiver, 7 is a demodulator,
Reference numeral 8 is a decoding converter.

The conventional analog radio device is configured as described above, the code converter 1 outputs the serial code SD, and the modulator 2 outputs, for example, FSK (frequency shift keying) modulation or PSK.
(Phase shift keying) modulation is performed to modulate a voice band signal, and then VHF radio transmitter 3 performs dual modulation with FM modulation and is transmitted from the transmitting antenna 4 to the air as a radio wave. On the other hand, the above radio wave received by the receiving antenna 5 is demodulated into a voice band signal by the VHF radio receiver 6, converted into a serial code RD by the demodulator 7, and then by the decoding converter 8. Code data is received.

FIG. 6 is a C / N-S / N characteristic diagram of a conventional wireless device. If the wireless signal-to-noise ratio C / N is good, S / N improvement can be expected at the FM demodulation level, and S / N will be better than C / N. However, if C / N deteriorates, a certain threshold level will be achieved. In the following, the S / N deteriorates and the decoding error of the demodulator output increases. This characteristic is shown in FIG. The bit error rate Pe of the decoded output is determined for the S / N, and the Pe
Therefore, it is necessary to secure a certain level of S / N and C / N.

[Problems to be solved by the invention]

In the conventional method as described above, when the C / N level is low, the bit error rate of the demodulator output becomes very poor and the C / N
There was a problem that it was not practical at 5 dB or less (Pe ≈ 10 ^-1 at C / N 5 dB).

The present invention has been made to solve such a problem, and uses a digital demodulator and a simple demodulator,
It is an object of the present invention to obtain a demodulator of a digital radio device that can reliably transmit data even when C / N is bad.

[Means for solving problems]

The demodulator of the digital radio according to the present invention, when performing transmission at a speed lower than the transmission capacity (modulation / demodulation transmission speed) of the digital radio, adds modulation by PN coding in the process of decreasing the transmission speed. , At the time of demodulation, the synchronization signal is secured under a constant condition, and the synchronization signal that has been secured can be self-synchronized if a constant condition cannot be obtained.
For signal demodulation, PN code demodulation must be done with a shift register and NO.
A simple circuit including an R circuit, an analog adder, a comparator, and the like is provided with a circuit for realizing a correct / wrong majority decision.

[Action]

According to the present invention, it is possible to extend the practical range of decoding of a digital radio device to a case where the S / N ratio is very small by making a correct / wrong majority decision. In consideration of noise, the demodulation of a digital radio device or the like has a sufficiently low composite error Pe when the S / N is large. On the other hand, S /
If N is small and the noise is white noise, Pe is
It approaches 0.5 (that is, the number of correct and incorrect decoding bits is equal).

〔Example〕

FIG. 1 is a block diagram showing a code transmission system by a digital radio according to an embodiment of the present invention. 1A is a code converter, 2A is a PN code modulator, 3A is a digital radio transmitter, and 6A is a digital radio. The receiver, 7A is a PN code demodulator, and 8A is a decoding converter.

In the digital wireless device configured as described above, the transmission code SD and the synchronization timing ST are transmitted from the code converter 1A.
Is output, and the PN code modulator 2A converts and modulates one bit length of the transmission code SD into a PN code length (2 ⁿ -1: n is an integer) and outputs SD '. Further, the modulation start timing is synchronized with the above-mentioned synchronization timing ST, and the transmission timing ST 'corresponding to each bit of the PN code modulation output is created and output. Then, the digital radio transmitter 3A directly modulates the above SD 'in accordance with ST', and transmits it as a radio wave from the transmitting antenna 4 to the air.

On the other hand, the above radio wave is received by the reception antenna 5, the reception PN code RD 'and the reception timing RT' are output from the digital radio receiver 6A, the demodulation output RD and the synchronization timing RT are created by the PN code demodulator 7A, Further, the decoding converter 8A reconstructs the received data. Third
The figure shows a timing chart showing the operation of the PN code modulator 2A.

Now, consider a 15-bit PN code as an example of the PN code. An example of the above-mentioned PN code demodulator 7A is shown in FIG. 2 and will be described in the case of a length of 15 bits. In addition, the above P
A timing chart showing the operation of the N code demodulator 7A is shown in FIG.

The received PN code RD 'and the reception timing RT' from digital radio receiver 6A inputted to the first shift register 7-1, S ₁₁₅ ~ triggers 'the RT' above RD at
The shift registers of S ₁₀₁ are sequentially shifted. Therefore, the respective data X _{1 to} X ₁₅ are arranged in S _{101 to} S _{115 in the} order of the input code, and this and the fixed values a _{1 to} a _{15 of the} PN code are XO.
Comparing each X ₁ and a _1, X ₂ and a ₂ ...... X ₁₅ and a ₁₅ in exclusive OR XOR circuit at R ₁ ~XOR _15. This exclusive OR XOR circuit outputs "1" if the signs match and "0" if the signs do not match, so the exclusive OR XO
X _1, X ₂ by R circuit, ... X ₁₅ and a _1, a _2, ... match with a _15, it is possible to obtain a number of mismatches. That is, the correlation function value can be obtained by the exclusive OR XOR circuit. The voltage adder 7-2 is configured by connecting to one point through the resistors R _{1 to} R ₁₅ interposed between the outputs of the exclusive OR XOR circuit. Assuming that the maximum voltage value that can be taken by the voltage adder 7-2 is A and the minimum value is B, the demodulation output by the majority comparator 7-3 that has the value of (A + B) / 2 as the decision level. RD is obtained. (However, in this case, it is necessary to sample in positive synchronization.) On the other hand, the maximum value A is output to the output of the voltage adder 7-2.
Output of all "1" comparator 7-4 for determining
A logical sum OR circuit 7-6, which receives the outputs of the all "0" comparator 7-5 and the output of the logical sum OR circuit, is provided.
When either of the outputs is present in the circuit 7-6, "1" is output, the output is input to the second shift register 7-7, and serially transmitted to the respective S _{215 to} S ₂₀₁ at the reception timing RT 'described above. A judgment output of the synchronization timing RT is obtained by the logical product AND circuit 7-8 which receives the shifted output of S ₂₀₁ as an input. That is, the above is the fixed P of the received PN code one cycle (15 bits) before the PN code length.
This is a circuit for obtaining the synchronization timing RT confirmed by double matching of the perfect match with the N code or the inverted code of the fixed PN code and the perfect match this time.

In order to confirm the operation on these circuits, as shown in Tables 1 to 6, when a 4 bit error out of 15 bits is randomly mixed in the received PN code string, when a 7 bit error is randomly mixed, The case of adding a random stream (15 bits) is divided into the cases of codes “1” to “0” and the cases of “1” to “1”, and each is 1000
The trial results of one time were created.

In each table, 1 to 16 at the top show the reception timing and 1
Indicates the synchronization timing of the code in the first half, 16 indicates the synchronization timing with an error in the latter half, and 2 to 15 indicate the reception timing during that period. Also, the leftmost -15 to 15
Indicates the correlation function value. Numerical values in each table indicate the number of occurrences of each correlation value in 1000 trials at each reception timing.

The conclusion from this simulation result is that the incidence of false synchronization for random errors in the PN code is very low (ie 15 or − at reception timing 2-15).
If the occurrence rate is set to Ps, the occurrence rate of Ps ² is obtained by collating twice, and it is understood that erroneous synchronization is unlikely to occur.

On the other hand, if the synchronization timing is correct, the demodulation output is the reception P
If the number of erroneous bits of the N code is less than 1/2 of the PN code length, correct demodulation can be performed. This means that the bit error rate Pe of the C / N-Pe characteristic (however, S / N in the figure can be read as C / N) shown in FIG. 7 of the digital radio is 10 ^-1 to 4 × 10 ^-1. Also, the demodulation output means that the error rate is low, and C / N
This shows that even 0 dB is sufficiently practical. The C / N-Pe characteristics of the wireless device differ depending on the modulation method, and the PSK modulation method is better than the FSK modulation method.

In the above-described embodiment, an example of high-reliability data transmission by a general digital radio has been described, but it is particularly effective for data transmission with fading in a mobile body. It can also be used for signal transmission in a premises or at home using a noisy line, for example, a low voltage line.

〔The invention's effect〕

As described above, the present invention is configured so that a simple PN code demodulation circuit using a digital radio can be used to make a correct / wrong majority decision. Therefore, high reliability is ensured even when transmission is performed in a place where C / N is not good. There is an effect that transmission can be performed.
Further, the above effect can be further promoted by combining an error correction code such as a burst correction code after PN code modulation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a code transmission system by a digital radio which is an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a PN code demodulator in the present invention, and FIG. 3 is a PN in the present invention. FIG. 4 is a timing chart showing the operation of the code modulator, FIG. 4 is a timing chart showing the operation of the PN code demodulator in the present invention, FIG. 5 is a block diagram showing a code transmission system by a conventional radio, and FIG. FIG. 7 is a S / N-Pe characteristic diagram in the conventional radio device, and FIG. 7 is a S / N-Pe characteristic diagram in the conventional radio device. In the figure, 6A is a digital radio receiver and 7A is a PN.
Code demodulator, 7-1 is first shift register, 7-2 is voltage adder, 7-3 is majority comparator, 7-4 is all "1" comparator, 7-5 is all "0" comparison , 7-6 is a logical sum circuit, 7-7 is a second shift register, 7-8 is a logical product circuit, 8A is a decoding converter, and XOR1 to XOR15.
Is an exclusive OR circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References IEEE Vehicular Tec hnology Centerence 1979.14. Probability of error of the spreadspectrum um mobile communications receiver in a non-Rayleigh fading environment.

Claims (3)

[Claims] 1. A demodulator of a digital radio device, which receives and demodulates a transmission wave modulated into a PN code sequence and its inverted code sequence according to the states of "1" and "0" of a serial code, A digital radio receiver that receives the transmission wave and outputs a PN code sequence and a reception timing, and a PN that creates a demodulation signal and a synchronization timing based on the PN code sequence and the reception timing from the digital radio receiver. A code demodulator and a decoding converter for reconstructing received data based on the demodulated signal from the PN code demodulator and synchronization timing, wherein the PN code demodulator is the PN code string and its inverted code. A demodulated signal of a column and a reception timing are input, and the first and second shift registers having a PN code length for trigger-sampling and serially shifting the demodulated signal according to the reception timing. An exclusive OR circuit for performing an exclusive OR of a star, an output of the first shift register, and the PN code string signal corresponding to a preset position corresponding to each shift position; A voltage adder that connects each output of the summing circuit to one point via the same resistor to perform voltage addition, and an output value when all outputs of the voltage adder are "1" and all "0" A demodulator for a digital wireless device, comprising: a majority comparator whose determination level is 1/2 of the output value in the case. 2. An all "1" comparator that outputs "1" only when the outputs of the voltage adder are all "1" and an all "0" that outputs "1" only when all of the outputs are "0". And a second shift register having a PN code length for obtaining a logical sum with the output of the comparator by a logical sum circuit, inputting the logical sum output, and triggering the serial shift by the reception timing; The logical product of the output of the final stage of the second shift register and the logical sum output is taken by the logical product circuit, and the two-fold comparison with the one cycle delay of the change point of the data is obtained to obtain the correct PN code demodulator. A demodulator for a digital radio device as set forth in claim (1), characterized in that a synchronization timing is obtained. 3. When the decoding converter receives the output of the PN code demodulator and the output of the AND circuit and obtains the synchronization timing, the same synchronization timing as on the transmitting side is obtained. When the determination is made and the output of the majority comparator of the demodulator is sampled at the timing and output as a serial code, and when the synchronization timing cannot be obtained, a time having the same length as the transmission timing from the previously obtained timing A demodulator for a digital radio device as set forth in claim (1), characterized in that the demodulator output is automatically sampled and output after a lapse of time, and is sequentially read.