JPH0654036A - Remote supervisory controller - Google Patents

Abstract

PURPOSE:To facilitate the measurement of performance by a test equipment by producing a preset error. CONSTITUTION:The controller is provided with a transmission data inversion changeover control circuit 10 consisting of a transmission data buffer 11 fetching one byte of a transmission data signal outputted serially from a communication LSI 62 synchronously with a clock signal, a flag setting device 13 to which a flag pattern is set, a comparator 12 comparing the flag pattern and the one byte data in the transmission data buffer, a programmable counter 16 starting count of bits of the transmission data based on an ON condition of a transmission enable signal from a MODEM when the data comparison indicates coincidence, a setting device 19 setting bits to be inverted in advance among transmission data after the transmission start flag pattern, a comparator 20 comparing the setting condition and the bit count in the programmable counter 16, and a transmission data inversion changeover section 17 inverting transmission data when the coincidence by the comparator 20 is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a high-level data link control procedure (hereinafter referred to as an HDLC transmission procedure) to control a monitored control device between a control station (master station) and a controlled station (slave station). The present invention relates to a distant supervisory control device capable of experimentally causing an error in transmission and transmission data in a method of transmitting information necessary for supervisory control.

[0002]

2. Description of the Related Art Conventionally, there has been no suitable method for forcibly generating a predetermined pattern error in transmission and transmission data in a remote monitoring and control apparatus using an HDLC transmission procedure. This is because the HDLC transmission procedure itself is supported by a general-purpose communication LSI, and real-time transmission procedures are required, such as generation of a flag sequence, zero insertion, abort of transmission frame, and time fill on the transmission side. Signal transmission, frame check sequence (CRD code)
Generation, flag sequence detection on the receiving side, zero remove, frame aboard signal detection, frame check sequence error check, secondary station address, global address detection, etc., most of which are executed on the LSI hardware. It Also, some LSIs support all the exchange of commands and responses in the HDLC procedure.

FIG. 6 is a diagram showing the relationship between a general transmission control unit and a modem. The transmission controller is composed of a sub-microprocessor 61 and a communication LSI 62, and is connected to the internal bus of the sub-microprocessor 61. The sub-microprocessor 61 sends information via the communication LSI 62,
Reception is exchanged, and processing of the address field, control field, and information field in the HDLC format is performed according to the protocol. Communication LSI
Reference numeral 62 supports a part of the HDLC transmission procedure that requires the real-time property. Further, the modem 63 is a modulator / demodulator for putting a transmission signal and a reception signal on an actual transmission line, and there are two types such as a synchronous type and an asynchronous type. In the case of a synchronous modem, a clock for data transmission / reception is generally required for the leader line. In FIG. 6, the ST signal is a transmission clock signal and the RT signal is a reception clock signal (however, the ST signal may be generated by the modem itself).

Among the modem control signals, ST and RT are as described above, but the RS signal is a signal for requesting the start of transmission to the modem 63, and when turned on, the modem 63 is turned on.
A carrier for transmission is output to the outside. The CS signal is a signal from the modem 63 to notify the transmission control unit that transmission is possible, and the transmission control unit recognizes that the carrier from the modem 63 by the RS signal is stable by receiving the ON response. As a result, the transmission control unit can start the transmission of the SD signal which is the transmission data. CD
The signal indicates that the carrier from the partner transmission control unit is detected, and the RD signal, which is the reception data, can be received in the ON state. All the modem control signals described above are CCITT V.V. Recommended in 24.

[0005]

In the above conventional apparatus, when the transmission format is generated by software, an error such as a frame check sequence can be easily generated on the protocol, but the HDLC transmission procedure is used. Since it is performed on the hardware of the LSI, it is practically impossible to make a change for the occurrence of a predetermined error. This has been a problem in evaluating whether or not the error check on the receiving side is surely performed during the device test. The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a distant monitoring control device that can generate a preset error and can easily perform performance measurement in a device test.

[0006]

In order to achieve the above object, the present invention performs a transmission protocol process according to an HDLC transmission procedure to control a modem between a control station (master station) and a controlled station (slave station). In a distant monitoring control device of a system in which information required for monitoring and control is transmitted while controlling signals, a transmission data signal serially output from a communication LSI for the transmission procedure is tuned to a transmission data clock signal. A transmission data buffer that captures 1 byte of data, a flag setter that sets a flag pattern defined in advance in the HDLC transmission procedure, and compares the flag pattern with 1 byte of data captured in the transmission data buffer. From the modem for turning on the transmission request signal to the modem among the modem control signals when the comparison result matches. A programmable counter that starts a bit count of transmission data together with an ON condition of a signal that can be received, a setter that sets any single or multiple bits of transmission data after a transmission start flag pattern, which is inverted in advance, A transmission data inversion switching control including a comparator for comparing a setting condition with the bit count value output from the programmable counter, and a transmission data inversion switching unit for inverting the corresponding transmission data value when a match between the comparators is detected. Equipped with a circuit.

The sub-microprocessor 61 first turns on the transmission request (RS) signal of the modem 63. When receiving the stable transmission enable signal (CS) of the carrier sent from the modem, the sub microprocessor 61 starts sending the SD signal.
Flag pattern (011 defined in HDLC transmission procedure
11110) is set, and the 1-byte data input to the transmission data buffer 11 is compared with the comparator.
Compared at 12. As a result, when a match with the flag pattern is detected, the Q output from the flip-flop 14 is input to the gate (G) of the programmable counter 16. After that, the programmable counter 16 starts counting when there is a count input signal. Further, the Q output from the flip-flop 14 is AND-determined by the AND gate 15 with the transmission data clock frequency. As a result, the transmission data clock signal is input to the programmable counter 16 which starts counting the number of transmission data bits after the start flag of the transmission data. As described above, the programmable counter 16 counts the number of bits of transmission data after the transmission data start flag. On the other hand, the setting device 23
Then, an arbitrary single or plural bits of the transmission data to be inverted are set in advance. The number of bits thus set is compared with the output value from the programmable counter 16 by the comparator 20, and when a match is detected, it is input to the transmission data inversion switching section 17 which inverts the corresponding transmission data. When the comparator 24 detects a match between the number of output bits from the programmable counter 16 and the number of bits from x to y, it outputs to the transmission data inversion switching section 17 during the match detection section. The transmission data inversion switching unit 17 has a point x
When data is recognized, the transmission data (SD) from the communication LSI 62
The inversion of the transmission data is started by switching to the signal route, and the inversion is continued until the point y while the match detection continues. When the output of coincidence detection disappears from the comparator 20, the SD signal is switched to the original route again to complete the inversion of the transmission data.

[0007]

Embodiments will be described below with reference to the drawings. Figure 1
1 is a configuration diagram of an embodiment of a remote monitoring and control device according to the present invention. In FIG. 1, the same parts as in FIG. In the figure, 10 is a transmission data inversion switching control circuit, which is a transmission data buffer 1
1, comparator 12, flag setter 13, flip-flop 14,
The AND gate 15, the programmable counter 16, the transmission data inversion switching unit 17, the notation gate 18 for inversion of the transmission data clock signal, the setter 19, and the comparator 20. Other configurations are the same as those in FIG.

Next, the operation will be described. The sub-microprocessor 61 first compares the LS for communication with the LS for communication in the occurrence of a transmission data error for comparing the error tests on the receiving side.
The transmission request (RS) signal to the modem 63 is turned on via I62. The modem 63 can perform transmission indicating that the transmission carrier has become stable after a certain period of time when the RS signal is turned on (C
S) The signal is returned to the communication LSI 62 side. When the sub-microprocessor 61 recognizes the SD signal via the communication LSI 62, it starts transmitting the SD signal. SD signal is shown in Figure 3.
LS for communication according to HDLC format as shown in
It is sent out in a serial state via I62, and is input to the transmission data buffer 11 which takes in one byte in synchronization with the transmission data clock signal separately from the modem 63. And HDL in advance
Flag pattern defined by the C transmission procedure (011111
The 1-byte data input to the transmission data buffer 11 and the flag setting device 13 in which 10) is set are compared by the comparator 12. As a result, when a match with the flag pattern is detected, the Q output from the flip-flop 14 is input to the gate (G) of the programmable counter 16. After that, the programmable counter 16 starts counting when there is a count input signal. Further, the Q output from the flip-flop 14 is the AND gate 15
The AND judgment with the transmission data clock frequency is made at. As a result, the transmission data clock signal is input to the programmable counter 16 which starts counting the number of transmission data bits after the start flag of the transmission data (indicates point s and subsequent points in FIG. 3).

As described above, the programmable counter 16 counts the number of transmission data bits after the start flag of transmission data. On the other hand, the setter 19 sets any single or plural bits of the transmission data which are to be judged in advance. The number of bits thus set is compared with the output value from the programmable counter 16 by the comparator 20, and if a match is detected, it is input to the transmission data inversion switching unit 17 which inverts the corresponding transmission data. For example, point x to point y in FIG. 3 (that is, the xth bit to the yth bit of the transmission data from point s).
If an error is generated by inverting the data up to, the setting device 19 first sets from point x to point y. When the comparator 20 detects a match between the number of output bits from the programmable counter 16 and the number of bits from x to y, the comparator 20 outputs the transmission data inversion switching unit 17 during the match detection section. When the transmission data inversion switching unit 17 recognizes the point x, the transmission data (SD) signal route from the communication LSI 62 (route A in FIG. 1) is switched to the route side having the logic inversion (route B in FIG. 1). Is started, and the inversion is continued while the match detection continues, that is, until the point y. When the output of the coincidence detection disappears from the comparator 20, the SD signal is switched to the original route A side again to complete the inversion of the transmission data.

FIG. 2 shows an example of the configuration of the inversion switching section 17. Here, the transmission data clock signal input as the clock (CK) signal of the flip-flop 21 by the transmission data inversion switching unit 17 is inverted by the not gate 22. This is generally the CCITT between the transmission controller and the modem.
V. By using the modem control signals recommended in 24. That is, the V. In the 24 Recommendation, the relationship between the ST signal and the SD signal is defined by the time chart as shown in FIG. 5, and the transmission data clock signal rises at the center of the transmission data. Therefore, when a flip-flop or the like that operates at the rising edge of the clock shown on the circuit side of the transmission data inversion switching unit 17 shown in FIG. 2 is used, a half clock shift occurs at the switching timing, Switching of data inversion cannot be performed properly. On the other hand, when the transmission data clock signal is inverted by the NOT gate 18, the data is smoothly inverted as shown in the time chart of FIG.

Next, using the time chart shown in FIG.
The operation will be described. Assuming that an example of transmission data is shown in FIG. 4 in FIG. 4, the bit section causing the inversion error is changed from point x (that is, the x-th bit from point s in FIG. 3) to point y (that is, point s in FIG. 3). To the y-th bit from) to). 30 shows a transmission data clock signal. Reference numeral 31 indicates an ON / OFF state of the RS signal from the sub microprocessor 61 to the modem 63 via the communication LSI 62 when the transmission data error occurs. Reference numeral 32 shows the ON / OFF state of the CS signal, which represents the stable state of the transmission carrier after a certain time with respect to the ON / OFF of the RS signal from the modem 63. When the sub microprocessor 61 recognizes that the CS signal is on, it starts transmitting the transmission data. 33, a transmission data signal output from the communication LSI 62 to the modem 63 is shown. This is a modem
Apart from 63, it is also a time chart of the transmission data buffer 11 which takes in one byte in synchronization with the transmission data clock signal. In 34, a flag setter 13 that sets a flag pattern (01111110) defined in advance in the HDLC transmission procedure
And the 1-byte data input to the transmission data buffer 11 are compared by the comparator 12, and the output state of the flip-flop 14 indicating the coincidence detection time is shown. When the programmable counter 16 receives the count input signal by the "positive" determination from the flip-flop 14, it starts counting.

At 35, the AND output with the transmission data clock signal, that is, the output of the AND gate 15 is shown based on the judgment of "positive" from the flip-flop 14, and this becomes the count input signal of the programmable counter 16.
Similarly, at 36, the state of the count value of the programmable counter 16 is shown. 36A shows the output of knot gate 18,
This value is input as the clock signal of the flip-flop 21 in the circuit example of the transmission data inversion switching unit 17 shown in FIG. 37 shows the Q output of the flip-flop 21 of FIG. As a result, the flip-flop 21 becomes a "positive" value from the point x to the point y of the inversion period, so that the transmission data is output from the NAND gate 23 as the inversion data as shown at 39. 38 also flip flops
21 Q output is shown. As a result, as shown at 40, the transmission data during the period other than the inversion period is output from the AND gate 22 as it is. When the output of the transmission data ends, the sub-microprocessor 61 turns on the RS signal to the modem 63, and the flip-flop 14, programmable counter 16, and programmable counter 16 under the condition that the CS signal from the modem is turned off.
Clear each of the flip-flops 21. From the above time chart output result, the final transmission data to the modem 63 as shown in the time chart 41 is output from the OR gate 24.

[0013]

As described above, according to the present invention, a transmission data inversion switching control circuit is provided between a communication LSI and a modem without adding a special control signal in addition to the conventional modem control signal. Since it is configured to be provided, it can be easily coupled to the conventional device,
It can also be realized by incorporating a transmission data inversion switching control circuit as a transmission control unit, and is effective when performing a device test such as evaluating the error verification capability of received data by using it as a transmission / transmission error generation device. Become.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a remote monitoring control device according to the present invention.

FIG. 2 is a circuit configuration example of a transmission data inversion switching unit in the above embodiment.

FIG. 3 shows the basics of an HDLC transmission format.

FIG. 4 is a time chart for explaining the operation of the embodiment.

FIG. 5: CCITT V. The relational diagram of SD signal and ST signal recommended in 24.

FIG. 6 is a diagram showing the relationship between a conventional transmission control unit and a modem.

[Explanation of symbols]

 10 Transmission data inversion switching control circuit 11 Transmission data buffer 12, 20 Comparator 13 Flag setting device 14 Flip-flop 15 AND gate 16 Programmable counter 17 Transmission data inversion switching unit 18 Not gate 19 Setting device 61 Sub-microprocessor 62 Communication LSI 63 modem

Claims (1)

[Claims] 1. A transmission protocol process is carried out according to an HDLC transmission procedure, and a control signal of a modem is controlled between a control station (master station) and a controlled station (slave station), and information necessary for monitoring and control is provided. In a remote monitoring control device of a mutual transmission system, a transmission data buffer that captures one byte of a transmission data signal serially output from a communication LSI in response to the transmission procedure in synchronization with a transmission data clock signal, and an HDLC in advance. A flag setter that sets a flag pattern defined by a transmission procedure, a comparator that compares the flag pattern with 1-byte data captured in the transmission data buffer, and the modem when the comparison results match. Among the control signals, the ON condition of the transmission enable signal from the modem with respect to the ON of the transmission request signal to the modem, and the bit data of the transmission data A programmable counter that starts the count, a setter that sets any single or multiple bits of the transmission data after the transmission start flag pattern that is inverted in advance, the setting condition and the bit output from the programmable counter. Remote monitoring characterized by comprising a comparator for comparing count values and a transmission data inversion switching control circuit comprising a transmission data inversion switching section for inverting the corresponding transmission data value when a match between the comparators is detected. Control device.