JPH0653939A - Parity counting system - Google Patents

Abstract

PURPOSE:To reduce a circuit scale required for a signal processing for counting and inserting a parity (B2 byte) to be inserted into a high speed side transmitted signal, and to reduce power consumption. CONSTITUTION:A synchronizing multiplex terminal repeater is constituted of low speed interface packages 51-54, and a high speed interface package 15. Then, counting circuits 41-44 of the B2 byte to be transmitted to a high speed side transmission path HS1, and inserting circuits 31-34 of a multiplexer section overhead(MSOH) including the B2 byte are mounted on the low speed interface packages 51-54, and a multiplex circuit 11 and a repeater section overhead(RSOH) inserting circuit 12 are mounted on the high speed interface package 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity counting system in a terminal multiplex interruption device for digital communication.

[0002]

2. Description of the Related Art CCITTG. 707-709, G.I. 7
SMT (Synchronous Transfer Mode) signal processing recommended by S.
There is an overhead called B2 byte in the signal, the parity calculation result for the STM signal is inserted in the B2 byte at the transmitting side and the parity calculation result calculated at the receiving side and the receiving B
The error between the devices is monitored by comparing with 2 bytes. FIG. 2 shows a block diagram of a synchronous multiplex terminal device that processes B2 bytes sent to a high-speed transmission line. The signal processing in the device of FIG.
4 and the high speed interface package 15.

The flow of signal processing for generating the B2 byte sent to the high speed side is as follows. The signals received from the low speed side transmission lines LS1 to LS4 are subjected to processing such as overhead separation in the low speed side signal processing circuits 21 to 24, respectively. These low speed signals are multiplexed with the high speed signals by the multiplexing circuit 11 of the high speed interface package 15. Overhead such as B2 bytes is inserted in the multiplexed signal by the overhead insertion circuit 12.
The B2 byte to be inserted is a BIP (bit interleave parity) using an even parity with respect to the predetermined data before scrambling in the B2 byte counting circuit 14.
24N (N is STM- where STM-1 signal is multiplexed)
(Representing the multiplicity of N signals). B
The multiplexed signal with 2 bytes of overhead inserted is
After being scrambled by the scramble circuit 13,
It is sent to the high-speed side transmission line HS1.

[0004]

In the above-described conventional B2 byte parity counting method, since the B2 byte to be inserted after the low speed side signal is multiplexed by the high speed interface package 15 is calculated, the high speed interface package 15 The scale of the B2 byte counting circuit 14 in the above becomes large as the multiplexing increases, and the B2 byte counting circuit 14 and the overhead insertion 12 must be operated at a high speed. There is a problem that the power consumption of the interface package 15 increases.

[0005]

According to the parity counting method of the present invention, S is transmitted to the high speed side in the low speed interface package of the synchronous terminal station multiple interruption device for processing the STM signal.
The feature is that after the parity for the TM signal is calculated and inserted, it is multiplexed in the high speed interface package.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, the signal processing for generating the B2 byte sent to the high speed side is as follows. The signals received from the low speed side transmission lines LS1 to LS4 are subjected to low speed side signal processing. Overheads including B2 bytes are inserted into these low speed signals by overhead insertion circuits (MSOH) 31 to 34. The B2 byte counting circuits 41 to 44 count the B2 bytes. In addition,
In the low-speed interface packages 51 to 54, the type of overhead to be inserted differs depending on the position of the mounted slot. For example, if the low-speed interface package 51 corresponds to the multiplexing number 1, the overhead insertion circuit 31 determines that the multiplexing number 1
The overhead (K1, K2 bytes, etc.) defined by the above is inserted, and other low speed interface packages 52 are inserted.
Up to 54, an overhead (natural use byte, etc.) defined by other than the multiplexing number 1 is inserted. The signal in which the overhead including B2 bytes is inserted in the low-speed interface packages 51 to 54 is multiplexed by the multiplexing circuit 11 of the high-speed interface package 15, and then the overhead insertion circuit (RSOH) 12 is used for A1 and A2 bytes. And the like are inserted, scrambled by the scramble circuit 13, and sent to the high-speed side transmission line HSI. Here, the RSOH 12 is mounted on the high-speed interface package 15 because the count range of B1 bytes in the RSOH 12 requires BIP-8 calculation for all the scrambled data.

[0008]

As described above, according to the present invention, B
Since the overhead including the counting of 2 bytes and the B2 byte is inserted by the low speed interface, the circuit scale required for the signal processing performed by the high speed interface can be made smaller than the conventional one. Further, the power consumption required for high-speed signal processing in the conventional method can be distributed to the regular interface, and the power consumption in the high-speed interface package can be reduced as compared with the conventional method.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional method.

[Description of Reference Signs] 11 multiplex circuit 12 overhead insertion circuit (RSOH) 13 scramble circuit 15 high speed interface package 21 to 24 low speed side signal processing circuit 31 to 34 overhead insertion circuit (MSOH) 41 to 44 B2 byte counting circuit 51 to 54 Low speed interface package

Claims (1)

[Claims] 1. A method of calculating and inserting a parity for an STM signal transmitted to a high speed side in a low speed interface package of a synchronous terminal station multiplex interruption device for processing an STM signal, and then multiplexing in a high speed interface package. Characteristic parity counting method.